1

ASIC Design Flow Manual using Cadence Tool Suite

for VLSI Lab – VTU

PART - B

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 LIST OF LAB EXPERIMENTS

Exp. Name of the Experiment Page

No. No.
1 4Bit UP/DOWN Counter Asynchronous Reset Counter 5
 Write Verilog Code
 Verify the Functionality using Test-bench
 Synthesize the Gate Level Netlist by setting Area and Timing Constraints and
also find the Critical Path and Maximum Frequency of Operation
 Perform the above for 32Bit UP/DOWN Counter
2 4Bit Adder 22
 Write Verilog Code
 Verify the Functionality using Test-bench
 Synthesize the design by setting proper constraints and obtain the netlist.
 From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required
3 UART 27
 Write Verilog Code
 Verify the Functionality using Test-bench
 Synthesize the design targeting suitable library and by setting area and timing
constraints
 Tabulate the Area, Power and Delay for the Synthesized netlist
 Identify Critical path
4 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if 37
statement for ALU Behavioral Modeling
 Write Verilog Code
 Verify functionality using Test-bench
 Synthesize the design targeting suitable library and by setting area and timing
constraints
 Tabulate the Area, Power and Delay for the Synthesized netlist
 Identify Critical path
5 Latch and Flip-Flop 42
 Synthesize the design and compare the synthesis report (D, SR. JK)
6 For synthesized netlist carry out the following: 47
 Floor planning
 Placement and Routing
 Record the parameters such as no. of metal layers used for routing, flip
method for placement of standard cells
 Physical Verification and record the DRC and LVS reports
 Generate GDSII

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 Lab 1: 4-bit Up/Down Counter

Aim: To write a verilog code for 4bit up/down asynchronous rest counter and its test-bench for
verification.
 Synthesizing the design by setting area and timing constraint and analyse reports.
 Finding the critical path and maximum frequency of operations
 Recording the power, area requirement and properties of each cell in terms of driving
strength.

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

 An up/down counter is a digital counter which can be set to count either from 0 to
MAX_VALUE or MAX_VALUE to 0.
 The direction of the count(mode) is selected using a single bit input. The module has 3
inputs - clk, reset which is active high and a UpOrDown mode input. The output is Counter
which is 4 bit in size.
 When Up mode is selected, counter counts from 0 to 15 and then again from 0 to 15.
 When Down mode is selected, counter counts from 15 to 0 and then again from 15 to 0.
 Changing mode doesn't reset the Count value to zero.
 You have to apply high value to reset, to reset the Counter output.

Creating a Work space :

 In Desktop Create a folder to do the digital design flow. Right click in the Desktop and
select New Folder as shown in Figure1.2
 It will create a folder like below and name it as Cadence_Digital_Labs

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 Figure No. 1.2: New Folder Creation

Figure No. 1.3: Naming the Folder

Note: Give folder name without any space

 Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

Figure No. 1.4: Creating and Naming the Sub-Directory

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Creating Source Codes

 In the Terminal, type gedit <filename>.v or <filename>.vhdl depending on the HDL

Language you are to use (ex: 4b_up_downCount.v).
 A Blank Document opens up into which the following source code can be typed down.

Note : File name should be with HDL Extension

Verilog code for 4-Bit Up-Down Counter:

//Defining a Timescale for Precision
`timescale 1ns/1ps
//Defining Module
module counter(clk,rst,m,count);
//Defining Inputs and Outputs (4bit)
input clk,rst,m;
output reg [3:0]count;
//The Block is executed when EITHER of positive edge of clock
//Both are independent events or Neg Edge of Rst arrives
always@(posedge clk or negedge rst)
begin
if(!rst)
count=0;
if(m)
count=count+1;
else
count=count-1;
end
endmodule

 Use Save option or Ctrl+S to save the code or click on the save option from the top most
right corner and close the text file.

Creating Test bench:

 Similarly, create your test bench using gedit <filename_tb>.v or <filename_tb>.vhdl to open
a new blank document (4bup_down_count_tb.v).

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Test-bench code for 4-Bit Up-Down Counter:
`timescale 1ns/1ps // Creating Time Scale as in Source Code
module counter_test; // Defining Module Name without Port List
reg clk, rst,m; // Defining I/P as Registers [to Hold Values]
wire [3:0] count; // Defining O/P as Wires [To Probe Waveforms]
Initial
begin
clk=0; // Initializing Clock and Reset
rst=0;#25; // All O/P is 4’b0000 from t=0 to t=25ns.
Rst=1; // Up-Down counting is allowed at posedge clk
end
initial
begin
m=1; // Condition for Up-Count
#600 m=0; // Condition for Down-Count
rst=0;#25;
rst=1;
#500 m=0;
end
counter counter1(clk,m,rst, count); // Instantiation of Source Code
always #5 clk=~clk; // Inverting Clk every 5ns
initial
#1400 $finish; // Finishing Simulation at t=1400ns
endmodule

 Click on the Save option and it will look like the below window and then close the file

Figure No.1.5: Verilog and Tesbench file for 4bit updown counter

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Functional Simulation:

• Invoke the cadence environment by type the below commands

◦ csh (Invokes C-Shell)
◦ source /home/install/cshrc (mention the path of the tools)
◦ (The path of cshrc could vary depending on the installation destination as /home/install/
or /home etc.)
• After this you can see the window like below

Figure No.1.6: Invoke the Cadence Environment

• To Launch Simulation tool

◦ linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG for
the first time for any design
◦ linux:/> nclaunch& // On subsequent calls to NCVERILOG

• It will invoke the nclaunch window for functional simulation we can compile,elaborate and
simulate it using Multiple

Figure No.1.7: Setting Multi-step simulation

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  Select Multiple Step and then select “Create cds.lib File” as shown in below figure
 Click the cds.lib file and save the file by clicking on Save option

Figure No.1.8: cds.lib file Creation

• Save cds.lib file and select the correct option for cds.lib file format based on the HDL
Language and Libraries used.
• Select “Don’t include any libraries (verilog design)” from “New cds.lib file” and click on
“OK” as in below figure
◦ We are simulating verilog design without using any libraries

Figure No. 1.9: Selection of Don’t include any libraries

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 • A Click “OK” in the “nclaunch: Open Design Directory” window as shown in below figure

Figure No. 1.10: Selection of OK for Creating cds.lib file

 A ‘NCLaunch window’ appears as shown in figure below

 Left side you can see the HDL files. Right side of the window has worklib and snapshots
directories listed.
 Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation

Menu
Bar
Tool bar
Icons

Design
Area
File
Browser

Console
Window

Figure no1.11.: Nclaunch Window

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To perform the function simulation, the following three steps are involved Compilation, Elaboration
and Simulation.

Step 1: Compilation:– Process to check the correct Verilog language syntax and usage
Inputs: Supplied are Verilog design and test bench codes

Outputs: Compiled database created in mapped library if successful, generates report else error
reported in log file

Steps for compilation:

1. Create work/library directory (most of the latest simulation tools creates automatically)

2. Map the work to library created (most of the latest simulation tools creates automatically)

3. Run the compile command with compile options

i.e Cadence IES command for compile: ncverilog +access+rwc -compile design.v

• Left side select the file and in Tools : launch verilog compiler with current selection will get
enable. Click it to compile the code
• Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation

ncvlog for
Verilog Designs

Figure No1.12: Compilation Launch Option

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 • After compilation it will come under worklib you can see in right side window.

Figure No1.13: Compiled database in worklib

• Select the test bench and compile it. It will come under worklib. Under Worklib you can see
the module and test-bench.

Figure No1.14: Compiled Test-bench Database in Worklib

The cds.lib file is an ASCII text file. It defines which libraries are accessible and where they are
located. It contains statements that map logical library names to their physical directory paths. For
this Design, you will define a library called “worklib”
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Step 2: Elaboration:– To check the port connections in hierarchical design
Inputs: Top level design / test bench Verilog codes

Outputs: Elaborate database updated in mapped library if successful, generates report else error
reported in log file

Steps for elaboration – Run the elaboration command with elaborate options

1. It builds the module hierarchy

2. Binds modules to module instances

3. Computes parameter values

4. Checks for hierarchical names conflicts

5. It also establishes net connectivity and prepares all of this for simulation
i.e Cadence IES command for elaboration: ncverilog +access+rwc -elaborate design.v

ncelab for Verilog

Designs

Figure No1.15: Elaboration Launch Option

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 • After elaboration the file will come under snapshot. Select the test bench and elaborate it.

ncsim for
Verilog Designs

Figure No1.16: Simulation launch option

Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe the
output behaviour

Inputs: Compiled and Elaborated top level module name

Outputs: Simulation log file, waveforms for debugging

Simulation allow to dump design and test bench signals into a waveform

Steps for simulation – Run the simulation command with simulator options

i.e Cadence IES command to run in GUI mode: ncsim -gui worklib.top level entity name
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 Run simulation Interrupt Simulation Zoom in, Zoom out

Figure No1.17: Simulation Waveform Window

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b) Synthesize the design using Constraints and analyse reports, critical path and
Max Operating Frequency.

Step 1: Getting Started

 Make sure you close out all the Incisive tool windows first.
 Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (Synopsis Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

 In your terminal type “gedit counter_top.sdc” to create an SDC File if you do not have one.
 The SDC File must contain the following commands;

i. create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]

ii. set_clock_transition -rise 0.1 [get_clocks "clk"]
iii. set_clock_transition -fall 0.1 [get_clocks "clk"]
iv. set_clock_uncertainty 0.01 [get_ports "clk"]
v. set_input_delay -max 0.8 [get_ports "rst"] -clock [get_clocks "clk"]
vi. set_output_delay -max 0.8 [get_ports "count"] -clock [get_clocks "clk"]
vii. set_input_transition 0.12 [all_inputs]
viii. set_load 0.15 [all_outputs]
ix. set_max_fanout 30.00 [current_design]

i→ Creates a Clock named “clk” with Time Period 2ns and On Time from t=0 to t=1.
ii, iii → Sets Clock Rise and Fall time to 100ps.
iv → Sets Clock Uncertainty to 10ps.
v, vi → Sets the maximum limit for I/O port delay to 1ps.

Figure No1.18: SDC file with .sdc file Extension

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Step 3 : Performing Synthesis

 The Liberty files are present in the below path,

/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/

 The Available technology nodes are 180nm ,90nm and 45nm.

 In the terminal, initialise the tools with the following commands if a new terminal is being
used.
◦ csh
◦ source /home/install/cshrc
 The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
 The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl counter.v
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Effort level to medium for generic, mapping
and optimization
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation
11. report_timing > counter_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > counter_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > counter_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > counter_netlist.v //Creates readable Netlist File
15. write_sdc > counter_sdc.sdc //Creates Block Level SDC

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 Figure No1.19: Genus Script file with .tcl file Extension

Synthesis RTL Schematic :

Figure No1.20: Schematic Capture of 4bit UpDown Counter

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Commands 1-5 are intended for Synthesis process while 11-15 for Generating reports and Outputs.

Note :-
1) report_timing gives you the path with highest failing slack where
Setup Slack = Required Time – Arrival Time.

2) Worst Setup Slack ==> Highest Arrival time ==> Highest Propagation Delay.

3) Maximum Clock Frequency = 1/ (Max Data Path Delay – Min Clock Path Delay + Tsetup)

All the Information can be gathered from report_timing.

4) The Cells given in the netlist can be checked in the .lib files for their properties.

c) Compilation, Simulation and Synthesis of 32-bit Up/Down Counter.

Source Code :

`timescale 1ns/1ps //Defining a Timescale for Precision

module counter(clk,rst,m,count); //Defining Module and Port List
input clk,rst,m; //Defining Inputs
output reg [31:0]count; //Defining 4-bit Output as Reg type
always@(posedge clk or negedge rst) //The Block is executed when
begin //EITHER of positive edge of clock
if(!rst) //or Neg Edge of Rst arrives
count=0; // Both are independent events
if(m)
count=count+1;
else
count=count-1;
end
endmodule

Test Bench :
`timescale 1ns/1ps //Creating Time Scale as in Source Code
module counter_test; //Defining Module Name without Port List
reg clk, rst,m; //Defining I/P as Registers [to Hold Values]
wire [31:0] count; //Defining O/P as Wires [To Probe Waveforms]
initial
begin
clk=0; //Initializing Clock and Reset
rst=0;#25; //All O/P is 4’b0000 from t=0 to t=25ns.
rst=1; //Up-Down counting is allowed at posedge clk
end
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initial
begin
m=1; //Condition for Up-Count
#600 m=0; //Condition for Down-Count
rst=0;#25;
rst=1;
#500 m=0;
end
counter counter1(clk,m,rst, count); //Instantiation of Source Code
always #5 clk=~clk; //Inverting Clk every 5ns
initial
#1400 $finish; //Finishing Simulation at t=1400ns
endmodule

Waveform :

Figure No1.21: Simulation Waveform Window

The procedure for Simulation and Synthesis remains same as mentioned earlier.

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 Lab 2: 4-Bit Adder

Aim: To write a verilog code for 4bit adder and verify the functionality using Test bench.
• Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and total area
requirement.

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

A full adder is a combinational circuit that performs the arithmetic sum of three input bits
Ai, addend Bi and carry in C in from the previous adder. Its results contain the sum Si and the carry
out, C out to the next stage. So to design a 4-bit adder circuit we start by designing the 1 –bit full
adder then connecting the four 1-bit full adders to get the 4-bit adder as shown in the diagram
below. For the 1-bit full adder, the design begins by drawing the Truth Table for the three input and
the corresponding output SUM and CARRY.

Figure No2.1: Diagram and truth table of full adder

Figure No2.2: Diagram of 4 Bit Adder

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 Creating a Work space :
 Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

a) Verify the Functionality

 Three Codes shall be written for implementation of 4-bit Adder as follows,
◦ fa.v → Single Bit 3-Input Full Adder [Sub-Module / Function]
◦ fa_4bit.v → Top Module for Adding 4-bit Inputs.
◦ fa_test.v → Test bench
Source Code – fa.v :-
module full_adder( A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
assign COUT = (A&B) | (CIN&(A^B));
endmodule

Source Code – fa_4bit.v :-

module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,[3:0] B,C0;
output [3:0] S,C4;
wire C1,C2,C3;
full_adder fa0 (A[0],B[0],C0,S[0],C1);
full_adder fa1 (A[1],B[1],C1,S[1],C2);
full_adder fa2 (A[2],B[2],C2,S[2],C3);
full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

Test Bench – fa_test.v :-

module test_4_bit;

reg [3:0] A;
reg [3:0] B;
reg C0;
wire [3:0] S;
wire C4;
four_bit_adder dut(A,B,C0,S,C4);
initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
end
initial
#50 $finish;
endmodule

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Waveform :

Figure No2.3: Simulation waveform of 4bit Adder

b) Synthesis and Report/Output Analysis

Step 1: Getting Started

 Make sure you close out all the Incisive tool windows first.
 Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (Synopsis Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

 As the Full Adder Program does not contain any Clock, SDC can be skipped as an Input if
you wish to, else you could include only Area Constraints in form of commands during
synthesis such as,
set_dont_use *XL (Indicating not to use Larger Cells)

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Step 3 : Performing Synthesis
 The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
 The Available technology nodes are 180nm ,90nm and 45nm.
 In the terminal, initialise the tools with the following commands if a new terminal is being
used.
◦ csh
◦ source /home/install/cshrc
 The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
 The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {4bi_adder.v} //Reading multiple Verilog Files
3. elaborate
4. set_top_module four_bit_adder //Differentiating Top & Sub Module
5. set_dont_use *XL //Dont Use Cells with High Driving Strength
6. set_db syn_generic_effort medium //Setting effort medium
7. set_db syn_map_effort medium
8. set_db syn_opt_effort medium
9. syn_generic
10. syn_map
11. syn_opt
//Performing Synthesis Mapping and Optimisation
12. report_timing -unconstrained > adder_timing.rep
//Generates Timing report for worst datapath and dumps into file
//-unconstrained is to be given as no timing constraints are given
13. report_area > adder_area.rep
//Generates Synthesis Area report and dumps into a file
14. report_power > adder_power.rep
//Generates Power Report [Pre-Layout]
15. write_hdl > adder_netlist.v //Creates readable Netlist File
16. write_sdc > adder_sdc.sdc //Creates Block Level SDC
17. report_qor > adder_qor.rpt // Critical slack path

Commands 1-11 are intended for Synthesis process while 12-17 for Generating reports and Outputs.

Note 1:-

1. The Cells given in the netlist can be checked in the .lib files for their properties.
2. The Max Operating Frequency does not apply for Purely Combinational Circuit.

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Synthesis RTL Schematic :

Figure No2.4: Schematic Capture of 4bit Adder

Some Common Constraints are given below for reference

Figure No2.5: Common SDC Constraints

Note 2:-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do
not overwrite the earlier ones.

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 Lab 3: UART

Aim: Write a verilog code for UART and carry out the following:
• To Verify the Functionality using test Bench
• Synthesize Design using constraints
• Tabulate Reports using various Constraints
• Identify Critical Path and calculate Max Operating Frequency

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

The UART is “Universal Asynchronous Receiver/Transmitter”, and it is an inbuilt IC within

a micro-controller but not like a communication protocol (I2C & SPI). The main function of UART
is to serial data communication. In UART, the communication between two devices can be done in
two ways namely serial data communication and parallel data communication.
The transmitter section includes three blocks namely transmit hold register, shift register and
also control logic. Likewise, the receiver section includes a receive hold register, shift register, and
control logic. These two sections are commonly provided by a baud-rate-generator. This generator
is used for generating the speed when the transmitter section & receiver section has to transmit or
receive the data.

Figure No3.1.: Block Diagram of UART

Creating a Workspace :
 Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

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a) Functional Verification using Test Bench
Source Code – Transmitter :

// This code contains the UART Transmitter. This transmitter is able

// to transmit 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When transmit is complete o_Tx_done will be
// driven high for one clock cycle.
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module UART_TX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_TX_DV,
input [7:0] i_TX_Byte,
output o_TX_Active,
output reg o_TX_Serial,
output o_TX_Done
);

parameter IDLE = 3'b000;

parameter TX_START_BIT = 3'b001;
parameter TX_DATA_BITS = 3'b010;
parameter TX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;
reg [2:0] r_SM_Main = 0;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_TX_Data = 0;
reg r_TX_Done = 0;
reg r_TX_Active = 0;

always @(posedge i_Clock)

begin

case (r_SM_Main)
IDLE :
begin
o_TX_Serial <= 1'b1; // Drive Line High for Idle
r_TX_Done <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
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 if (i_TX_DV == 1'b1)
begin
r_TX_Active <= 1'b1;
r_TX_Data <= i_TX_Byte;
r_SM_Main <= TX_START_BIT;
end
else
r_SM_Main <= IDLE;
end // case: IDLE

// Send out Start Bit. Start bit = 0

TX_START_BIT :
begin
o_TX_Serial <= 1'b0;

// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= TX_DATA_BITS;
end
end // case: TX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish

TX_DATA_BITS :
begin
o_TX_Serial <= r_TX_Data[r_Bit_Index];

if (r_Clock_Count < CLKS_PER_BIT-1)

begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;

// Check if we have sent out all bits

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 if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= TX_STOP_BIT;
end
end
end // case: TX_DATA_BITS

// Send out Stop bit. Stop bit = 1

TX_STOP_BIT :
begin
o_TX_Serial <= 1'b1;

// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_STOP_BIT;
end
else
begin
r_TX_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
r_TX_Active <= 1'b0;
end
end // case: TX_STOP_BIT

// Stay here 1 clock

CLEANUP :
begin
r_TX_Done <= 1'b1;
r_SM_Main <= IDLE;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_TX_Active = r_TX_Active;
assign o_TX_Done = r_TX_Done;
endmodule
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Source Code – Receiver :
// This file contains the UART Receiver. This receiver is able to
// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete o_rx_dv will be
// driven high for one clock cycle.
//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module UART_RX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_RX_Serial,
output o_RX_DV,
output [7:0] o_RX_Byte
);

parameter IDLE = 3'b000;

parameter RX_START_BIT = 3'b001;
parameter RX_DATA_BITS = 3'b010;
parameter RX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;

reg [7:0] r_Clock_Count = 0;

reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_RX_Byte = 0;
reg r_RX_DV = 0;
reg [2:0] r_SM_Main = 0;

// Purpose: Control RX state machine

always @(posedge i_Clock)
begin

case (r_SM_Main)
IDLE :

begin
r_RX_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;

31
 if (i_RX_Serial == 1'b0) // Start bit detected
r_SM_Main <= RX_START_BIT;
else
r_SM_Main <= IDLE;
end

// Check middle of start bit to make sure it's still low

RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (i_RX_Serial == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= RX_DATA_BITS;
end
else
r_SM_Main <= IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_START_BIT;
end
end // case: RX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles to sample serial data

RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_RX_Byte[r_Bit_Index] <= i_RX_Serial;

// Check if we have received all bits

if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= RX_DATA_BITS;
end

32
else
begin
r_Bit_Index <= 0;
r_SM_Main <= RX_STOP_BIT;
end
end
end // case: RX_DATA_BITS

// Receive Stop bit. Stop bit = 1

RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_STOP_BIT;
end
else
begin
r_RX_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
end
end // case: RX_STOP_BIT

// Stay here 1 clock

CLEANUP :
begin
r_SM_Main <= IDLE;
r_RX_DV <= 1'b0;
end

default :
r_SM_Main <= IDLE;

endcase
end

assign o_RX_DV = r_RX_DV;

assign o_RX_Byte = r_RX_Byte;
endmodule // UART_RX

33
Test bench :
// This testbench will exercise the UART RX.
// It sends out byte 0x37, and ensures the RX receives it correctly.
`timescale 1ns/10ps

`include "uart_tx.v"
`include "uart_rx.v"

module UART_TB ();

// Testbench uses a 25 MHz clock

// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per Bit.
parameter c_CLOCK_PERIOD_NS = 40;
parameter c_CLKS_PER_BIT = 217;
parameter c_BIT_PERIOD = 8600;

reg r_Clock = 0;
reg r_TX_DV = 0;
wire w_TX_Active, w_UART_Line;
wire w_TX_Serial;
reg [7:0] r_TX_Byte = 0;
wire [7:0] w_RX_Byte;

UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst

(.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),
.o_RX_Byte(w_RX_Byte)
);

UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst

(.i_Clock(r_Clock),
.i_TX_DV(r_TX_DV),
.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);
// Keeps the UART Receive input high (default) when
// UART transmitter is not active
assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;
always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
34
 // Main Testing:
initial
begin
// Tell UART to send a command (exercise TX)
@(posedge r_Clock);
@(posedge r_Clock);
r_TX_DV <= 1'b1;
r_TX_Byte <= 8'h3F;
@(posedge r_Clock);
r_TX_DV <= 1'b0;
end
endmodule

Waveform :

Figure No3.2: Simulation Waveform of UART

b) Synthesize the Design

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {uart_tx.v / uart_rx.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
35
 8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation
11. report_timing > uart_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > uart_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. report_qor > uart_qor.rep
15. write_hdl > uart_netlist.v
//Creates readable Netlist File
16. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

Synthesis RTL Schematic :

Figure No3.3: Schematic Capture of UART Design

Note :-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do
not overwrite the earlier ones.

36
 Lab 4: 32-Bit ALU
Aim: Write a verilog code for 32 bit ALU supporting four logical and four arithmetic operations,
use case statement and if statement for ALU behavioral modeling.
• To Verify the Functionality using Test Bench
• Synthesize and compare the results using if and case statements
• Identify Critical Path and constraints

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the
following task like addition subtraction, multi-fiction and logical operations. As the input is given in
32 bit we get 32 bit output. The arithmetic will show only one output at a time so a selector is
necessary to select one of the operator.

Figure No4.1: Block Diagram of 32 Bit ALU

Creating a Work space :

 Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

37
 a) To Verify the Functionality using Test Bench

Source Code – Using Case Statement :

module alu_32bit_case(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b010:y=a+b; //Addition
3'b011:y=a-b; //Subtraction
3'b100:y=a*b; //Multiply
default:y=32'bx;
endcase
end
endmodule

Test Bench :

module alu_32bit_tb_case;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule
38
Source Code - Using If Statement :

module alu_32bit_if(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
if(f==3'b000)
y=a&b; //AND Operation
else if (f==3'b001)
y=a|b; //OR Operation
else if (f==3'b010)
y=a+b; //Addition
else if (f==3'b011)
y=a-b; //Subtraction
else if (f==3'b100)
y=a*b; //Multiply
else
y=32'bx;
end
endmodule

Test bench :

module alu_32bit_tb_if;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule
39
Wave Forms :

Figure No4.2: Simulation Waveform of 32-Bit ALU

b) Synthesize Design
 Run the synthesis Process one time for each code and make sure the output File names are
changed accordingly.

Synthesis Process :
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {alu_32bit_if.v (OR) alu_32bit_case.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Optional-Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
//Performing Synthesis Mapping and Optimisation
11. report_timing > alu_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > alu_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > uart_netlist.v
//Creates readable Netlist File
15. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

40
Synthesis RTL Schematic :

Figure No4.3: Schematic Capture of 32-Bit ALU

Note :-

1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do
not overwrite the earlier ones.

41
 Lab 5: Latches and Flip Flops

Aim: Write a verilog code for Latch and Flip-flops (D, SR, JK), Synthesize the design and
compare the synthesis report.

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

Latches and flip-flops are the basic elements for storing information. One latch or flip-flop
can store one bit of information. The main difference between latches and flip-flops is that for
latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted.
In other words, when they are enabled, their content changes immediately when their inputs
change. Flip-flops, on the other hand, have their content change only either at the rising or falling
edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising
or falling edge of the clock, the flip-flop content remains constant even if the input changes.
There are basically four main types of latches and flip-flops: SR, D, and JK. The major
differences in these flip-flop types are the number of inputs they have and how they change state.
For each type, there are also different variations that enhance their operations.

Example: D-Flip-flop

Figure No5.1: Block Diagram and Truth Table of D-Flip Flop

Creating a Work space :

 Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

42
a) Verilog Codes for D-Flip Flop, JK-Flip Flop and SR-Flip Flop.

Source code for D-Flip Flop :

module DFF( Q,Qbar,D,Clk,Reset);
output reg Q;
output Qbar;
input D,Clk,Reset;
always @(posedge Clk)
begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q;
endmodule

Source code for D-Latch :

module DFF( Q,Qbar,D,en,Reset);
output reg Q;
output Qbar;
input D,en,Reset;
assign Reset = ~D;
always @(en)
begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q;
endmodule

Source code for SR Flip Flop :

module Main(S,R,clk,Q,Qbar);
input S,R,clk;
output Q,Qbar;
reg M,N;
always @(posedge clk)
begin
M = !(S & clk);
N = !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);
endmodule
43
Source Code for SR Latch :
module Main(S,R,en,Q,Qbar);
input S,R,en;
output Q,Qbar;
reg M,N;
always @(en)
begin
M <= !(S & clk);
N <= !(R & clk);
end
assign Q <= !(M & Qbar);
assign Qbar <= !(N & Q);
endmodule

Source Code for JK Flip Flop :

module jkff(J, K, clk, Q);
input J, K, clk;
output reg Q,Qm;
always @(posedge clk)
begin
if(J == 1 && K == 0)
Qm = 1;
else if(J == 0 && K == 1)
Qm = 0;
else if(J == 1 && K == 1)
Qm = ~Qm;
end
endmodule

Source of JK Latch :
module jkff(J, K, en, Q);
input J, K, en;
output reg Q,Qm;
always @(en)
begin
if(J == 1 && K == 0)
Qm <= 1;
else if(J == 0 && K == 1)
Qm <= 0;
else if(J == 1 && K == 1)
Qm <= ~Qm;
end
endmodule

44
Wave Forms for D-Flip Flop:

Figure No5.2: Simulation Waveform of D Flip-Flop

b) Synthesize the Design & Comparing Reports

Synthesis Commands :
1. read_libs /home/install_run/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl dff.v
3. elaborate
4. read_sdc constraints_top.sdc
5. set_db syn_generic_effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
11. report_timing > dff_timing.rep
12. report_area > dff_area.rep
13. report_power > dff_power.rep
14. write_hdl > dff_netlist.v
15. write_sdc > dff_sdc.sdc

Example for SDC:

Figure No5.3: SDC for a D Flip-Flop

The Above is the example SDC for a D Flip Flop

45
 Figure No5.4: SDC file for a D Latch

The above is an Example for SDC File for D Latch.

Synthesis RTL Schematic :

Figure No5.5: Schematic Capture of D Flip-Flop

Note :-

1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do
not overwrite the earlier ones.

46
 Lab 6: Physical Design

Aim: For the synthesized netlist carry out the following any two above experiments:
• Floor planning, identify the placement of pads, placement and Routing

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus
 Physical Design: Innovus

Mandatory Inputs for PD:

1. Gate Level Netlist [Output of Synthesis]
2. Block Level SDC [Output of Synthesis]
3. Liberty Files (.lib)
4. LEF Files (Layer Exchange Format)

Expected Outputs from PD:

1. GDS II File (Graphical Data Stream for Information Interchange – Feed In for Fabrication
Unit).
2. SPEF, SDF

 Make sure the Synthesis for the target design is done and open a terminal from the
corresponding workspace.
 Initiate the Cadence tools and cmd :innovus (Press Enter)
 For Innovus tool, a GUI opens and also the terminal enters into innovus command prompt
where in the tool commands can be entered.

Physical Design involves 5 stages as following :

After Importing Design,
→ Floor Planning
→ Power Planning
→ Placement
→ CTS (Clock Tree Synthesis)
→ RoutingModule

Importing Design

To Import Design, all the Mandatory Inputs are to be loaded and this can be done either using script
files named with .globals and .view/.tcl or through GUI as shown below.

The target design considered here is 4bit up down counter design

The procedure shall remain the same for any other design from the above discussed experiments.

47
Note :

1. For Synthesis, slow.lib was read as input. Each liberty file contains a pre-defined Process,
Voltage and Temperature (PVT) values which impact the ease of charge movement.
2. Process, Voltage and Temperature individually affect the ease of currents as depicted below.

3. Hence, slow.lib contains PVT combination (corner) with slow charge movement =>
Maximum Delay => Worst Performance
4. Similarly, fast.lib contains PVT Combination applicable across its designs to give Fast
charge movement => Minimum Delay => Best Performance.
5. When these corners are collaborated with the sdc, they can be used to analyse timing for
setup in the worst case and hold in the best case.
6. All these analysis views are to be manually created either in the form of script or using the
GUI.

Figure No6.1: Script file of Default.globals file

48
 Figure No6.2: Script file of Default.view (or) Default.tcl file

Note : Check the paths to properly read in the input files.

 Else, if you would like to import your design using GUI, open the Innovus tool and from the
GUI, go to File → Import Design.
 A new pop-up window appears.
 First load the netlist. You can browse for the file and select “Top cell : Auto Assign”.

Similarly select your lef files from /home/install/FOUNDRY/digital/90nm/dig/lef/ as shown below.

49
Once both the Netlist and LEF Files are loaded, your import design window is as follows.

 In order to load the Liberty File and SDC, create delay corners and analysis view, select the
“Create Analysis Configuration” option at the bottom.

50
  An MMMC browser Pops Up.

The order of adding the MMMC Objects is as follows.

1. Library Sets
2. RC Corners
3. Delay Corners
4. Constraints (SDC)

Once all of them are added, Analysis Views are created and assigned to Setup and Hold.

In order to add any of the objects, make a right click on the corresponding label → Select New.

 Adding Liberty Files under “Library Sets”

51
  Similarly, add fast.lib with a label Fast or any identifier of your own.

 Adding RC Corners can also be done in a similar process. The temperature value can be
found under the corresponding liberty file. Also, cap table and RC Tech files can be added
from Foundry where available.
52
  Delay Corners are formed by combining Library Sets with RC Corners.
 An example is shown below.

53
  Similarly, SDC can be read in under the MMMC Object of “Constraints”.

54
  Analysis Views are formed from combinations of SDC and Delay Corner.

 Once “Best” and “Worst” Analysis views are created, assign them to Setup and Hold.

 Once all the process is done, Click on “Save&Close” and save the script generated with any
name of your choice.
 Make sure the file extension remains .view or .tcl
 After saving the script, go back to Import Design window and Click “OK” to load your
design.

55
  Add Power and Ground Net names (Identifiers) under Import design window.
56
  A rectangular or square box appears in your GUI if and only if all the inputs are read
properly.

 If the box does not appear, check for errors in your log (Either on terminal or log file from
pwd)

57
  The internal area of the box is called “Core Area”.
 The horizontal lines running along the width of Core are “Standard Cell Rows”. Every
alternate of them are marked indicating alternate VDD and VSS rows.
 This setup is called “Flipped Standard Cell Rows”.

→ Floorplan

Steps under Floorplan :

1. Aspect Ratio [Ratio of Vertical Height to Horizontal Width of Core]

2. Core Utilisation [The total Core Area % to be used for Floor Planning]
3. Channel Spacing between Core Boundary to IO Boundary

 Select Floorplan → Specify Floorplan to modify/add concerned values to the above Factors.
On adding/modifying the concerned values, the core area is also modified.

58
  The Yellow patch on the Left Bottom are the group of “Unassigned pins” which are to be
placed along the IO Boundary along with the Standard Cells [Gates].

→ Power Planning

Steps under Power Planning :

1. Connect Global Net Connects
2. Adding Power Rings
3. Adding Power Strings
4. Special Route

Under Connect Global Net Connects, we create two pins, one for VDD and one for VSS connecting
them to corresponding Global Nets as mentioned in Globals file / Power and Ground Nets.

1. Select Power → Connect Global Nets.. to create “Pin” and “Connect to Global Net” as
shown and use “Add to list”.
2. Click on “Apply” to direct the tool in enforcing the Pins and Net connects to Design and
then Close the window.

59
  In order to Tap in Power from a distant Power supply, Wider Nets and Parallel connections
improve efficiency. Moreover, the cells that would be placed inside the core area are
expected to have shorter Nets for lower resistance.
 Hence Power Rings [Around Core Boundary] and Power Stripes [Across Core Boundary]
are added which satisfies the above conditions.
 Select Power → Power Planning → Add Rings to add Power rings ‘around Core Boundary’.

60
  Select the Nets from Browse option OR Directly type in the Global Net Names separated by
a space being Case and Spelling Sensitive.
 Select the Highest Metals marked ‘H’ [Horizontal] for Top and Bottom and Metals marked
‘V’ [Vertical] for Right and Bottom. This is because Highest metals have Highest Widths
and thus Lowest Resistance.
 Click on Update after the selection and “Set Offset : Centre in Channel” in order to get the
Minimum Width and Minimum Spacing of the corresponding Metals and then Click “OK”.
 Similarly, Power Stripes are added using similar content to that of Power Rings.

Factors to be considered under Power Stripes :

→ Nets
→ Metal and It’s Direction
→ Width and Spacing [Updated]
→ Set to Set Distance = ( Minimum Width of Metal + Min. Spacing ) x 2

61
  On adding Power Stripes, The Power mesh setup is complete as shown. However, There are
no Vias that could connect Metal 9 or Metal 8 directly with Metal 1 [VDD or VSS of
Standard Cells are generally made up of Metal 1].
 The connection between the Highest and Lowest Metals is done through Stacking of Vias
done using “Special Route”.
 To perform Special Route, Select Route → Special Route → Add Nets → OK.
 After the Special Route is complete, all the Standard Cell Rows turn to the Color coded for
Metal 1 as shown below.

The complete Power Planning process makes sure Every Standard Cell receives enough power to
operate smoothly.

→ Pre – Placement :

 After Power Planning, a few Physical Cells are added namely, End Caps and Well Taps.
 End Caps : They are Physical Cells which are added to the Left and Right Core Boundaries
acting as blockages to avoid Standard Cells from moving out of boundary.
 Well Taps : They act like Shunt Resistance to avoid Latch Up effects.

62
To add End Caps, Select Place → Physical Cell → Add End Caps and “Select” the FILL’s from the
available list.

 Higher Fills have Higher Widths. As shown Below, The End Caps are added below your
Power Mesh.

 To add Well Taps, Select Place → Physical Cell → Add Well Tap → Select →FillX [X →
Strength of Fill = 1,2,4 etc] → Distance Interval [Could be given in range of 30-45u] → OK

63
→ Placement
1. The Placement stage deals with Placing of Standard Cells as well as Pins.
2. Select Place → Place Standard Cell → Run Full Placement → Mode → Enable ‘Place I/O
Pins’ → OK → OK .

64
  All the Standard Cells and Pins are placed as per the communication between them, i.e.,
Two communicating Cells are placed as close as possible so that shorter Net lengths can be
used for connections as Shorter Net Lengths enable Better Timing Results.

 You can toggle the Layer Visibility from the list on the Right. The List of Layers available
are shown on the right under “Layer” tab with colour coding.
65
→ Report Generation and Optimization :
1. Timing Report :
1. To generate Timing Report, Timing → Report Timing → Design Stage – PreCTS
2. Analysis Type – Setup → OK
3. The Timing report Summary can be seen on the Terminal.
2. Area Report :
1. cmd : report_area
3. Power Report :
1. cmd : report_power

66
  In case of any Violating paths, the design could be optimized in the following way.
 To optimize the Design, Select ECO → Optimize Design → Design Stage [PreCTS] →
Optimization Type – Setup → OK

 After you run the optimization, the terminal displays the latest Timing report and updated
area and power reports can be checked.

 This step Optimizes your design in terms of Timing, Area and Power. You can Generate
Timing, Area, Power in similar way as above report Post – Optimization to compare the
Reports.

Clock Tree Synthesis

 The CTS Stage is meant to build a Clock Distribution Network such that every Register
(Flip Flop) acquires Clock at the same time (Atleast Approximately) to keep them in proper
communication.
 A Script can be used to Build the Clock Tree as follows :

67
  Source the Script as shown in the above snapshot through the Terminal and then Select
Clock → CCOpt Clock Tree Debugger → OK to build and view clock tree.

 The Red Boxes are the Clock Pins of various Flip Flops in the Design while Yellow
Pentagon on the top represents Clock Source.
 The Clock Tree is built with Clock Buffers and Clock Inverters added to boost up the Clock
Signal.
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Report Generation and Design Optimization :

 CTS Stage adds real clock into the Design and hence “Hold” Analysis also becomes
prominent. Hence, Optimizations can be done for both Setup & Hold, Timing Reports are to
be Generated for Setup and Hold Individually.

Setup Timing Analysis :

Hold Timing Analysis :

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Routing :

1. All the net connections shown in the GUI till CTS are only based on the Logical
connectivity.
2. These connections are to be replaced with real Metals avoiding Opens, Shorts, Signal
Integrity [Cross Talks], Antenna Violations etc.
3. To run Routing, Select Route → Nano Route → Route and enable Timing Driven and SI
Driven for Design Physical Efficiency and Reliability.

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Area and Power Reports :
Use the commands report_area and report_power for Area and Power Reports respectively.

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  As an alternate to the setAnalysisMode command, you can use the GUI at Tools → Set
Mode → Set Analysis Mode → Select On-Chip-Variation and CPPR.

 The Report generation is same as shown prior to Design Optimization.

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It is recommended to save Netlist and Design at every stage.

To restore a Design Data Base, type source <DesignName>.enc in the terminal.

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Physical Verification – Capturing DRC and LVS:

 After saving the routed Database, you can proceed for Physical Verification and capture the
DRC and LVS reports.
 Inputs Required – DRC :
◦ Technology Library and Rule Set
◦ GDS format giles of all Standard Cells (Given by Cadence at /home/install/FOUNDRY/
90nm/dig/gds for 90nm Tech node)
 Outputs – DRC :
◦ DRC Violation Report
◦ Physical Netlist (Optional)
From the Innovus GUI, select PVS → Run DRC to open the “DRC Submission Form”.

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The DRC Run Submission Form begins with mentioning the Run Directory. The Run Directory is
the location where all the logs, reports and other files concerned with PVS are saved.

The technology Library is to be loaded under “Rules tab”.

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  The Technology Library is specific for PVS Tool and technology node on which the design
is created.
 On reading the tech lib, the rule set is loaded and the corresponding fabrication rules are
read in to be checked against the design.

 The GDS format files of all standard cells available with the corresponding technology node
are also provided by the vendor. Select all of them to add.

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  The output report can be named and saved as shown.

 Hit “Submit” to run the DRC and the following windows appear.

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  All the list of DRC Errors can be seen in the above window of which the location of the
DRC Violation occuring can be highlighted dealing one to one.

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  For example, in the above shown snapshot, the errors associated
with N-Implant can be seen. (Select a error occurrence and click on the right arrow below to
highlight/zoom in the location.)
 You can save the DRC Run as a “Preset” file to rerun the DRC if required at a later point of
time.
 Saving/loading the Preset File is shown below.

 Loading a Preset file is shown below.

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 Note : A Physical Netlist can be saved after the DRC Run as shown below.

 Inputs Required – LVS :

◦ Technology Library
◦ Standard Cell GDS Files
◦ Spice Netlist of all Standard Cells (Provided by Library Vendor)
 Outputs – LVS :
◦ LVS Match/Mismatch Report

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  From the Innovus GUI, Select PVS → Run LVS to open the LVS run submission form.

 Provide the Run directory and log file name (Along with path – Optional)
 Load the Tech Lib, GDS Files and Spice Netlist of all Standard Cells under the
corresponding technology node.

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  On successful completion of LVS Run, the following windows appear.
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  You can create a GDS file along with Stream out file either using the GUI as File → Save →
GDS/Oasis or use the following command.
 Cmd : streamOut <GDSFileName>.gds -streamOut <streamOut>.map or
 innovus 1> streamOut design_GDS.gds -mapFile streamOut2.map -libName Mydesign -
merge {/home/install/FOUNDRY/digital/90nm/dig/gds/*.gds} -units 2000 -mode ALL

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