2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2018), MAY 18th

& 19th 2018

Performance Analysis of Various Topologies of

Common Source Low Noise Amplifier (CS-LNA) at
90nm Technology
Lekshmi Vimalan Devi S
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Amrita Vishwa Vidyapeetham, Amritapuri, India Amrita Vishwa Vidyapeetham, Amritapuri, India
[email protected] [email protected].

Abstract—One of the basic components in any radio frequency In this paper, the LNA is designed for GPS applications
(RF) communication systems is Low Noise Amplifier (LNA). This with frequency 1.57GHz at 90 nm CMOS technology[9]. This
paper compares various Common Source Low Noise Amplifier paper presents three main topologies of common source LNA
(CS-LNA) topologies based on their performance analysis. The (CS-LNA) for performance comparison. In this paper, various
three main common source LNA topologies that has been taken design parameters of LNA are briefly described in Section II,
for the performance analyses are an inductively loaded Common the basic topologies of LNA are introduced in Section III, the
Source LNA , a CS-LNA with feedback resistor and a CS-LNA simulation results obtained are shown in Section IV and the
cascode stage with inductive source degeneration. In this paper, conclusion is reported in Section V.
all the three LNA’s are designed for 1.57 GHz frequency which is
generally used for Global Positioning System (GPS) applications.
The performance of these LNA topologies are analyzed by II. LITERATURE SURVEY
comparing various aspects such as gain, Noise Figure (NF), S In the literature survey, several LNA topologies can be
parameters, stability and linearity of each circuit. The
presented. In 1997, a 1.5V CMOS LNA operating at 1.5 GHz
simulations are done at 90nm CMOS technology by using
Cadence Virtuoso Spectre RF. Out of the three topologies is proposed by Shaeffer and Lee [5] in which NF optimization
analyzed in this paper, the cascode CS-LNA with inductive techniques and induced gate noise effects on MOS devices are
source degeneration provides high gain and low noise figure at discussed in detail. In 2001, Andreani and Sjoland [6],
1.57 GHz frequency and with 1.2 V power supply. proposed a CMOS LNA, which operates on inductive source
degeneration topology for reducing the gate induced noise. In
Keywords—Common Source (CS), Low Noise Amplifier (LNA), 2002, another LNA topology is presented by Goo et al. [7] in-
S- parameters, linearity, Noise Figure (NF), gain, stability, cascode, order to study the effect of geometry of the MOS device on
Radio Frequency (RF). noise figure and how it is tackled by using inductive source
I. INTRODUCTION degeneration. In 2005, Molavi and Hashemi [8], introduces a
wideband LNA which deales with both the power constrained
In a typical radio frequency wireless communication techniques and also the input matching techniques
system, the first block of the front-end receiver section is an simultaneously. In 2006, Azevedo et al. [9], discussed sigle
LNA. The LNA has an important role in maintaining the
ended and differential LNA topologies and introduces an
overall noise figure (NF) of the entire system in every front-
active balun circuit for LNA. In 2007, Qi and Jie [10], also
end receiver section [12]. The LNAs are mainly used for
amplification of the desired signals received by the receiving proposed a differential LNA operates at 1.5 V supply using
antenna as minimum noise and distortion as possible. So the 180 nm technology. In 2008, Fan et al. [11], again proposed a
design of the LNA should be in such a way that its noise differential LNA along with techniques for reducing the noise
figure must be as minimum as possible [1] [2] [3]. and improving the linearity of the circuit. In 2009, Chang et
al.[12] proposed a 5 GHz CMOS LNA which operates at low
The performance of LNA is more affected by process voltage and low power achieved by using current reuse
technologies than that of the circuit topologies [12]. LNAs can methods and is implemented in 180nm technology. In 2010,
be designed with one or more transistors which enable more Muhamad and Nardin [13], proposed another CMOS LNA
degree of freedom for introducing different LNA architectures
topology at 180 nm technology with power constrained noise
even for a specific purpose. The performance of the LNAs can
optimization techniques. In 2011, Yousef et al. [14], proposed
be analyzed in different ways, either by fixing the process
technology for different circuit topologies or by fixing a a ultra wide band LNA which operates at a frequency range of
circuit topology for various process technologies. In this 2- 16 GHz and is implemented using current reuse topology.
paper, process technology is fixed at 90 nm. For 90 nm CMOS Another differential CMOS LNA topology is proposed by
technology, three different common source circuit topologies ( Xuan et al.,operates at 2.5 GHz using 180 nm technology.
a CS-LNA stage with inductive loading, a feedback resistor
III. DESIGN PARAMETERS
and a CS-LNA cascode stage with inductive source
degeneration) are designed, simulated and analyzed their The parameters of LNA varies with different topologies.
performance for the comparison purpose. Different circuit will The parameters that are considered while designing an LNA
produce different performance and design trade-off [6] [10]. are as follows:

978-1-5386-2440-1/18/$31.00 ©2018 IEEE

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A. Noise Figure (NF)
Noise Figure defines the extend of degradation of SNR in a
circuit. In-order to maintain a low noise figure, proper biasing
is provided with simultaneous input matching and power
constrained techniques [2] [4]. The noise figure of the entire
receiver system is given by [5].
NFtot = NFLNA + NF2-1 (1)
GLNA
where, NFtot is the noise figure of the first LNA stage, NF2 is
the noise figure of the successive blocks after the first stage
and GLNA is the gain of LNA.
Fig.1: 1-db compression point
B. S-parameters
The scattering parameters (S- parameters) are mainly used
for impedance matching. Under matched conditions, the S-
parameters (S11, S12, S21, S22) represents the transmission and
reflection coefficients of a two port network. S11 is the
reflection coefficient at port 1 known as input reflection
coefficient which expressed in decibels gives the input return
loss and at port 2, S22 is the reflection coefficient known as
output reflection coefficient and when it is expressed in
decibels gives the output return loss [1] [4] [5].

C. Gain
S21 is the forward gain of the LNA. The ability of an LNA Fig. 2: Third order intercept point
to amplify an input signal amplitude is termed as gain of an
LNA [4].
IV. BASIC COMMON SOURCE LNA TOPOLOGIES
Gain = 20 log Vout (2)
Vin There exist various LNA topologies for different
applications. One of the most widely used LNA topologies is
D. Stability the Common Source LNA topology.
During the LNA design make sure that the circuit is stable A. CS-LNA stage using Inductive Load
in its desired frequency range. By plotting the stability factor
CS-LNA with inductive load is introduced to eliminate
(K), the stability of the LNA can be check out. For a stable
circuit, the stability factor (K) should always greater than 1. many drawbacks of CS-LNA with resistive load. The resistive
The stability factor is directly affected by coupling. The load leads to improper matching and also it cannot operate at
stability of the LNA can be improved by inductive loading and high frequencies. The resistive load also leads to a trade-off
neutralization [7]. between voltage gain and the supply voltage. This again
makes it difficult for scaling down of the device to lower
E. Linearity technologies [1]. All these drawbacks of the resistive loading
Linearity of LNA can be measured by plotting the can be overcome by using inductive loading as shown in
parameters such as third-order intercept point (IP3) and 1-dB Fig.3. The voltage drop across an inductor is ideally zero. So
compression point (P1dB) [1][4]. The third-order intercept this circuit can operate at very low supply voltages. Here the
point (IP3) as shown in Fig.1 is the point at which the third- transistor is scaled to 90nm CMOS technology.
order inter-modulation product coincides with the first order
output. The input intercept point (IIP3) is defined as the input
power level corresponds to IP3. The 1dB compression point as
shown in Fig.2 is the point at which the output signal power
drops to 1db from its expected value.

Fig. 3.Circuit diagram of CS-LNA using an inductive load

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B. CS-LNA stage using a feedback resistor II. SIMULATION RESULT
The circuit diagram of CS-LNA stage using a feedback The simulated outputs of the three topologies for various
resistor is shown in Fig.4. In this circuit, the transistor M 2 acts parameters are shown from Fig.6 to Fig.26.
as a current source and the resistor R1 acts as feedback resistor
which detects the voltage at the output node and convert it into
corresponding current and feedback to the input node [1] [5].
This topology allows a wide range of frequency band with
proper input and output matching. In this topology resistor is
used for input matching instead of inductor. So chip area can
be reduced and thus scaling can be better than the previous
topology. But the resistive feedback topology gives poor NF Fig. 6. Noise figure of CS-LNA stage using inductive load
and also power consumption is comparatively large.

Fig. 7. S11 of CS-LNA stage using inductive load

Fig. 4.Circuit diagram of CS-LNA stage using a feedback

resistor
C. CS-LNA cascode stage with inductive source degeneration
Fig. 8. S12 of CS-LNA stage using inductive load
This topology combines the benefits of both the cascode
CS-LNA and CS-LNA stage with inductive source
degeneration. It is one of the most prevalent topologies used
for various applications. Since the cascode circuits has high
output impedance, the gain is also high [5]. The Miller
capacitance of the input device can be suppressed by using the
cascode circuits, which in turn increase the reverse isolation.
This again suppresses the parasitic capacitance of the
transistor at the input which helps the amplifier to operate at
high frequencies [11].The circuit diagram of CS-LNA cascode Fig. 9. S21 of CS-LNA stage using inductive load
stage with inductive source degeneration is shown in Fig.5.

Fig. 10. S22 of CS-LNA stage using inductive load

Fig. 5.Circuit diagram of CS-LNA cascode stage with

inductive source degeneration Fig. 11. 1- dB point of CS-LNA stage with inductive load

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 Fig. 19. 1-dB point of CS-LNA stage using a feedback resistor
Fig. 12. IIP3 of CS-LNA stage using inductive load

Fig. 13. NF of CS-LNA stage using a feedback resistor

Fig. 20. NF of CS-LNA cascode stage with inductive source
degeneration

Fig. 14. S11 of CS-LNA stage using a feedback resistor

Fig. 21. S11 of CS-LNA cascode stage with inductive source

degeneration

Fig. 15. S12 of CS-LNA stage using a feedback resistor

Fig. 22. S12 of CS-LNA cascode stage with inductive source

degeneration
Fig. 16. S21 of CS-LNA stage using a feedback resistor

Fig. 23. S21 of CS-LNA cascode stage with inductive source

degeneration
Fig. 17. S22 of CS-LNA stage using a feedback resistor

Fig. 24. S22 of CS-LNA cascode stage with inductive source

Fig. 18. IIP3 of CS-LNA stage using a feedback resistor degeneration

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 we can conclude that the CS-LNA cascode stage with
inductive source degeneration is best suited for GPS
applications.

REFERENCES

[1] B. Razavi,”RF Microelectronics”, second edition ed.

Fig. 25. 1-dB point of CS-LNA cascode stage with inductive Prentice Hall,2011.
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[3] B. M. Ninan and Balamurugan K., “Design of CMOS
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[5] Derek K Shaeffer and Thomas H Lee, “ A 1.5 V, 1.5GHz
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V. ACKNOWLEDGEMENT “A 2.4 GHz Monolithic Single-ended Input/ Differential
Output Low Noise Amplifier,” SiRF 2006, Jan. 2006.
The authors would like to acknowledge the valuable sup-
[10] Hong Qi and Zhang Jie, “ A1.5V Low Power CMOS
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India for providing facilities for doing this project. We would Antenna Propogation and EMC Technologies for
like to express our sincere gratitude to everyone who Wireless Communications, pp.1379-1382, Aug. 2007.
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completion of this project. “ A Noise Reduction and Linearity Improvement
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State Circuits, vol 43, pp.588-599, March 2008.
VI. CONCLUSION [12] Chieh-Pin Chang, Ja-Hao Chen and Yeong-Her Wang, “
The simulation results of three LNA topologies designed A fully integrated 5GHz low voltage and low power low
for GPS frequency 1.57GHz are analyzed in this paper. noise amplifier(LNA) using forward body bias
Cadence design suite is used to design these LNAs at CMOS technology,” IEEE Microwave and Wireless Components
Letters, vol.19, no.3, pp. 176-178, March 2009.
90nm technology. At a frequency of 1.57 GHz , 1.2V power [13] M. Muhamad and N. A. Nordin, “ An Area Efficient of
supply, the cascode stage along with inductive source 0.18um LNA Using Power Constraint Method,” IEEE
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Simulation (AMS). Pp. 606-609, May 2010.
18.9dB, 1-dB compression point of -2.651 dBm and IIP3 of -
[14] K. Yousef, H Jia, R. Pokharel, A. Allaml, M. Ragab and
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topologies in all aspects like S-parameter, noise and gain. So

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