UNIVERSITI TEKNOLOGI MARA ELECTRICAL

ENGINEERING STUDIES

DIGITAL DESIGN AND COMPUTER ARCHITECTURE

(ETL614)

LAB 2

SYSTEM VERILOG HDL USING ALTERA DE2-115 FPGA

BOARD

1
 TABLE OF CONTENT

No Contents Page

1 Table of Content 1

2 Objectives 2

3 Part 1: Clock Divider 3

4 Part 2: 7 Segment Decoder 5

5 Part 3: Top Module 7

6 Appendix 8

1
A.OBJECTIVES:

i. To compile, program and test the clock divider module in part 1 on FPGA board.

ii. To compile, program and test the decoder to 7 segment modules in part 2 on
FPGAboard.

iii. To integrate the modules above as top module in part 3 and implement on FPGA
board.

2
B.EXPERIMENTS:

Part 1: Clock Divider

module clkdiv(
input logic clk_in,
input logic reset,
output logic clk
);

logic [23:0] count;

always_ff @(posedge clk_in, posedge reset)

if(reset) begin
count <= 25'd24999999;
clk <= 1'b0;
end
else begin
count <= count + 25'h1ffffff;
if(!count) begin
count <= 25'd24999999;
clk <= ~clk;
end
end

endmodule

Figure 1

1) Based on the SystemVerilog code in Figure 1, draw the block diagram for the clock divider module.

2) Create a Quartus project file as clkdiv.qpf in part 1 folder. Compile the clkdiv.sv file.
Capturethe RTL schematic

3) Assign the pin connections for the input clock, reset and LED as below. Refer the attachment
for pin location on the DE2 115 FPGA board. Recompile the design.

Table 1

INPUT/OUTPUT PORTS NAME PIN LOCATIONS

CLK50 CLOCK,clk_in

SW0 RESET,reset

LEDR0/LEDG0 OUTPUT,clk

3
4) Program the design on the FPGA board.

5) Observe the output at LED. Capture the results on the board and discuss the results. Show
that the reset button can force the LED to be OFF.

6) Change the counter value count to 25'd50000000. Capture the results on the board and
discuss the results. Compare with the previous results.

4
PART 2: 7 Segment Decoder.

1) Create a Quartus project file decoder7seg.qpf in part 2 folder.

module decoder7seg (input logic clk,reset,

input logic I1, I2, I3,
output logic [6:0] HEX0);

always_ff @(posedge clk, posedge reset)

if (reset)
begin HEX0 <= 7'b1000000;endelse

if (!reset)

begin
if (!I1&&(I2)&&(I3))
begin HEX0 <= 7'b1111001;end //DISPLAY 1
else if ( ) //ADD THE CORRECT CONDITION HERE
begin HEX0 <= 7'b ;end //ADD THE CORRECT OUTPUT PATTERN FOR HEX0.DISPLAY 2
else if ( ) //ADD THE CORRECT CONDITION HERE
begin HEX0 <= 7'b ;end //ADD THE CORRECT OUTPUT PATTERN FOR HEX0.DISPLAY 3

end
endmodule

Figure 2

1. The module in Figure 3 will convert the inputs from push button KEY1, KEY2 and KEY3 into its
numerical representation on the HEX0 7 segment display. Press and Hold the respective KEY
button and toggle SW0 up and down to generate clock. Show that the output HEX0 reset to
zero when SW1 (reset) HIGH. Test for several inputs and capture the results. Discuss the
results

2. Determine the type of module and SystemVerilog format of the code above.

3. Complete the decoder7seg.sv file in figure 2 and compile the design. Determine whether the
7-segment display is common anode or common cathode. Capture the RTL schematic

4. Create a project for the module in ModelSim. Write a testbench for the module. Simulate

the module and observed the output waveform. Discuss the results.

5. Assign the pin connections for the inputs and output HEX0 7-segment display as below. Refer
the attachment for pin locations on the DE2 115 FPGA board.

5
 Table 2

INPUT/OUTPUT PORTS NAME PIN LOCATIONS

KEY 1 I1
KEY 2 I2
KEY3 I3
SW0 clk
SW1 reset
HEX0[6] HEX0
HEX0[5]
HEX0[4]
HEX0[3]
HEX0[2]
HEX0[1]
HEX0[0]

6. Program the design on the FPGA board.

7. Test the inputs for several patterns. Capture the results on the board. Discuss the results of
the design and compare with the ModelSim simulation.

Figure 3

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 PART 3: Top Module

1. Combine the clock divider and 7-segment decoder modules as below. Create a new module,
top in Quartus. Compile the design and capture the RTL schematic.

2. Create a project for the top module in ModelSim. Write a testbench for the top module.

Simulate the top module and observed the output waveform. Discuss the results.

3. Assign the pin connections and program the design on FPGA. Test the inputs for several
patterns. Capture the results on the boards and discuss the results of the new module top.
Compare the results with the ModelSim simulation.

decoder7seg
I1

I2
I3

clkdiv HEX0 [6:0]

clk
clk_in

reset

TOP

Figure 4

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Appendix:

8
 PIN ASSIGNMENTS:
.-0

"'""
l£ O A 2
,..,,.,

lfOR14
lfOR\5

"'
lEOA.18

"""" •••
G22

Figure 4 9 Connections bGtween the LEDs and Cyclone IV E FPGA

Table 4-3 Pin Assig'n-_m_e_n_ts_i_o_r_L_E_D

_s , SW17 SW16 SW15 SW14 SW3 SW2 SW1 SWO

Signal Name FPGAPin No. Description VO Standard Figure 4-8 Connections between the slide switches and Cyclone IV E FPGA
LEDR(OJ PIN _G19 LED Red(OJ 2.5V
LEDR(1] PIN_F19 LED Red[1] 2.5V T•b l• 4-1 Pin Assignmrnts (orSUdtS"'ilth s

LEDR 2] --g-E19 LED Red(ll 2.5V -=i Slgn•J H.,,,. FPG AP

Ni.n O.scrlptlon VOSf•ndard

SW(OJ PIN_ AB28 SlldeSWi tch(O) Depending on JP7

LEDR(3] PIN_F21 I LED Red(3] 2.5V SW(1) PIN_AC2S Slide SWftch(1) Depending on JP7
LEDR(4] PIN_F18 LED Red(4] 2.5V SW(2] PIN_AC27 Slide SWl tch(2) Depending on JP7
LEDR(5] PIN_E18 LED Red[S] 2.5V SW(3) PIN_A027 Slide Swftch[3J O.pendlng on JP7
LEDR 6] LED Red(6) 2. 5V SW(4) PIN_A8 27 SlideSWftch(4J Depending on JP?
1 SW(5] PIN_AC26 Slide SWitch{5J Depending on JP7
LED Red(7J 2.5V
SW(6] PIN_AD26 Slide Switch{6) Depending on JP7
LEDR(8] LED Red[8] 2.SV SW(7J PIN_A826 Sild o Swkch(7J Depending on JP7
LEDR(9) PIN_G17 LED Red(9] 2.5V SW(SJ PIN_AC25 Slide SWttch {8) Depending on JP7
LEDR 10) PIN J15 LED Red(10) 2.5V SW( 9] PIN_AB2S Slide SWitch(9 ) 0.pendlng on JP7

1
=i
1 SW(10] PIN_AC24 Slldo Swftch(10] Depending on JP7
LEDR(11] PIN H16 LED Red(11) 2. sv PIN_A8"24 SlideSWitch(11J Oopendlng on JP7
SW(11J

LEDR(12) PIN_J16 LED Red(12] 2.SV SWl12) PIN_AB23 $fideSWl tch(12] Depending on JP7
LEDR(13) PIN_H17 LED Red(13) 2. 5V SW(13) PIN_AA.24 Slid e SWitch(13) Oopendlng on JP7
SW(14) PIN. AA2) Slide Switch(14] Depending on JP7
LEDR(14) PIN_F15 LEDRed() 4) 2.5V SW(15] PIN_AA22 SlideSwitch(15] Oependlng on JP7
LEDR(15) PIN _G15 LEDRed[15] 2. 5V SW(16) PIN_Y2.4 $UdeSwitch(16) Depending on JP7
LEDR(16) PIN_ G16 LEDRed(16) -ii . SW(17] PIN_Y23 Slide SWftch(17 ] Depending on JP7

LEDR(17] PIN_H15 LEDRed[17] J_:SV

, LEDG(OJ PIN_E21 LEDGreen[OJ 2.5V
LEDG[1) PIN_E22 LEDGreen[1) 2.SV
LEDG[_!J PIN_E25 LEDGree-n(2) 2.5V

L G(_!J PIN_ LEDGreen[3) 2.SV

LEDG[4) PIN_H21 LEDGreen[4) 2.SV

LEDG[SJ Pl _G20 LEDGreen[S) 2.SV
LEDG[6) PIN_G22 LEDGreen[6) 2.SV
EDG(7J PIN _G21 LEDGreen(7J 2.5V
LEDG(8) PIN_F17 LEDGreen(8) 2.5V