ICE3203 Lecture22
ICE3203 Lecture22
Chapter 2
8051 Architecture
• Overview of 8051
• RAM/ROM Configuration
• I/O Port
Overview of the 8051
• Made by Intel in 1981
• An 8-bit, single-chip microcontroller optimized for control applications
• 128 bytes RAM, 4096 bytes (4KB) ROM, 2 timers, 1 serial port, 4 I/O ports
• 40 pins in a dual in-line package (DIP) layout
General Physical Features
• 4KB ROM
• 128 bytes internal RAM
• 4 register banks of 8 bytes each (R0-R7)
• 16 bytes of bit-addressable area
• 80 bytes of general purpose memory
• Four 8-bit I/O ports (P0-P3)
• Two 16-bit timers (Timer0 & Timer1)
• One serial receiver-transmitter interface
• Five interrupt sources (2 external & 3 internal)
• One oscillator (generates clock signal)
General Operational Features
• Memory of 8051 can be increased externally:
• Increase memory space for codes (programs) by 64K
• Increase memory space for data by 64K
• Boolean instructions work with 1 bit at a time
• Assume clock frequency = 12MHz, it takes about 4 µs (i.e. 4 x 10-6s) to carry out a 8-bit
multiplication instruction
Hardware Description
1. Oscillator circuit
2. Program counter (PC)
3. Data pointer (DPTR)
4. Accumulator (“A”) register
5. B register
6. Flags
7. Program status word (PSW)
8. Internal memory (ROM, RAM, additional memory)
9. Stack & stack pointer (SP)
10. Special function register (SFR)
-1-
Chapter 2 – 8051 Architecture
-2-
Chapter 2 – 8051 Architecture
Oscillator Circuit
• The heart of the 8051
• Produces clock pulses
• Synchronize all 8051’s internal operations
Machine Cycle
Machine cycle is the basic repetitive process that the CPU performs once it is powered on. A
machine cycle consists of a fixed number of clock cycles (pulses). It is different for different
kinds of CPU.
The 8051 family needs 12 clock cycles for a machine cycle.
The CPU takes one or more machine cycles to complete an instruction. More complex
instructions require more number of machine cycles to complete the instruction. The number
of machine cycles of the 8051 instructions are ranging from 1 to 4.
Program Counter (PC)
• PC is a 16-bit register
• PC is the only register that does not have an internal address
• Holds the address of the memory location to fetch the program instruction
• Program ROM may be on the chip at addresses 0000H to 0FFFH (4Kbytes), external to the
chip for addresses that exceed 0FFFH
• Program ROM may be totally external for all addresses from 0000H to FFFFH
• PC is automatically incremented (+1) after every instruction byte is fetched
Data Pointer (DPTR)
• DPTR is a 16-bit register
• DPTR is made up of two 8-bit registers: DPH and DPL
• DPTR holds the memory addresses for internal and external code access and external data
access
• DPTR is under the control of program instructions and can be specified by its 16-bit name,
or by each individual byte name, DPH and DPL
• DPTR does not have a single internal address; DPH and DPL are each assigned an address
(83H and 82H)
Accumulator (A Register)
• Most versatile CPU register and is used for many operations, including addition, integer
multiplication and division, and Boolean bit manipulations
• A register is also used for all data transfer between the 8051 and any external memory
B Register
• B register is used with the A register for multiplication and division operations
• No other special function other than as a location where data may be stored
Flags
• Flags are 1-bit registers provided to store the results of certain program instructions
• Other instructions can test the condition of the flags and make decisions based on the flag
states
• Flags are grouped inside the program status word (PSW) and the power control (PCON)
-3-
Chapter 2 – 8051 Architecture
Internal Memory
• A functioning computer must have memory for program code bytes, commonly in ROM,
and RAM memory for variable data that can be altered as the program runs
• 8051 has internal RAM (128 bytes) and ROM (4Kbytes)
• 8051 uses the same address but in different memories for code and data
• Internal circuitry access the correct memory based on the nature of the operation in progress
• Can add memory externally if needed
-4-
Chapter 2 – 8051 Architecture
-5-
Chapter 2 – 8051 Architecture
Internal ROM
• Internal ROM occupies the code address space from 0000H to 0FFFH
• Program addresses higher than 0FFFH will automatically fetch code bytes from external
program memory
• Code bytes can also be fetched exclusively from an external memory by connecting the
external access pin (EA) to ground
Some Important Pins
• VCC (pin 40 - provides supply voltage of +5V)
• GND (pin 20)
• XTAL1 & XTAL2 (pins 19 & 18 - to crystal and then caps)
• RST (pin 9- reset)
• EA (pin 31 - external access)
• PSEN (pin 29 - program store enable)
• ALE (pin 30 - address latch enable)
• Ports 0-3
I/O Ports (P0 - P3)
One of the most useful features of the 8051 is that it consists of 4 I/O ports (P0 - P3)
• All ports are bidirectional (they can take input and to provide output)
• All ports have multiple functions (except P1)
• All ports are bit addressable
• On RESET all the ports are configured as output
• When a bit latch is to be used as an input, a “1” must be written to the corresponding
latch by the program to configure it as input
Port 0
• Occupies a total of 8 pins (Pins 32-39)
• Can be used for :
• Input only
• Output only
-6-
Chapter 2 – 8051 Architecture
• Input and output at the same time (i.e. some pins for input and the others for output)
• Can be used to handle both address and data
• Need pull-up resistors
Port 0 as an Output Port
The following code will continuously send out to port 0 the alternating values 55H and AAH
-7-
Chapter 2 – 8051 Architecture
Read-Modify-Write Feature
• A method used to access the 8051 ports
• Combining all 3 actions in a single instructions :
• Read the data at the port
• Modify (do operation on) the data at the port
• Write the results to the port
•
Single-bit Addressability of Ports
• One of the most powerful features of the 8051
• Access only one or several bits of the port instead of the entire 8 bits
-8-