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ICE3203 Lecture22

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0% found this document useful (0 votes)
20 views8 pages

ICE3203 Lecture22

Uploaded by

Par Veen
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 2 – 8051 Architecture

Chapter 2
8051 Architecture
• Overview of 8051
• RAM/ROM Configuration
• I/O Port
Overview of the 8051
• Made by Intel in 1981
• An 8-bit, single-chip microcontroller optimized for control applications
• 128 bytes RAM, 4096 bytes (4KB) ROM, 2 timers, 1 serial port, 4 I/O ports
• 40 pins in a dual in-line package (DIP) layout
General Physical Features
• 4KB ROM
• 128 bytes internal RAM
• 4 register banks of 8 bytes each (R0-R7)
• 16 bytes of bit-addressable area
• 80 bytes of general purpose memory
• Four 8-bit I/O ports (P0-P3)
• Two 16-bit timers (Timer0 & Timer1)
• One serial receiver-transmitter interface
• Five interrupt sources (2 external & 3 internal)
• One oscillator (generates clock signal)
General Operational Features
• Memory of 8051 can be increased externally:
• Increase memory space for codes (programs) by 64K
• Increase memory space for data by 64K
• Boolean instructions work with 1 bit at a time
• Assume clock frequency = 12MHz, it takes about 4 µs (i.e. 4 x 10-6s) to carry out a 8-bit
multiplication instruction
Hardware Description
1. Oscillator circuit
2. Program counter (PC)
3. Data pointer (DPTR)
4. Accumulator (“A”) register
5. B register
6. Flags
7. Program status word (PSW)
8. Internal memory (ROM, RAM, additional memory)
9. Stack & stack pointer (SP)
10. Special function register (SFR)
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Chapter 2 – 8051 Architecture

The 8051 Block Diagram

The 8051 Pin Assignments

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Chapter 2 – 8051 Architecture

Oscillator Circuit
• The heart of the 8051
• Produces clock pulses
• Synchronize all 8051’s internal operations
Machine Cycle
 Machine cycle is the basic repetitive process that the CPU performs once it is powered on. A
machine cycle consists of a fixed number of clock cycles (pulses). It is different for different
kinds of CPU.
 The 8051 family needs 12 clock cycles for a machine cycle.
 The CPU takes one or more machine cycles to complete an instruction. More complex
instructions require more number of machine cycles to complete the instruction. The number
of machine cycles of the 8051 instructions are ranging from 1 to 4.
Program Counter (PC)
• PC is a 16-bit register
• PC is the only register that does not have an internal address
• Holds the address of the memory location to fetch the program instruction
• Program ROM may be on the chip at addresses 0000H to 0FFFH (4Kbytes), external to the
chip for addresses that exceed 0FFFH
• Program ROM may be totally external for all addresses from 0000H to FFFFH
• PC is automatically incremented (+1) after every instruction byte is fetched
Data Pointer (DPTR)
• DPTR is a 16-bit register
• DPTR is made up of two 8-bit registers: DPH and DPL
• DPTR holds the memory addresses for internal and external code access and external data
access
• DPTR is under the control of program instructions and can be specified by its 16-bit name,
or by each individual byte name, DPH and DPL
• DPTR does not have a single internal address; DPH and DPL are each assigned an address
(83H and 82H)
Accumulator (A Register)
• Most versatile CPU register and is used for many operations, including addition, integer
multiplication and division, and Boolean bit manipulations
• A register is also used for all data transfer between the 8051 and any external memory
B Register
• B register is used with the A register for multiplication and division operations
• No other special function other than as a location where data may be stored
Flags
• Flags are 1-bit registers provided to store the results of certain program instructions
• Other instructions can test the condition of the flags and make decisions based on the flag
states
• Flags are grouped inside the program status word (PSW) and the power control (PCON)

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Chapter 2 – 8051 Architecture

registers for convenient addressing


• Math flags: respond automatically to the outcomes of math operations (CY, AC, OV, P)
• User flags: general-purpose flags that may be used by the programmer to record some event
in the program (F0, GF0, GF1)
Program Status Word (PSW)
PSW contains the math flags, user program flag F0, and the register select bits that identify which
of the four general-purpose register banks is currently in use by the program

Program Status Word (PSW)

Internal Memory
• A functioning computer must have memory for program code bytes, commonly in ROM,
and RAM memory for variable data that can be altered as the program runs
• 8051 has internal RAM (128 bytes) and ROM (4Kbytes)
• 8051 uses the same address but in different memories for code and data
• Internal circuitry access the correct memory based on the nature of the operation in progress
• Can add memory externally if needed

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Chapter 2 – 8051 Architecture

Stack and Stack Pointer (SP)


• SP is a 8-bit register used to hold an internal RAM address that is called the “top of the
stack”Stack refers to an area of internal RAM that is used in conjunction with certain
opcodes to store and retrieve data quickly
• SP holds the internal RAM address where the last byte of data was stored by a stack
operation
• When data is to be placed on the stack, the SP increments before storing data on the stack so
that the stack grows up as data is stored
• As data is retrieved from the stack, the byte is read from the stack, and then the SP
decrements to point to the next available byte of stored data
Special Function Registers (SFR)
• 8051 has 21 SFRs which occupy the addresses from 80H to FFH (128bytes)
• Not all of the addresses from 80H to FFH are used for SFRs
• Attempt to use the “empty” addresses may get unpredictable result
Special Function Register Map

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Chapter 2 – 8051 Architecture

Internal ROM
• Internal ROM occupies the code address space from 0000H to 0FFFH
• Program addresses higher than 0FFFH will automatically fetch code bytes from external
program memory
• Code bytes can also be fetched exclusively from an external memory by connecting the
external access pin (EA) to ground
Some Important Pins
• VCC (pin 40 - provides supply voltage of +5V)
• GND (pin 20)
• XTAL1 & XTAL2 (pins 19 & 18 - to crystal and then caps)
• RST (pin 9- reset)
• EA (pin 31 - external access)
• PSEN (pin 29 - program store enable)
• ALE (pin 30 - address latch enable)
• Ports 0-3
I/O Ports (P0 - P3)
One of the most useful features of the 8051 is that it consists of 4 I/O ports (P0 - P3)
• All ports are bidirectional (they can take input and to provide output)
• All ports have multiple functions (except P1)
• All ports are bit addressable
• On RESET all the ports are configured as output
• When a bit latch is to be used as an input, a “1” must be written to the corresponding
latch by the program to configure it as input
Port 0
• Occupies a total of 8 pins (Pins 32-39)
• Can be used for :
• Input only
• Output only

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Chapter 2 – 8051 Architecture

• Input and output at the same time (i.e. some pins for input and the others for output)
• Can be used to handle both address and data
• Need pull-up resistors
Port 0 as an Output Port
The following code will continuously send out to port 0 the alternating values 55H and AAH

Port 0 as an Input Port


In the following code, port 0 is configured first as an input port by writing 1s to it, and then data is
received from that port and sent to P1

Dual Role of Port 0


• When connecting an 8051 to an external memory, port 0 provides both address and data
(AD0 – AD7)
• When ALE = 0, it provides data D0 – D7
• When ALE = 1, it provides data A0 – A7
• ALE is used for demultiplexing address and data with the help of a 74LS373 latch
Port 1
• Occupies a total of 8 pins (Pins 1-8)
• Can be used as input or output
• Does not need any pull-up resistors
• Upon reset, port 1 is configured as an output port
• No alternative functions
Port 2
• Occupies a total of 8 pins (Pins 21-28)
• Similar function as Port 1
• Can be used as input or output
• Does not need any pull-up resistors
• Upon reset, port 1 is configured as an output port
Dual Role of Port 2
• When connecting an 8051 to an external memory, port 2 provides both address (A8 – A15)
• It is used along with P0 to provide the 16-bit address
• When P2 is used for the upper 8 bits of the 16-bit address, it cannot be used for I/O
Port 3

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Chapter 2 – 8051 Architecture

• Occupies a total of 8 pins (Pins 10-17)


• Similar function as Port 1 and Port 2
• Can be used as input or output
• Does not need any pull-up resistors
• Upon reset, port 1 is configured as an output port
• Pins can be individually programmable for other uses
• Most commonly be used to provide some important signals (e.g. interrupts)
Port 3 Alternate Functions

Read-Modify-Write Feature
• A method used to access the 8051 ports
• Combining all 3 actions in a single instructions :
• Read the data at the port
• Modify (do operation on) the data at the port
• Write the results to the port


Single-bit Addressability of Ports
• One of the most powerful features of the 8051
• Access only one or several bits of the port instead of the entire 8 bits

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