15EI53
15EI53
Module -1
Draw the block diagram of a general process control system. Taking
1a 6
an example explain the functions of each block.
Discuss the following requirements to achieve objectives of a process
1b
control system.
i) Stability 6
ii) Steady state regulation
iii )Transient regulation
With a neat sketch and necessary equations, explain the following
1c
control system evaluation criteria
4
i) Minimum area criteria
ii) Quarter amplitude criteria
OR
Draw the block diagram and explain the function of elements used in
2a
final control operation. 6
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The temperature of water in a tank is controlled by a two-position
3b
controller. When the heater is off the temperature drops at 2 K per
minute. When the heater is on the temperature rises at 4 K per minute.
6
The setpoint is 323 K and the neutral zone is ±4% of the setpoint.
There is a 0.5-min lag at both the on and off switch points. Find the
period of oscillation and plot the water temperature versus time.
OR
Consider the proportional-mode level-control system of Figure 4.a.
4a
Value A is linear, with a flow scale factor of 10 m3/h per percent
controller output. The controller output is nominally 50% with a
constant of Kp = 10% per %. A load change occurs when flow through
valve B changes from 500 m3/h to 600 m3/h . Calculate the new
controller output and offset error.
Fig. 4a
With a neat graph of error and controller output, discuss working of
4b 8
integral control mode.
Summarize the characteristics of the derivative mode.
4c 2
Module -3
OR
Draw a neat block diagram of a computer supervisory control, explain
6a
its operation considering an example of strongly interacting process.
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Module -4
OR
In a compound control system, the ratio between two variables is to be
8a
maintained at 3.5 to 1. If each has been converted to a 0–5-V range
8
signal, devise a signal conditioning system that will output a zero signal
to the controller when the ratio is correct.
Illustrate and explain with a block diagram and wave forms, how
8b
process control loop can cause instability for some frequency, if Gain 8
margin and phase margin is not properly designed.
Module -5
OR
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