Logic Circuits

Number Systems:
Binary Number System:
• Uses two digits (0 and 1) for counting items. Hence, Base = 2
• Each binary digit (0 and 1) is referred to as a ‘bit’.
• Nibble: string of four bits
• Byte: string of eight bits
Decimal Number System:
• Uses 10 number of digits: 0 to 9. Hence, Base = 10
• Any number is represented using these digits
Octal Number system:
• Any number is represented using the digits 0 to 7. Hence, Base = 8
Hexadecimal Number system:
Any number is represented using the digits 0 to 9 and then using letters A, B, C, D, E, F. The letters A to F are
used to represent the numbers 10, 11, 12, 13, 14, 15 respectively. Hence, Base = 16
Decimal to Binary Conversion:

• Divide progressively the decimal number by 2

• Write down the remainder for each division
• Continue the process until the quotient becomes 0 and remainder 1
• Take remainder in reverse order to have the equivalent binary number
Steps to convert the decimal number (13)10 as follows:

Binary to Decimal Conversion:

• Determine the local value of each bit by multiplying each bit by its weightage (Base)n, where ‘n’ is the
decimal value of its position, Base =2 for Binary system
• Add the local values of bits to calculate decimal value
Decimal to Octal Conversion:

• Divide progressively the decimal number by Example:

8
• Write down the remainder for each division
• Continue the process until the quotient
becomes 0
• Take remainder in reverse order to have the
equivalent binary number
Octal to Decimal Conversion:

• Determine the local value of each digit by Example:

multiplying each digit by its weightage
(Base)n, where ‘n’ is the decimal value of its
position, Base =8 for octal system
• Add the local values of digits to calculate
decimal number

Octal to Binary Conversion:

• Each octal digit is represented by 3-bit binary Example:

number

Just do the opposite for conversion from Binary to Octal

Hexadecimal to Decimal Conversion and vice versa:
Follows the same procedure as described for Octal to Decimal and vice versa except the base = 16

Hex to Binary Conversion: Example:

• Each Hex digit is represented by 4-bit binary
number

Just do the opposite for conversion from Binary to Hex

BCD (Binary Coded decimal):

• Each decimal number is represented by a 4-
bit binary number
• For Example, Conversion of a decimal
number (489)10 to BCD as follows:
Binary to Gray Code and vice-versa:
Binary to Gray code conversion Gray to Binary code conversion

Example: Binary (B3B2B1B0)=1011 Example: Binary (G3G2G1G0)=1011

Gray code (G3G2G1G0)=1110 Gray code (B3B2B1B0)=1101

Homework: Convert (ACD.EF)16 to octal and decimal

Boolean Algebra:
Algebra that deals with logic operations/logic functions of Boolean variables that takes only two bits (0 and 1)
and also results only 0 or 1.
Single variable theorem:

Plus(+) : OR operation
Dot(.): AND operation
Bar (𝐴̅) : NOT operation

Multi-variable theorem
Duality Principle: Boolean expression remains same if the AND and OR operations are interchanged, and also 0
and 1 are interchanged

Then Duality principle states the following is also true

De Morgan’s Theorem:
Theorem-1: Theorem-2:

Prove De’Morgan Theorem:

Theorem-1 Proof: Let’s say, F1=A’B’ and F2=(A+B)’
Now, F1.F2’=A’B’(A+B)=A’B’A+A’B’B=0
Hence, F1=F2

Similarly, Theorem-2 can be proved considering F1=A’+B’ and F2=A.B

Here, F1.F2’=0 indicating F1=F2

Q. Find the Boolean expression for the output of the following logic circuit using De Morgan’s theorem
The output Boolean expression

Using De Morgan’s theorem

Logic Gates:
Basic logic gates: AND, OR, NOT gate
Universal logic gates: NAND, NOR gate

Symbol Boolean Truth Table

expression
OR gate Y=A+B

AND gate Y=A.B

 NOT gate Y=𝐴̅

Exclusive OR or XOR gate:

Similar inputs results ‘0’ output

Symbol Boolean Expression Truth Table

Y=

Y = 𝐴̅𝐵 + 𝐴𝐵̅

XNOR gate/Equivalence gate:

Similar inputs results ‘1’ output

Symbol Boolean Expression Truth Table

Y=

Y = 𝐴𝐵 + 𝐴̅𝐵̅

Universal gates:
Any Boolean function can be implemented using only NAND gates or NOR gates. Hence, these gates are called
Universal gate.
NAND/NOR gate as Universal gate:
Similarly, NOR gate can be used to implement any logic gates. Here, below, examples of implementing XOR gate
using NAND and NOR gate have been shown.

XOR gate using NAND XOR gate using NOR

Boolean expression (SOP and POS)

SOP (Sum of Products) and POS (Product of Sum) are two standard forms to represent a Boolean expression.
SOP and POS expressions are denoted by ∑ and ∏ respectively. Each product containing all input variables
(true/complemented form) of a SOP expression is called ‘Minterm’; whereas, each sum containing all input
variables (true/complemented form), of a standard POS expression is called ‘Maxterm’.

Example of a standard SOP form: Y=A+BC Example of a standard POS form: Y=A(B+C)
What are the minterms? What are the Maxterms?
Y=A+BC Y=A(B+C)
=A(B+B’)(C+C’)+(A+A’)BC =(A+BB’)(AA’+B+C)
=(ABC+ABC’+AB’C+AB’C’)+(ABC+A’BC) = (A+B)(A+B’)(A+B+C)(A’+B+C)
=A’BC+AB’C’+AB’C+ABC’+ABC =(A+B+CC’)(A+B’+CC’)(A+B+C)(A’+B+C)
(Canonical form) =(A+B+C)(A+B+C’)(A+B’+C)(A+B’+C’)(A+B+C)(A’+B+C)
Here, minterms are as follows: A’BC, AB’C’, =(A+B+C)(A+B+C’)(A+B’+C)(A+B’+C’)(A’+B+C)
AB’C, ABC’, ABC. Hence, if any minterm of Y (Canonical form)
equal to 1, then Y=1. Here, Maxterms are as follows: (A+B+C), (A+B+C’),
Now, to find decimal equivalent number of (A+B’+C), (A+B’+C’), (A’+B+C)
each minterm take ‘1’ for true form of a Hence, if any Maxterm of Y equal to 0, then Y=0.
variable and ‘0’ for complement form of a Now, to find decimal equivalent number of each Maxterm take
variable. Therefore, ‘0’ for true form of a variable and ‘1’ for complement form of a
Y =∑𝑚(3, 4, 5, 6, 7) variable. Therefore,
Y = ∏𝑀(0, 1, 2, 3, 4)

Simplification of Boolean expression

K-Map (Karnaugh Map): Used to find the simplified Boolean expression with minimum input variables.

Steps:
[1] Draw a K-map according to the number of input variables.
 [2] Note what are the maxterms or minterms (can be identified from the given problem.)
[3] If it is SOP expression, put the 1’s in the respective cells of the K-map with respect to the minterms. Put 0’s
elsewhere.
[4] If it is POS expression, place 0’s in the respective cells of the K-map with respect to the maxterms. Put 1’s
elsewhere which is just opposite to that of SOP expression.
[5] Make groups of cells containing 1s or 0s (depending on whether minterms/maxterms are given) in the power
of two, such as 2,4,8 ..(except 1). Grouping should be made with an many neighbouring cells as possible.
[6] From the groups that have been created in step 5, find the product terms and then sum them up for the SOP
form

POS Form:
 MULTIPLEXER
 A Multiplexer is a combinational digital circuit.
 It has 2n numbers of input lines, where n is the
number of select lines/address lines.
 MUX has only one output line.
 MUX o/p line is connected to one of the input lines
depending on the value on address lines/select lines.
Using select line we can set which input line to be
directly shorted to the output line.
 In above figure there are two select lines
(S1S0)…..so there are 22=4 numbers of input lines
I0, I1, I2, I3.….and only one o/p line Y.
 When select line S1S0=00 then Y=I0 (data on 0th
input line I0 is transmitted to o/p)

Fig. Block Diagram, Truth Table and K-Map for o/p Y

of 4X1 Multiplexer
When select line S1S0=01 then Y=I1 (data on I1 is transmitted to o/p)
Similarly, I2 and I3 are connected to o/p for S1S0=10 and 11 respectively.
Logic Expression for Y: Y=I2 when S1S0=10…………….> Y=S1S0’.I2
Y=I0 when S1S0=00…………….> Y=S1’S0’.I0 Y=Y3 when S1S0=11…………….> Y=S1S0.I3
Y=I1 when S1S0=01…………….> Y=S1’S0.I1
Therefore, Y=S1’S0’.I0 + S1’S0.I1 + S1S0’.I2 +
S1S0.I3

Q. What is the logic expression for F in the following ANSWER: F=B’C’.I0 + B’C. I1 + BC’. I2 + BC. I3
diagram =B’C’.0 + B’C. 1 + BC’. A’ + BC.A
=B’C + A’BC’ + ABC
=C. (B’ + AB) + A’BC’
= C. (B’ + A) + A’BC’
=B’C + AC +A’BC’
Internal circuit of MUX:

Fig. Internal circuit of 4X1 MUX

Implementation of 8x1 MUX using 2x1 MUXes:

Address lines/Select lines Output (Y)

S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Implementation of 8x1 MUX using 4x1 MUXes:

Address lines/Select lines Output (Y)

SEL2 SEL1 SEL0 Y
0 0 0 IN0
0 0 1 IN1
0 1 0 IN2
0 1 1 IN3
1 0 0 IN4
1 0 1 IN5
1 1 0 IN6
1 1 1 IN7
 DEMULTIPLEXER
 A DeMultiplexer is a combinational digital circuit.
It’s working is just opposite of a MUX.
 It has 2n numbers of output lines, where n is the
number of select lines/address lines.
 DeMUX has only one input line.
 DeMUX i/p line is connected to one of the output
lines depending on the value on address lines/select
lines. Using select line we can set which output line
to be directly shorted to the input line.
Logic Expression for o/p lines:
D0 = B’A’.X D1 = B’A. X D2 = BA’. X
D3 = BA. X

Fig. 1 X 4 DeMUX internal digital circuit, symbol,

Truth Table
ENCODER

 An Encoder is a combinational digital circuit.

 It has maximum of 2n numbers of input lines and ‘n’ numbers of output lines.

 Only one line of 2^n inputs will be ‘1’ at a time, while

other inputs will be at ‘0’ and that active high input will
be encoded into an n-bit code at the output. It will
produce a binary code equivalent of the active input.

 D0-D7 are the eight input lines and Q0-Q2 are the three
output lines of 8-to-3 Encoder (Q2 is the MSB of outputs)
 Truth table of a 8-to-3 Encoder is given as follows:


 When all inputs are ‘0’s, the outputs are in ‘don’t care’
states, which is presented by ‘X’ symbol…..For other
cases only one input line will be at logic ‘1’ at a time and Fig. Block Diagram of 8 : 3 Encoder
will be encoded in equivalent binary number at output. A Truth Table representing 8:3 Encoder.
For example, when D3 = 1, then the output will be binary
equivalent of octal number ‘3’ which ‘011’. Hence, INPUT OUTPUT
output is Q2Q1Q0 = 011
 Use K-map to find out the digital expression for outputs D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
Q2, Q1, Q0
 Using OR gates, the digital expression for outputs Q2, Q1, 0 0 0 0 0 0 0 0 X X X
Q0 as follows:
Q2=D4 + D5 + D6 + D7
0 0 0 0 0 0 0 1 0 0 0
Q1=D2 + D3 + D6 + D7
Q0=D1 + D3 + D5 + D7
0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0
 0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

DECODER

⚫ A decoder performs the reverse operation of an encoder.

⚫ It has maximum 2n numbers of output lines and ‘n’ numbers of input lines.

⚫ It decodes the n-bit input code at output. Out of 2^n only one output line that corresponds to n-bit input code will be ‘1’
at a time, while other output lines will be at ‘0’.

⚫ Control input of Decoder: A standard decoder typically has an additional input called Enable. Output is generated
according to input only when the Enable input is active; otherwise, all outputs are 0.

Active high Enable: decoder is enabled when Enable/EN=1

When EN=0, output is 0000 ⚫ Truth table of a 2:4 decoder with AB input and Y3Y2Y1Y0 output (Enable signal
irrespective of bits on input lines is active high)
Logic Expressions for Decoder
Output:

Y3=EN.(A.B) Y2=EN.(A.B’)
Y1=EN.(A’.B) Y0=EN.(A’.B’)

where A’ and B’ are the inversion of

A and B respectively.
 Flip Flop (FF)
⚫ One-bit memory which is used to store digital data Types of FF:
⚫ Example of Sequential digital circuit: Output depends on the present input conditions and 1. SR Flip Flop
previous output. Hence, it is different from combinational circuit like Encoder, decoder, 2. JK Flip Flop
MUX etc. in which output depends only on present input conditions 3. D Flip Flop
⚫ Bistable multivibrator: Output can be either of two stable states (0 and 1) indefinitely 4. T Flip Flop
⚫ Used to store single bit information

Difference between Combinational circuit and Sequential circuit using block diagram:

Combinational circuit Sequential circuit

SR Flip Flop:

SR Flip Flop using NAND Gates

JK Flip Flop:

Race Around Condition: Race around Condition in JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a
long period of time, then Q output will toggle as long as CLK is high, which makes the output of the flip-flop unstable
or uncertain. This problem is called race around condition in J-K flipflop.
D Flip Flop:

Characteristics equation:
Qnext =D

T Flip Flop:

T Flip Flop can be

implemented by short-circuit
of J and K input of JK Flip Flop

Characteristics equation:
Next state Qn+1=T XOR Qn

References:

1. https://www.geeksforgeeks.org/cmos-logic-gate/
2. https://www.geeksforgeeks.org/implementing-321-multiplexer-using-81-multiplexers/
3. https://www.electronics-tutorials.ws/transistor/tran_4.html
4. “Principles of Electronics” by Mehta and Mehta
5. https://www.electronics-tutorial.net/Digital-CMOS-Design/CMOS-Inverter/
6. https://byjusexamprep.com/cmos-inverter-i
7. https://electronics-fun.com/digital-decoder/
8. https://learn.circuitverse.org/docs/seq-msi/counters.html
9. https://byjus.com/gate/introduction-of-k-map-karnaugh-map-notes/