VHDL Tutorial

1. Introduction

 VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.
o Hardware description language with the goal to develop very high-speed integrated circuit.
o Allow you to describe and simulate complex digital systems

 VHDL language look similar as conventional programming languages, there are some important
differences.
o A hardware description language is inherently parallel, i.e. commands, which correspond to
logic gates, are executed (computed) in parallel, as soon as a new input arrives.
o A HDL program mimics the behavior of a physical, usually digital, system. It also allows
incorporation of timing specifications (gate delays) as well as to describe a system as an
interconnection of different components.

2. Levels of representation and abstraction

 A digital system can be represented at different levels of abstraction. This keeps the description and
design of complex systems manageable. Figure 1 shows different levels of abstraction.

Figure 1: Levels of abstraction: Behavioral, Structural and Physical

 The highest level of abstraction is the behavioral level that describes a system in terms of what it
does (or how it behaves) rather than in terms of its components and interconnection between them.
o A behavioral description specifies the relationship between the input and output signals.
This could be a Boolean expression or a more abstract description such as the Algorithmic
level.
o As an example, let us consider a simple XOR circuit. At the behavioral level this could be
expressed as,

F = (not a and b) or ( a and not b)

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  The structural level, on the other hand, describes a system as a collection of gates and components
that are interconnected to perform a desired function.
o For the example above, the structural representation is shown in Figure 2 below.

Figure 2: Structural representation of a “XOR” circuit.

 VHDL allows one to describe a digital system at the structural or the behavioral level.
 The behavioral level can be further divided into two kinds of styles: Data flow and Algorithmic.
The dataflow representation describes how data moves through the system. This is typically done in
terms of data flow between registers (Register Transfer level).

3. Basic Structure of a VHDL file

 A digital system in VHDL consists of a design entity that can contain other entities that are then
considered components of the top-level entity.
 Each entity is modeled by an entity declaration and an architecture body.
o One can consider the entity declaration as the interface to the outside world that defines the
input and output signals,
o while the architecture body contains the description of the entity and is composed of
interconnected entities, processes and components, all operating concurrently, as
schematically shown in Figure 3 below.

Figure 3: A VHDL entity consisting of an interface (entity declaration) and a body

(architectural description).

 VHDL Keywords and user-defined identifiers are case insensitive.

 Lines with comments start with two adjacent hyphens (--) and will be ignored by the compiler.
 VHDL also ignores line breaks and extra spaces.
 VHDL is a strongly typed language which implies that one has always to declare the type of every
object that can have a value, such as signals, constants and variables.

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a. Entity Declaration

o The entity declaration defines the NAME of the entity and lists the input and output ports.
The general form is as follows,

entity NAME_OF_ENTITY is [ generic generic_declarations);]

port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;

o The NAME_OF_ENTITY is a user-selected identifier

 Identifiers are user-defined words used to name objects in VHDL models. When
choosing an identifier one needs to follow these basic rules:
 May contain only alpha-numeric characters (A to Z, a to z, 0-9) and the
underscore (_) character
o The first character must be a letter and the last one cannot be an
underscore.
o An identifier cannot include two consecutive underscores.
o An identifier is case insensitive (ex. And2 and AND2 or and2 refer to
the same object)
o An identifier can be of any length.

 Examples of valid identifiers are: X10, x_10, My_gate1.

 Some invalid identifiers are: _X10, my_gate@input, gate-input.

o signal_names consists of a comma separated list of one or more user-selected identifiers that
specify external interface signals.
o mode: is one of the reserved words to indicate the signal direction:
o in – indicates that the signal is an input
o out – indicates that the signal is an output of the entity whose value can only be read by
other entities that use it.
o buffer – indicates that the signal is an output of the entity whose value can be read
inside the entity’s architecture
o inout – the signal can be an input or an output.
o type: a built-in or user-defined signal type. Examples of types are bit, bit_vector, Boolean,
character, std_logic, and std_ulogic.
o bit – can have the value 0 and 1
o bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
o std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9 values to indicate
the value and strength of a signal. Std_ulogic and std_logic are preferred over the bit or
bit_vector types.
o boolean – can have the value TRUE and FALSE
o integer – can have a range of integer values
o real – can have a range of real values
o character – any printing character
o time – to indicate time

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o generic: generic declarations are optional and determine the local constants used for timing
and sizing (e.g. bus widths) the entity. A generic can have a default value. The syntax for a
generic follows,

generic (
constant_name: type [:=value] ;
constant_name: type [:=value] ;
:
constant_name: type [:=value] );

o For the example of Figure 2 above, the entity declaration looks as follows.

-- comments: example of the xor circuit of fig. 2

entity XorGate is
port (in1, in2: in std_logic;
out1: out std_logic);
end XorGate;

o std_logic type is the preferred type of digital signals.

o In contrast to the bit type that can only have the values ‘1’ and ‘0’, the std_logic and
std_ulogic types can have nine values. This is important to describe a digital system
accurately
 binary values 0 and 1,
 unknown value X,
 uninitialized value U,
 “-” for don’t care,
 Z for high impedance,
 and several symbols to indicate the signal strength (e.g. L for weak 0, H for weak 1,
W for weak unknown).
o The std_logic type is defined in the std_logic_1164 package of the IEEE library.
o Library and Packages: library and use keywords
 A library can be considered as a place where the compiler stores information about a
design project.
 A VHDL package is a file or module that contains declarations of commonly used
objects, data type, component declarations, signal, procedures and functions that can
be shared among different VHDL models.
 std_logic is defined in the package ieee.std_logic_1164 in the ieee library. In order
to use the std_logic one needs to specify the library and package. This is done at the
beginning of the VHDL file using the library and the use keywords as
follows:

library ieee;
use ieee.std_logic_1164.all;

 The .all extension indicates to use all of the ieee.std_logic_1164 package.

 The Xilinx Foundation Express comes with several packages. ieee Library:
 std_logic_1164 package: defines the standard datatypes

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  std_logic_arith package: provides arithmetic, conversion and comparison
functions for the signed, unsigned, integer, std_ulogic, std_logic and
std_logic_vector types
 std_logic_unsigned
 std_logic_misc package: defines supplemental types, subtypes, constants and
functions for the std_logic_1164 package.

 To use any of these one must include the library and use clause:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

b. Architecture body

o The architecture body specifies how the circuit operates and how it is implemented.
o an entity or circuit can be specified in a variety of ways, such as behavioral, structural
(interconnected components), or a combination of the above.

o The architecture body looks as follows,

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations

begin
-- Statements

end architecture_name;

Behavioral model
o The architecture body for the example of Figure 2, described at the behavioral level, is given
below,

architecture behavioral of XorGate is

begin
out1<=(not in1 and in2) or ( in1 and not in2);
end behavioral;

o The architecture name can be any legal identifier.

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o The “<= ” symbol represents an assignment operator and assigns the value of the expression
on the right to the signal on the left.

o Another solution of a two-input XOR gate is shown below.

entity XOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XOR2;

architecture behavioral_xor of XOR2 is

-- signal declaration (of internal signals X, Y)
signal X, Y: std_logic;
begin
X <= (not A) and B;
Y <= A and (not B);
Z <= X or Y;
End behavioral_xor;

o Logic operators that are allowed are: and, or, nand, nor, xor, xnor and
not. In addition, other types of operators including relational, shift, arithmetic are allowed.

o Concurrency
 It is worth pointing out that the signal assignments in the above examples are
concurrent statements.
 For instance, when the input A changes, the internal signals X and Y change values
that in turn causes the last statement to update the output Z. There may be a
propagation delay associated with this change.
 The execution of the statements is determined by the flow of signal values. As a
result, the order in which these statements are given does not matter (i.e., moving the
statement for the output Z ahead of that for X and Y does not change the outcome).
This is in contrast to conventional, software programs that execute the statements in
a sequential or procedural manner.

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Experiment 1: Write VHDL code for realize all logic gates.
a) AND Gate: A Logic circuit whose output is logic ‘1’ if and only if all of its inputs are logic ‘1’.

Solution:
VHDL Code for AND Gate:
-- File : andgate.vhd
-- Entity : andgate

-- Description : VHDL code to realize AND gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
Entity Declarations
entity andgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic );
end andgate;
architecture Behavioral of andgate is
begin
Y<= A and B ;
end Behavioral;

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 b) OR Gate: A logic gate whose output is logic ‘0’ if and only if all of its inputs are logic ‘0’.

Solution:
VHDL Code for OR Gate:
-- File : orgate.vhd
-- Entity : orgate
-- Description : VHDL code to realize OR gate functionality
--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
Entity Declarations
entity orgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic);
end orgate;
architecture Behavioral of orgate is
begin
Y<= A or B ;
end Behavioral;

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 c) NOT Gate: A logic gate whose input is complement of its input.

Solution:
VHDL Code for NOT Gate:
-- File : notgate.vhd
-- Entity : notgate

-- Description : VHDL code to realize NOT gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;

Entity Declarations
entity notgate is
Port( A : in std_logic;
Y : out std_logic);
end notgate;
architecture Behavioral of notgate is
begin
Y<= not A ;
end Behavioral;

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 d) X-OR (Exclusive OR): A logic gate whose output is logic ‘0’ when all the inputs are equal and
logic ‘1’ when they are un equal.

Solution:
VHDL Code for XOR Gate:
-- File : xorgate.vhd
-- Entity : xorgate
-
-- Description : VHDL code to realize EX-OR gate functionality
--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
Entity Declarations
entity xorgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic);
end xorgate;
architecture Behavioral of xorgate is
begin
Y<= A xor B ;
end Behavioral;

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