Presented by TEAM ID:13 Devtanu Barman(22B3904) Sanjay Kumar Meena(22B3978) Archisman Bhattacharjee(22B2405) Shreyash Wanjari(22B3926) Description:-
Based on the Little Computer Architecture, IITB-RISC-23 is a 16-
bit extremely basic computer designed for education. An 8- register, 16-bit computer system is the IITB-RISC-23. R0 through R7 are its eight general purpose registers. Program Counter is always stored in Register R0. Every address consists of instructions and bytes. It always retrieves two bytes for the data and instructions. The two flags in the condition code register used by this architecture are the Carry flag (C) and the Zero flag (Z). Despite its extreme simplicity, the IITB-RISC-23 has sufficient generality to tackle challenging issues. Multiple load and store operations as well as predicted instruction execution are supported by the architecture. There are a total of 14 instructions in the three machine-code instruction forms (R, I, and J type). Components: 1. IR Memory : Contains all the instruction PC In : Takes input the current PC IR Out : Gives the corresponding instruction from memory.
2. IR Decoder : Decodes the instruction
IR In : Takes the corresponding instruction as input Its Output are : - Opcode - Ra (First operand) - Rb (Second operand) - Rc (Third operand) - Imm6 (6 bit immediate data) - Imm9 (9 bit immediate data)
3. Register File : Contain 8 registers
Its inputs are: - RF_A1 : To select register to read - RF_A2 : To select register to read - RF_A3 : To select register to write - RF_D3 : Data to write - PC in - Clock - Reg_en : Write enable signal - Reset : Reset signal Its Output are : - RF_D1 : Data of Register selected - RF_D2 : Data of Register selected - PC out 4. Arithmetic Logic Unit (ALU) : Performs ADD and NAND Input : - Ir_in : selects operation - Alu_in_a : First input - Alu_in_b : Second input Output : - Alu_out_c : Output
5. Sign-extender 7 and sign-extender 10
- Converts the 7 bit and 10 bit inputs to 16 bit output 6. Adder : Takes two input and add them 7. PC Adder : updates PC after every cycle (PC+1) 8. Comparator : Compares 2 input Input: - Input 1 - Input 2 Output: - El signal : is set if both inputs are equal - Lte signal : is set if input 1 is less than input 2 9. Complement : Outputs the complement of a 16 bit input 10. Data memory : Contains data in which all the operations are performed Read: - Memory-read-address : input address to the memory to read the data - Memory-data-output : data corresponding to the input address Write: - Memory-write-address : input address to the memory to write the data - Memory-write-data :input data to write at the input address Pipeline Register Content Stages of Pipeline :
Instruction Fetch (IF): In this stage the instruction is
fetched by the processor and the program counter(PC) is incremented (PC++). Instruction Decode (ID): In this stage the fetched instruction is decoded into different signals such as opcode, operand ra, operand rb, operand rc, imm6, imm9. Register Read (RR): In this stage the decoded instruction is used to read the necessary registers from the register file (RF). Instruction Execute (IE): This stage mainly deals with execution of the instruction with the help of ALU, adder and also modifying the value of carry and zero flag wherever required. Memory Access (MA): In this stage memory-read and memory-write operations are performed. Write Back (WB): In this stage all the final results obtained after 5th stage are written back to the register. Testing : Complete Output file:-
