Questions 1

An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-1, source reg-2

Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2

I2: SUB R5, R3, R4

I3: ADD R3, R5, R6

I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

A
Correct Answer
There is a RAW dependency on R3 between I1 and I2
B
There is a WAR dependency on R3 between I1 and I3
C
There is a RAW dependency on R3 between I2 and I3
D
There is a WAW dependency on R3 between I3 and I4

Explanation
A pipelined processor processes multiple instructions simultaneously at different stages of their execution. Understanding data dependencies
in this context is crucial for identifying potential hazards. The common types of dependencies are Read After Write (RAW), Write After
Read (WAR), and Write After Write (WAW).

Let's analyze each of the given instructions:

I1: DIV R3, R1, R2

I2: SUB R5, R3, R4

I3: ADD R3, R5, R6

I4: MUL R7, R3, R8

Now, let's evaluate each statement:

Option A: There is a RAW dependency on R3 between I1 and I2

RAW (Read After Write) dependency occurs when an instruction depends on the result of a previous instruction. Here, I2 reads R3, which is
written by I1. Thus, there is a RAW dependency between I1 and I2.

So, this statement is True.

Option B: There is a WAR dependency on R3 between I1 and I3

WAR (Write After Read) dependency occurs when a later instruction overwrites a register that a previous instruction reads. In this case,
there is no WAR dependency, as I3 writes to R3, which I1 also writes to, but not reads from.

So, this statement is False.

Option C: There is a RAW dependency on R3 between I2 and I3

This statement examines if I3 reads R3, which is previously affected by I2. However, I3 reads R5 (output of I2), but writes to R3. Thus,
there is no RAW dependency on R3 between I2 and I3.

So, this statement is False.

Option D: There is a WAW dependency on R3 between I3 and I4

WAW (Write After Write) dependency occurs when two instructions write to the same register. Here, I3 writes to R3, and the value of R3 is
used by I4 (not written by I4). Thus, there is no WAW dependency.

So, this statement is False.

Considering all analysis above, only Option A is correct.

Questions 2

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and
Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?
A
Correct Answer
In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a
later instruction
B
Correct Answer
In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction
C
Correct Answer
Forwarding cannot prevent all pipeline stalls
D
Forwarding does not require any extra hardware to retrieve the data from the pipeline stages
Explanation
Let's analyze each statement about forwarding in a pipelined processor:

Option A: In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the
destination stage of a later instruction.

 This statement is CORRECT. Forwarding is a technique used in pipelined processors to resolve data hazards. It allows the
result of an instruction to be forwarded directly to a later instruction that needs it, bypassing the need to wait for it to be written
back to the register file.

Option B: In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next
instruction.

 This statement is CORRECT. In a common forwarding scenario, the result of a load instruction (available at the end of the
MEM stage) can be forwarded to the EX stage of the next instruction if that instruction depends on the loaded value.

Option C: Forwarding cannot prevent all pipeline stalls.

 This statement is CORRECT. While forwarding is an effective technique for resolving many data hazards, it cannot resolve all
types of hazards. For example, hazards caused by load instructions that need to access memory may still require stalls.

Option D: Forwarding does not require any extra hardware to retrieve the data from the pipeline stages
  This statement is INCORRECT. Forwarding requires additional hardware components called forwarding paths or multiplexers.
These components are used to select the appropriate data to be forwarded from the different pipeline stages.

Therefore, the correct statements are Options A, B, and C.

Question 3

Register renaming is done in pipelined processors

A
as an alternative to register allocation at compile time

B
for efficient access to function parameters and local variables

C
Correct Answer
to handle certain kinds of hazards

D
as part of address translation

Question 4
For a pipelined 𝐶𝑃𝑈 with a single 𝐴𝐿𝑈, consider the following situations
1. The 𝑗+1 instruction uses the result of the 𝑗-𝑡ℎ instruction as an operand
2. The execution of a conditional jump instruction
3. The 𝑗-𝑡ℎ and 𝑗+1 instruction require the 𝐴𝐿𝑈 at the same time

Which of the above can cause a hazard?

A
1 and 2 only

B
2 and 3 only

C
3 only

D
Correct Answer
ALL the three

Question 5

Comparing the time 𝑇1 taken for a single instruction on a pipelined 𝐶𝑃𝑈 with time 𝑇2 taken on a non-pipelined but identical 𝐶𝑃𝑈, we can
say that
A
𝑇1≤𝑇2

B
Correct Answer
𝑇1≥𝑇2

C
𝑇1<𝑇2

D
𝑇1 is 𝑇2 plus the time taken for one instruction fetch cycle
Question 6
A 5-stage pipelined processor has Instruction Fetch (𝐼𝐹), Instruction Decode (𝐼𝐷), Operand Fetch (𝑂𝐹), Perform Operation (𝑃𝑂) and Write
Operand (𝑊𝑂) stages. The 𝐼𝐹,𝐼𝐷,𝑂𝐹 and 𝑊𝑂 stages take 1 clock cycle each for any instruction. The 𝑃𝑂 stage takes 1 clock cycle
for 𝐴𝐷𝐷 and 𝑆𝑈𝐵 instructions, 3 clock cycles for 𝑀𝑈𝐿 instruction, and 6 clock cycles for 𝐷𝐼𝑉 instruction respectively. Operand forwarding
is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?

A
13

B
Correct Answer
15

C
17

D
19

Question

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4, in stages 𝑆1,𝑆2,𝑆3,𝑆4 is shown

below.

What is the number of cycles needed to execute the following loop?

For (𝑖=1 to 2) {I1;I2;I3;I4;}
A
16
B
Correct Answer
23
C
28
D
30

question
The following code is to run on a pipelined processor with one branch delay slot
I1:𝐴𝐷𝐷𝑅2←𝑅7+𝑅8I2:𝑆𝑈𝐵𝑅4←𝑅5−𝑅6I3:𝐴𝐷𝐷𝑅1←𝑅2+𝑅3I4:𝑆𝑇𝑂𝑅𝐸𝑀𝑒𝑚𝑜𝑟𝑦[𝑅4]←𝑅1𝐵𝑅𝐴𝑁𝐶𝐻𝑡𝑜𝐿𝑎𝑏𝑒𝑙𝑖𝑓𝑅1==0
Which of the instructions I1,I2,I3 or I4 can legitimately occupy the delay slot without any other program modification?
A
I1
B
I2
C
I3
D
Correct Answer
I4

question

The performance of a pipelined processor suffers if

A
Your answer
The pipeline stages have different delays
B
Consecutive instructions are depend on each other
C
The pipeline stages share single hardware resources
D
Correct Answer
All of the above

question

Which of the following are NOT true in a pipelined processor?

1. Bypassing can handle all RAW hazards
2. Register renaming can eliminate all register carried WAR hazards
3. Control hazard penalties can be eliminated by dynamic branch prediction.
A
1 and 2 only
B
Your answer
1 and 3 only
C
Correct Answer
2 and 3 only
D
1,2 and 3

question
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
1. Function locals and parameters
2. Register saves and restores
3. Instruction fetches
A
Correct Answer
1 only
B
2 only
C
3 only
D
1,2 and 3
question

Consider a pipelined processor with the following four stages

𝐼𝐹: Instruction Fetch
𝐼𝐷: Instruction Decode and Operand Fetch
𝐸𝑋: Execute
𝑊𝐵: Write Back

The 𝐼𝐹,𝐼𝐷 and 𝑊𝐵 stages take one clock cycle each to complete the operation. The number of clock cycles for the 𝐸𝑋 stage depends on the
instruction. The 𝐴𝐷𝐷 and 𝑆𝑈𝐵 instructions need 1 clock cycle and the 𝑀𝑈𝐿 instruction needs 3 clock cycles in the 𝐸𝑋 stage. Operand
forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

A
7
B
Correct Answer
8
C
10
D
14

question

A CPU has five stages pipeline and runs at 1 𝐺𝐻𝑧 frequency. Instruction fetch happens in the first stage of the pipeline. A conditional
branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching
new instruction following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20%
are conditional branches. If each instruction takes one cycle to complete on average, then total execution time of the program is
A
1.0 second
B
Your answer
1.2 seconds
C
Correct Answer
1.4 seconds
D
1.6 seconds