8051 Microcontroller
8051 Microcontroller
Microcontroller
• A smaller computer
on a CHIP
• On-chip RAM, ROM,
I/O Ports, Timer,
Serial Controller…
• Example: Motorola’s 2
8051
Microcontroller
8051 CPU
Operation
1. Features
2. Pin Diagram
3. Block Diagram
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Pin Diagram
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Pin Description of the
8051
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XTAL1 and XTAL2
• The 8051 has an on-chip oscillator but requires an external crystal to run it
• A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2
(pin18)
• The quartz crystal oscillator also needs two capacitors of 30 pF value
• The original 8051 operates at 12 MHZ
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RST
• RESET pin is an input and is active high (normally low)
• Upon applying a high pulse to this pin, the microcontroller will
reset and terminate all activities
• This is often referred to as a power-on reset
• Activating a power-on reset will cause all values in the registers
to be lost
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EA’
• EA’, “external access’’, is an input pin and must be connected to Vcc
or GND
• The 8051 family members all come with on-chip ROM to store
programs and also have an external code and data memory.
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I/O Port Pins
• The four 8-bit I/O ports P0, P1,
P2 and P3 each uses 8 pins.
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Port 1 and Port 2
• In 8051-based systems with no external
memory connection:
• Both P1 and P2 are used as simple I/O.
• In 8051-based systems with external
memory connections:
• Port 2 must be used along with P0 to provide the
16-bit address for the external memory.
• P0 provides the lower 8 bits via A0 – A7.
• P2 is used for the upper 8 bits of the 16-bit
address, designated as A8 – A15, and it cannot
be used for I/O.
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P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits
the high order address byte during fetches from
external program memory and during accesses to
external data memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
8051 Microcontroller
serves special features as explained. 16
PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
ALE O Address Latch Enable: Output pulse for latching the low
byte of the address during an access to external
memory.
PSEN* O Program Store Enable: The read strobe to external
program memory. When executing code from the
external program memory, PSEN* is activated twice
each machine cycle, except that two PSEN*
activations are skipped during each access to external
data memory.
EA*/VPP I External Access Enable/Programming Supply Voltage:
EA* must be externally held low to enable the device to
fetch code from external program memory locations. If
EA* Is held high, the device executes from internal
program memory. This pin also receives the
programming supply voltage Vpp during Flash
8051 Microcontroller programming. (applies for 89c5x MCU's) 17
CPU
Bus Serial
OSC 4 I/O Ports
Control Port
TXD RXD
P0 P1 P2 P3
8051 Peripheral Overview
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Microcontroller
8051 Interrupts
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Six Interrupts in 8051
Six interrupts are allocated as follows:
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Steps in Executing an Interrupt
1. It finishes the instruction it is executing and
saves the address of the next instruction
(PC) on the stack.
2. It also saves the current status of all the
interrupts internally (i.e: not on the stack).
3. It jumps to a fixed location in memory,
called the interrupt vector table, that
holds the address of the ISR.
4. The microcontroller gets the address of the
ISR from the interrupt vector table and
jumps to it.
5. It starts to execute the interrupt service
subroutine until it reaches the last
instruction of the subroutine which is RETI
(return from interrupt).
6. Upon executing the RETI instruction, the
microcontroller returns to the place 25
where it was interrupted.