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bcs302 - Lab - Experiment List

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Swetha Manjunatha
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9 views1 page

bcs302 - Lab - Experiment List

Uploaded by

Swetha Manjunatha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Table of contents

Sl.No Particulars Page No


1. Introduction to ORCAD simulation 1

2. Given a 4-variable logic expression, simplify it using appropriate 6


technique and simulate the same using basic gates
3. Design a 4 bit full adder and subtractor and simulate the same using 7
basic gates.
4. Introduction to Verilog 9
5. Design Verilog HDL to implement simple circuits using structural, 17
Data flow and Behavioural model
6. Design Verilog HDL to implement Binary Adder-Subtractor – Half and 18
Full Adder, Half and Full Subtractor
7. Design Verilog HDL to implement Decimal adder. 20
8. Design Verilog program to implement Different types of multiplexer 21
like 2:1, 4:1 and 8:1
9. Design Verilog program to implement types of De-Multiplexer 24
10. Design Verilog program for implementing various types of Flip-Flops 26
such as SR, JK and D
11. Extra experiments 29
12. Viva -voce questions 31

Course outcomes (Course Skill Set):


At the end of the course, the student will be able to:
CO1: Apply the K–Map techniques to simplify various Boolean expressions.
CO2: Design different types of combinational and sequential circuits along with
Verilog programs.
CO3: Describe the fundamentals of machine instructions, addressing modes and
Processor performance.
CO4: Explain the approaches involved in achieving communication between processor
and I/O devices.
CO5: Analyze internal Organization of Memory and Impact of cache/Pipelining on
Processor Performance.

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