Scribd
Upload
32 views4 pages

Prabhakar INTEL

Uploaded by

avanti sarnaik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
32 views4 pages

Prabhakar INTEL

Uploaded by

avanti sarnaik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Prabhakar.

Mobile No: +91-8682069932


Email: [email protected]

CAREER OBJECTIVE

To pursue a challenging career and be a part of progressive organization that gives a scope to enhance my
knowledge and utilizing my skills towards the growth of the organization.

SUMMARY:

 Around 6 years of experience in Post/Pre silicon, Server Dimm & PnP Power Management FV
Validation.
 Proficient in handling System validation, Debugging and Scripting.
 Knowledge of different testing and debugging to figure out the issues.
 Quick learner and confident professional with a passion for learning new technologies.
 Recognized for the work done under high pressure environment for super critical projects.
 Excellent written and verbal communication skills

PROFESSIONAL EXPERIENCE:

INTEL Technology System Validation Engineer


March 2022 – Till Date
Domain : Memory FV, Power Management
Location: Bangalore

Roles & Responsibilities:

 IP Level validation, Flow verification and debugging


 Actively involving on Power ON and identifying the Bugs
 Good Knowledge on Power Management features (C6, PC6, Latency isolation)
 Lower Power state verification on both core & uncore side
 Performance/frequency tunning based on load level.
 Frequency and Power stability via Spec Power load line, & SIR.
 Good Understanding on P-states, & C-states
 Achieve good performance with minimal power by tuning the algorithms.
 Stress by keeping few and all Cores to max to encounter issues.
 Reset Stagewise FSM Verification.
 Analyzing the issues with help of LTB and ITP
 Create contents to improve Power and Battery Life
 Understands System with HW/FW/SW components as a whole, drives test execution and debug with cross
functional teams.
 Creates, defines, and develops system validation environment and test suites.
 Power and Thermal utilization and throttling functionality.
 Good Knowledge on Memory, Bios Flow, Security and PCIe
 Pre-Silicon PM verification & Issue isolation via FSDB waveform.
HCL Technology Lead Engineer
October 2020 – March 2022
Domain : Server Persistent Memory Validation
Client : Intel (Bangalore )

Roles & Responsibilities:

 Memory Dimm Validation, Debugging and Automation


 Experienced in 2 Sockets & 4 Sockets Server platform on both 1DPC & 2DPC.
 Explored on RMT and new feature testing.
 Good understanding on RAS feature
 Memory Wearing out & Disturb technique.
 Need to segregate the Dimm issue based on training phase.
 Log analyzing for CPS specific issue’s and to provide 1st level debug update.
 Different kind of Workload validation with different goal.
 Test case automation using python and PowerShell script.
 Hands on some of the python modules – Re, Sys, OS, Pretty Table, Paramiko.
 Data analyzing from the logs whether the value meets the expected band value.
 Script Modifications Based on the new requirement.
 Raising the ticket for failure and update the same with more failure info from logs.
 Good understanding about the new storage features like Flash memory.
 Exploring on New memory technology CXL.

UST Global, Bangalore Validation Engineer


June 2017 – October 2020
Domain: Semiconductor
Client : Intel (Bangalore)

A Windows platform validation team provides an integrated framework to capture the client's requirements and
translate them into a detailed test plan with the necessary test tools, environment, and reporting to ensure
successful validation. It also provides integrated custom and off-the shelf testing and validation tools with
automated testing facilities.
Doing firmware validation like BIOS, Security, Storage, Power management etc. and moved to debug to root
cause the issues and L1 development.

Roles & Responsibilities:

 Automate the installation process and area where we can avoid manual invention using python and
PowerShell script.
 Good understanding on security feature like TXT, Boot Guard & Bios Guard.
 Working on test cases development and log analyzing using python and PowerShell script.
 Finding bugs and taking careful notes of where they are and where they can be reproduced.
 Attending review meetings to analyze client requirements and arranging test environment for the
execution of test cases.
 Having experience on storage domain with NVME, PCIe.
 Isolate the issue and provide in-person assistance to fix issues.
 Analyzing the memory dump using windbg.
 Analyzing the Hang using ITP

ELECTRICITY DEPARTMENT PONDICHERRY Graduate Apprentice


July 2014 – July 2015

 I was worked in Transformer section as a Graduate Apprentice trainee for 1 yr and I have knowledge in
Current transformer, Lightning arrestor and etc.

TECHNICAL SKILL SET USED:

Language : C, PowerShell, Python.


Primary Skill : Server dimm, Security, PnP, First Boot and debug.
Secondary Skill : Manual and Automation testing.
Debugging Tools : LTB, Windbg, ITP, Signal Analyzing, Spec Power
OS : Linux and Windows

AWARDS

 R&R Award from Intel account under Execution Mindset category for delivering the project with good
quality and for being quick learner and Multitasked.
 Special Award from Intel account for Driven a QSR (Quarterly security Release) team without any
escalation and provide crispy results.
 Best performer & debugger award in Optane project

EDUCATION

Education Board or University Year Percentage Secured


10th State Board 2007 89.8%

12th State Board 2009 70.66%

B. Tech (EEE) Pondicherry University 2009 -2013 7.46 out of 10.00

ACADEMIC PROJECT

 Design and analyze of photo voltaic cell using soft switching boost converter with MPPT algorithm.
Description: To degrade switching losses and get maximum power from the PV panel with the
help of MPPT algorithm.

PERSONAL DETAILS

Name : Prabhakar. P
Date of Birth : 10th December 1991
Marital Status : Married
Nationality : Indian
Passport : Yes
Languages : English, Tamil
Permanent Address : 78, Marutham Street, Priyadharshini nagar, Nainarmandabam, Puducherry-4.

You might also like