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VLSI Lab Manual

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VÑ ÇREATIONZ
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19 views11 pages

VLSI Lab Manual

Uploaded by

VÑ ÇREATIONZ
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EXP 1: 32 BIT ALU

module alu32(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;

always@(*)
begin
case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b100:y=a+b; //Addition
3'b101:y=a-b; //Subtraction
3'b110:y=a*b; //Multiply
default:y=32'bx;

endcase
end
endmodule

TESTBENCH
module alu32_tb;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;

alu32 dut(.y(y),.a(a),.b(b),.f(f));
initial begin
a=32'h00000000;
b=32'hffffffff;
f=3'b000; #10;
f=3'b001; #10;
f=3'b010; #10;
f=3'b011; #10;
f=3'b100; #10;
f=3'b101; #10;
f=3'b110; #10;
end
endmodule
output:

EXP 2: FOUR BIT FULL ADDER

module fourbitadder(A,B,C0,S);
input [3:0]A,B;
input C0;
output [3:0]S;
wire C1,C2,C3,C4;
fulladder fa0 (A[0],B[0],C0,S[0],C1);
fulladder fa1 (A[1],B[1],C1,S[1],C2);
fulladder fa2 (A[2],B[2],C2,S[2],C3);
fulladder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

module fulladder(A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
assign COUT = (A&B) | (CIN&(A^B));
endmodule

TESTBENCH
module fourbitadder_t;

reg [3:0] A;
reg [3:0] B;
reg C0;
wire [3:0] S;

fourbitadder uut (.A(A), .B(B), .C0(C0), .S(S));


initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
end

endmodule

output:

EXP 3: FLIP FLOPS


D FLIP FLOP

module dff(d,clk,q,qb);
input d,clk;
output reg q=0,qb=1;
always@(posedge clk)
begin
case(d)
1'b0:q=0;
1'b1:q=1;
default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module dff_t;
reg d;
reg clk;
wire q;
wire qb;
dff uut (.d(d), .clk(clk), .q(q), .qb(qb));

initial
clk =1;
always #5 clk=~clk;
initial begin
d=0; #10;
d=1; #10;
end
endmodule

output:

SR FLIP FLOP

module srff(sr,clk,q,qb);
input[1:0]sr;
input clk;
output reg q=0,qb=1;
always@(posedge clk)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bz;
default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module srff_t;
reg [1:0] sr;
reg clk;
wire q;
wire qb;
srff uut (.sr(sr), .clk(clk), .q(q), .qb(qb));

initial
clk=1
always #5 clk=~clk;
initial begin
sr=2’b00; #10;
sr=2’b01; #10;
sr=2’b10; #10;
sr=2’b11; #10;
end
endmodule

output:

JK FLIP FLOP

module jkff(jk,clk,q,qb);
input[1:0]jk;
input clk;
output reg q=0,qb=1;
always@(posedge clk)
begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module jkff_t;
reg [1:0] jk;
reg clk;
wire q;
wire qb;

jkff uut (.jk(sjk), .clk(clk), .q(q), .qb(qb));

initial
clk=1
always #5 clk=~clk;
initial begin
jk=2’b00; #10;
jk=2’b01; #10;
jk=2’b10; #10;
jk=2’b11; #10;
end
endmodule

output:
LATCHES
D LATCH

module dlatch(e,d,q,qb);
input e,d;
output reg q=0,qb=1;
always@(e)
begin
if(e)
q=d;
q=~qb;
end
endmodule

TEST BENCH
module dlatch_t;

reg e;
reg d;
wire q;
wire qb;

dlatch uut (.e(e), .d(d), .q(q), .qb(qb));

initial
e=1;
always #3 e=~e;
initial
d=0;
always #10 d=~d;

endmodule

output:
SR LATCH

module srlatch(sr,en,q,qb);
input[1:0]sr;
input en;
output reg q=0,qb=1;
always@(en)
begin
if(en)
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bz;
default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module srlatch_t;

reg [1:0] sr;


reg en;
wire q;
wire qb;

srlatch uut (.sr(sr), .en(en), .q(q), .qb(qb));

initial
en=1;
always #3 en=~en;
initial begin
sr=00; #10;
sr=01; #10;
sr=10; #10;
sr=11; #10;
end

endmodule

output:
JK LATCH

module jklatch(jk,en,q,qb);
input[1:0]jk;
input en;
output reg q=0,qb=1;
always@(en)
begin
if(en)
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module jklatch_t;

reg [1:0] jk;


reg en;
wire q;
wire qb;

jklatch uut (.jk(jk), .en(en), .q(q), .qb(qb));

initial
en=1;
always #3 en=~en;
initial begin
jk=00; #10;
jk=01; #10;
jk=10; #10;
jk=11; #10;

end
endmodule

output:
EXP 4: BOOTH MULTIPLIER

module boothmul(PRODUCT, A, B);


output reg signed [7:0] PRODUCT;
input signed [3:0] A, B;
reg [1:0] temp;
integer i;
reg e;
reg [3:0] B1;
always @(A,B)
begin
PRODUCT = 8'd0;
e = 1'b0;
B1 = -B;
for (i=0; i<4; i=i+1)
begin
temp = { A[i], e };
case(temp)
2'd2 : PRODUCT[7:4] = PRODUCT[7:4] + B1;
2'd1 : PRODUCT[7:4] = PRODUCT[7:4] + B;
endcase
PRODUCT = PRODUCT >> 1;
PRODUCT[7] = PRODUCT[6];
e=A[i];
end
end
endmodule

TESTBENCH
module boothmul_t;

reg [3:0] A;
reg [3:0] B;
wire [7:0] PRODUCT;

boothmul uut (.PRODUCT(PRODUCT), .A(A), .B(B));

initial begin
A=0; B=0; #100;
A=1; B=0; #100;
A=7; B=5; #100;
A=-7; B=5; #100;
A=8; B=9; #100;
A=8; B=-9; #100;
end
endmodule
output:

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