Exercise 2
Exercise 2
2.1. For the following C statement, write the corresponding RISC-V assembly
code. Assume that the C variables f, g, and h, have already been placed in
registers x5, x6, and x7 respectively. Use a minimal number of RISC-V
assembly instructions.
f = g + (h − 5);
2.2. Write a single C statement that corresponds to the two RISC-V assembly
instructions below.
add f, g, h
add f, i, f
2.3. For the following C statement, write the corresponding RISC-V assembly
code. Assume that the variables f, g, h, i, and j are assigned to registers
x5, x6, x7, x28, and x29, respectively. Assume that the base address of the
arrays A and B are in registers x10 and x11, respectively.
B[8] = A[i−j];
2.4. For the RISC-V assembly instructions below, what is the corresponding C
statement? Assume that the variables f, g, h, i, and j are assigned to
registers x5, x6, x7, x28, and x29, respectively. Assume that the base
address of the arrays A and B are in registers x10 and x11, respectively.
slli x30, x5, 3 // x30 = f*8
add x30, x10, x30 // x30 = &A[f]
slli x31, x6, 3 // x31 = g*8
add x31, x11, x31 // x31 = &B[g]
ld x5, 0(x30) // f = A[f]
addi x12, x30, 8
ld x30, 0(x12)
add x30, x30, x5
sd x30, 0(x31)
2.5. Show how the value 0xabcdef12 would be arranged in memory of a little-
endian and a big-endian machine. Assume the data are stored starting at
address 0 and that the word size is 4 bytes.
2.6. Translate 0xabcdef12 into decimal.
2.7. Translate the following C code to RISC-V. Assume that the variables f, g,
h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively.
Assume that the base address of the arrays A and B are in registers x10
and x11, respectively. Assume that the elements of the arrays A and B are
8-byte words:
B[8] = A[i] +A[j];
2.8. Translate the following RISC-V code to C. Assume that the variables f, g,
h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively.
Assume that the base address of the arrays A and B are in registers x10
and x11, respectively.
addi x30, x10, 8
addi x31, x10, 0
Chapter_02 Exercises
sd x31, 0(x30)
ld x30, 0(x30)
add x5,x30, x31
2.9. For each RISC-V instruction in Exercise 2.8, show the value of the
opcode (op), source register (rs1), and destination register (rd) fields. For
the I-type instructions, show the value of the immediate field, and for the
R-type instructions, show the value of the second source register (rs2).
For non U- and UJ-type instructions, show the funct3 field, and for R-type
and Stype instructions, also show the funct7 field.
2.10. Assume that registers x5 and x6 hold the values 0x8000000000000000
and 0xD000000000000000, respectively.
a. What is the value of x30 for the following assembly code?
add x30, x5, x6
b. Is the result in x30 the desired result, or has there been
overflow?
c. For the contents of registers x5 and x6 as specified above, what
is the value of x30 for the following assembly code?
sub x30, x5, x6
d. Is the result in x30 the desired result, or has there been
overflow?
e. For the contents of registers x5 and x6 as specified above, what
is the value of x30 for the following assembly code?
add x30, x5, x6
add x30, x30, x5
f. Is the result in x30 the desired result, or has there been
overflow?