Answer Key: Assistant Professor (VLSI Design & Tech.

)
Q No Key Q No Key
1 B 26 A
2 D 27 D
3 B 28 A
4 A 29 C
5 D 30 C
6 C 31 D
7 A 32 C
8 B 33 C
9 C 34 A
10 A 35 A
11 B 36 B
12 D 37 C
13 B 38 C
14 D 39 A
15 D 40 B
16 A 41 B
17 D 42 D
18 C 43 A
19 B 44 D
20 B 45 A
21 B 46 B
22 B 47 C
23 C 48 B
24 D 49 D
25 D 50 B
Test Booklet Test Booklet No.
Series
Test Booklet for the Post of
A Assistant Professor VLSI Design & Technology

Name of Applicant ............................................................ Answer Sheet No. ....................................

Applicant ID/Roll No. : ............................................... Signature of Applicant : .................................

Date of Examination: .......................................... Signature of the Invigilator(s)

1. ..................................................

Time of Examination : ....................................... 2. ..................................................

Duration : 1 Hour] [Maximum Marks : 50

IMPORTANT INSTRUCTIONS
(i) The question paper is in the form of Test-Booklet containing 50 (Fifty) questions. All questions are
compulsory. Each question carries four answers marked (A), (B), (C) and (D), out of which only
one is correct. Choose the correct option or the most appropriate option.
(ii) On receipt of the Test-Booklet (Question Paper), the candidate should immediately check it and
ensure that it contains all the pages, i.e., 50 questions. Discrepancy, if any, should be reported by
the candidate to the invigilator immediately after receiving the Test-Booklet.
(iii) A separate Answer-Sheet is provided with the Test-Booklet/Question Paper. On this sheet there are
50 rows containing four circles each. One row pertains to one question.
(iv) The candidate should write his/her Application ID/Roll number at the places provided on the cover
page of the Test-Booklet/Question Paper and on the Answer-Sheet and NOWHERE ELSE.
(v) No second Test-Booklet/Question Paper and Answer-Sheet will be given to a candidate. The
candidates are advised to be careful in handling it and writing the answer on the Answer-Sheet.
(vi) For every correct answer of the question One (1) mark will be awarded. There will be negative
marking and 1/4 (0.25) mark will be deducted for every incorrect answer.
(vii) Marking shall be done only on the basis of answers responded on the Answer-Sheet.
(viii) To mark the answer on the Answer-Sheet, candidate should darken the appropriate circle in the row
of each question with Blue or Black pen.
(ix) For each question only one circle should be darkened as a mark of the answer adopted by the
candidate. If more than one circle for the question are found darkened or with one black circle any
other circle carries any mark, the answer will be treated as incorrect.
(x) The candidates should not remove any paper from the Test-Booklet/Question Paper. Attempting to
remove any paper shall be liable to be punished for use of unfair means.
(xi) Rough work may be done on the blank space provided in the Test-Booklet/Question Paper only.
(xii) Mobile phones (even in Switch-off mode) and such other communication/programmable devices
are not allowed inside the examination hall.
(xiii) No candidate shall be permitted to leave the examination hall before the expiry of the time.
DO NOT OPEN THIS QUESTION BOOKLET UNTIL ASKED TO DO SO.
VLSI Design & Technology 1 [P.T.O.
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VLSI Design & Technology 2
General Physical constants, if not provided in the question :
Planks constant, h = 4.14 × 10 –15 eV-sec, 6.626 × 10 –34 joule-sec
Si Intrinsic carrier concentration, n i = 1.45 × 1010 cm–3
Electron mass, m 0 = 9.108 × 10–31 kg
Speed of light in vacuum, C = 3 × 10 8 m/sec
Relative permittivity of air = 1
Permittivity of free space, 0 = 8.85 × 10–12 farad/m
Relative permeability of air = 1.257 × 10 –6 H/m
Electronic charge, q = 1.6 × 10 –19 C
Boltzmann Constant, k = 1.380649 × 10 –23 joule K–1

1. As MOS devices are scaled to smaller dimensions, gate oxides must be reduced in thickness.
As the gate oxide thickness decreases, the MOS devices become _______________ to sodium
contamination.
(A) Not affected, not prone to sodium contamination, and balanced by other gate oxide charges
(B) Become less sensitive as oxide thickness decreases.
(C) Become highly sensitive as oxide thickness decreases.
(D) Increases the threshold of the MOS cap.

2. In a particular positive resist process exposed with e-beam, it is sometimes noticed that there is
difficulty developing away the last few hundred angstroms of resist in exposed areas. Suggest
a best possible solution of this problem, without effecting the critical dimension.
(A) Apply the low exposure dose, with low acceleration voltage.
(B) Apply the reduced resist development time, and optimize post exposure bake.
(C) Apply anti reflecting coating over the resist.
(D) Apply short pulse O2 plasma results in descum.

3. In a small MOS device, there may be a statistical variation in V T due to differences in fixed
charges from one device to another. In a 0.13 µm technology minimum device (gate oxide
area = 0.1 µm × 0.1 µm) with a 2.5 nm gate oxide, what would be the threshold voltage be for
devices with 4 fixed charge in the gate oxide, if carrier charge is 1.6 × 10 –19?
(A) 1.1 mV (B) 4.6 mV
(C) 3.2 mV (D) 1 V

VLSI Design & Technology 3 [P.T.O.

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4. Under what conditions is the thermal growth rate of SiO 2 over perfectly cleaned Si wafer is
linearly proportional to time? Where D = Diffusivity, ks = Surface oxidation reaction rate constant,
XO = Oxide depth.

(A) The oxide growth is in the linear regime for the low oxide thickness, below 200 nm, and
when kSXO/D << 1.

(B) The oxide growth is in the linear regime for large values of the oxide thickness, above
500 nm, and when kSXO/D << 1.

(C) The oxide growth is in the linear regime for the low oxide thickness, below 200 nm, and
when ksXO/D >> 1.

(D) The oxide growth is in the linear regime for large values of the oxide thickness, above
500 nm, and when kSXO/D >> 1.

5. A process engineer on the day shift started a boron isolation diffusion for a structure in
which the boron diffusion needs to penetrate completely through a 1 µm thick N-type epitaxial
layer that is lightly doped with phosphorus (N D = 1 × 1015 cm–3) on a P type substrate
(NA = 1 × 1014 cm–3). The purpose of the diffusion is to provide isolation between different
N-type regions. The day shift engineer left no information on what he or she did, what should
he do best for a quick estimation of the job done without much damaging the sample.

(A) Check the resistivity by hot probe method.

(B) Take the IV measurement by two probes and deduce the resistivity by slope.

(C) Fabricate a hall bar pattern and test the resistivity by Hall method.

(D) Check the resistivity by van der pauw method.

6. Suggest a best way to decrease the asymmetry deposition over the wafer in sputter deposition.

(A) The target size can be narrowed

(B) Decrease the spacing between target and wafer.

(C) Increase the pressure during sputter deposition.

(D) Increase the temperature during sputter deposition.

VLSI Design & Technology 4

7. A resistor for an analog integrated circuit is made using a layer of deposited polysilicon 0.5 m
thick, as shown below. The doping the polysilicon is 1 × 10 16 cm–3. The carrier mobility
µ = 100 cm2 V–1 sec–1 is low because of scattering at grain boundaries. If the resistor has
L = 100 µm, W = 10 µm, what is its resistance in Ohms?

(A) 1.25 M (B) 0.5 M

(C) 1.5 M (D) 0.1 M

8. An NMOS transistor is being built and an ion implantation is done after the gate oxide is grown
and before the gate polysilicon deposition, in order to adjust the threshold voltage by +1 volt.
Calculate the dose/cm2 of the dopant if the oxide thickness is 10 nm.
(A) 4.51 × 1016 (B) 2.16 × 1012
(C) 3.50 × 1018 (D) 4.51 × 1014

9. Consider a piece of pure silicon 100 m long with a cross-sectional area of 1 m2, having overall
mobilities of 1000 cm 2 v–1sec–1. How much current would flow through this “resistor” at room
temperature in response to an applied voltage of 2 volt?
(A) 1.21 pA (B) 2.42 pA
(C) 4.64 pA (D) 5.21 pA

10. A state-of-the-art NMOS transistor might have a drain junction area of 0.5 × 0.5 m. Calculate
the intrinsic fermi potential associated with this junction. The applied reverse bias of 2 volts exists
at the junction. Assume the drain region is very heavily doped 1 × 10 20 cm–3 and the substrate
doping is 1 × 1016 cm–3.
(A) 934 mV (B) 620 mV
(C) 500 mV (D) 320 mV

VLSI Design & Technology 5 [P.T.O.

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11. When the gate-to-source voltage (V GS) of a MOSFET with threshold voltage of 400 mV,
working in saturation is 900 mV, the drain current is observed to be 1.5 mA. Neglecting the
channel width modulation effect and assuming that the MOSFET is operating at saturation, the
drain current for an applied V GS of 1400 mV is

(A) 0.5 mA (B) 6.0 mA

(C) 4.0 mA (D) 3.5 mA

12. The electron concentration in a sample of doped n-type silicon at 300 K varies linearly from
1017/cm3 at x = 0 to 6 × 1016/cm3 at x = 2 µm. Assume a situation that electrons are supplied
to keep this concentration gradient constant with time. If electronic charge is 1.6 × 10 –19 C and
the diffusion constant D n = 35 cm2/s, the current density in the silicon, if no electric field is
present is

(A) +112 A/cm2 (B) –112 A/cm2

(C) +1120 A/cm2 (D) –1120 A/cm2

13 At 300 K, for a diode current of 1 mA, a certain germanium diode requires a forward bias of
0.1435 V, whereas a certain silicon diode requires a forward bias of 0.718 V. Under the
conditions state above, the closest approximation of the ratio of reverse saturation current in
germanium diode to that in the silicon diode is

(A) 1 × 102 (B) 4 × 103

(C) 5 × 103 (D) 8 × 103

14. For a BJT the common base current gain 0.98 and the collector base junction reverse bias
saturation current I co = 0.6 mA. This BJT is connected in the common emitter mode and operated
in the active region with a base drive current I B = 20 µA. The collector current I c for this mode
of operation is

(A) 0.98 mA (B) 0.99 mA

(C) 1.0 mA (D) 1.01 mA

VLSI Design & Technology 6

15. For the n-channel MOS transistor shown in the figure below, the threshold voltage V Th is
0.8 V. Neglect channel length modulation effects. When the drain voltage V D = 1.6 V, the drain
current ID was found to be 0.5 mA. If V D is adjusted to be 2 V by changing the values of
R and VDD, the new value of ID is

(A) 0.625 mA (B) 0.75 mA

(C) 1.5 mA (D) 1.125 mA

16. For the MOSFETs shown in the figure, the threshold voltage V t = 2 V and

1 W
K  C ox  0.1 mA/V 2 .
2 L

The value of ID (in mA) is ____.

(A) 0.9 mA (B) 1 mA

(C) 1.1 mA (D) 2.9 mA

VLSI Design & Technology 7 [P.T.O.

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17. Calculate the overdrive voltage for NMOS transistor with I D = 1 µA, IVT = 0.1 µA,
and VDS >> VT. Device parameters are W = 10 µm, L = 1 µm, n = 1.5, K’ = 200 µA/V 2
and tox =100 Å. Assume the temperature is 27°C.
(A) 8 mV (B) 16 mV
(C) 64 mV (D) 32 mV

18. The outputs of two systems S1 and S2 for same input x[n] = e in are 1 and (–1)n, respectively.
Which of the following statements are correct.
(A) Both S1 and S2 are linear time invariant systems.
(B) S1 is linear time invariant but S2 is not linear time-invariant.
(C) S1 is not linear time invariant but S2 is linear time invariant
(D) Neither S1 nor S2 is linear time-invariant.

19. A system is defined by its impulse response h(n) = 2 n u[n–2]. The system is :
(A) Stable and causal (B) Causal but not stable
(C) Stable but not causal (D) Unstable and noncausal

20. A Si pn Junction diode under reverse bias has depletion width of 10 µm. The relative permittivity
of Si (r) = 11.7 and permittivity of free space (0) is 8.85 × 10–12 F/m. The depletion capacitance
of the diode per square meter is :
(A) 100 µF (B) 10 µF
(C) 1 µF (D) 20 µF

21. If the emitter resistance in a common emitter voltage amplifier is not bypassed, it will
(A) Reduced both the voltage gain and the input impedance
(B) Reduce the voltage gain and increase the input impedance
(C) Increase the voltage gain and reduce the input impedance.
(D) Increase both the voltage gain and the input impedance.

VLSI Design & Technology 8

22. To obtain very high input and output impedance in a feedback amplifier, the topology mostly
used is :
(A) Voltage series (B) Current series
(C) Voltage shunt (D) Current shunt

23. The slope of the ID vs VGS curve of an n-channel MOSFET in linear regime is 10 –3 –1 at
VGS = 0.1 V. For the same device, neglecting the channel length modulation, the slope of the

I D vs VGS curve (in A / V) under saturation regime is approximately.

(A) 0.05 (B) 0.06

(C) 0.07 (D) 0.08

24. Consider a chip design using 10 mask levels. Suppose that each mask can be made with 98%
yield. Determine the worst-case composite mask yield for the set of 10 masks.
(A) 98% (B) 49%
(C) 48.8% (D) 81.7%

25. Calculate the W/L of MOSFET in the resistive load inverter configuration with load resistance,
R = 1 k such that VOL = 0.6 V. When an enhancement-type nMOS driver with following
parameters V DD = 5.0 V, k' = 22.0 µA/V2, VT = 1.0 V. Condition: the driver transistor operates
in the linear region, i.e. V OUT = VOL, VIN = VDD = 5.0 V.
(a) 45.05 (b) 30.03
(c) 22.5 (d) 90.1

26. What of the following causing the charge sharing problem in domino CMOS VLSI circuits.
(A) Charge sharing between output capacitance and an intermediate node capacitance.
(B) Charge sharing between input capacitance and output load capacitance.
(C) Charge sharing between input capacitance and an intermediate node capacitance
(D) Charge sharing with pMOS pull up transistor to force the node remain low.

VLSI Design & Technology 9 [P.T.O.

27. The nMOS and pMOS transistors in a CMOS inverter have the following parameters :
Vto = 1.0 V for both nMOS and pMOS transistors,  = 0.0 V –1. The CMOS inverter is designed
with (W/L)p = 20 and (W/L)n = 10, and its capacitive load is 2 pF. Calculate the average power
dissipation in the inverter when its input signal is a rectangular pulse with 100 ns period which
swings 5 V and 0 V. It is assumed that load capacitance and parasitic capacitances connected
to the drain node.

(A) 0.25 mW (B) 1 mW

(C) 2 mW (D) 0.5 mW

28. A BJT transistor has F = 0.99 and R = 0.2. Calculate the collector junction reverse saturation
current. when its emitter junction reverse saturation current is 10 –14 A.

(A) 4.95 × 10–14 A (B) 2.48 × 10–14 A

(C) 1.24 × 10–14 A (D) 0.20 × 10–14 A

29. The bonding pad in I/O circuit are implemented in the topmost metal layer with a dimension of
75 µm × 75 µm. If the separation of the topmost metal layer with SiO 2 from the common
substrate layer (ground plane) is 1 µm. Calculate the capacitance (parasitic) of the bonding pad?

(A) 0.38 pF (B) 0.76 pF

(C) 0.19 pF (D) 0.152 pF

30. Following entity represents a ______________ circuit.

ENTITY my_circuit is

PORT (a, b : IN STD_LOGIC_VECTOR (3downto 0);

x : OUT STD_LOGIC_VECTOR (3downto 0);

y : OUT STD_LOGIC;

END my_circuit;

(A) Serial Adder (B) Half Adder

(C) Parallel adder (D) Full Adder

VLSI Design & Technology 10

31. What is the correct method to declare a SIGNED type signal ‘x’?

(A) SIGNAL x : IN SIGNED_VECTOR (7 DOWN TO 0)

(B) SIGNAL x : IN SIGNED

(C) SIGNAL x : OUT SIGNED

d) SIGNAL x : IN SIGNED (7 DOWN TO 0)

32. Which of the following is not defined by the entity?

(A) Direction of the signal (B) Different ports

(C) Behavior of the signal (D) Name of the signal

33 What will be the value of the following variables after MOD operations?

X = 5 MOD 3;

Y = –5 MOD 3;

Z = 5 MOD –3;

(A) X = 2, Y = –1 and Z = 2 (B) X = 2, Y = –2 and Z = –2

(C) X = 2, Y = 1 and Z = –2 (D) X = 2, Y = –2 and Z = 1

34. In most synthesis tools, only generic of types ___________ are supported

(A) INTEGER (B) REAL

(C) STD_LOGIC (D) BIT_VECTOR

35. Which of the following is true about guarded blocks?

(A) Guarded blocks can have both guarded as well as unguarded statements

(B) Guarded blocks can have only guarded statements

(C) Guarded blocks are executed when guarded expression is false

(D) Guarded expression can have BIT type

VLSI Design & Technology 11 [P.T.O.

36. Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of
target signals periodically irrespective of any events?
(A) Event-driven Simulator (B) Cycle-based Simulator
(C) Both (A) and (B) (D) None of the above

37. In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and other
interconnection discontinuities?
(A) Power/Ground Noise (B) Crosstalk Noise
(C) Reflection Noise (D) All of the above

38. If A = 1’b1, B = 2’b01, C = 2’b10 then Y = {A, B[1], C[0]} will result in
(A) 5’b10110 (B) 3’b111
(C) 3’b100 (D) 3’b000

39. Which level of routing resources are supposed to be the dedicated lines allowing output of each
tile to connect directly to every input of eight surrounding tiles?
(A) Ultra-fast local resources (B) Efficient long-line resources
(C) High speed, very long-line resources (D) High performance global networks

40. In high noise margin (NMH), the difference in magnitude between the maximum HIGH output
voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.
(A) Driven (B) Receiving
(C) Transmission (D) All of the above

41. Maze routing is also known as ________

(A) Viterbi’s algorithm (B) Lee/Moore algorithm
(C) Prim’s algorithm (D) Quine-McCluskey algorithm

VLSI Design & Technology 12

42. The lattice constant of Ge at room temperature is a = 5.65 × 10 –8 cm. Determine the number
of Ge atoms/cm 3.
(A) 2.22 × 10 22 atoms/cm3 (B) 8.88 × 10 22 atoms/cm3
(C) 6.66 × 10 22 atoms/cm3 (D) 4.44 × 10 22 atoms/cm3

43. A planer P++-n Si step junction diode with an n-side doping of ND = 10 15/cm3, breakdown
voltage of 320 V and T = 300 K, determine the depletion width at the breakdown voltage.
(A) 20.4 µm (B) 10.2 µm
(C) 40.8 µm (D) 5.021 µm

44. A semiconductor fabrication facility manufactures 1000 wafers weekly. It's estimated that each
wafer holds 100 chips, each potentially yielding $50 in revenue if functional. Presently, the chip
yield stands at 50%. Enhancing the yield would substantially boost profits, as all 100 chips are
produced regardless of functionality. What increase in yield is required to generate a yearly profit
surge of $10,000,000?
(A) 5.5% (B) 15.4%
(C) 2.25% (D) 7.7%

45. Assume there are no clear choices for lithography systems beyond optical projection tools based
on 193-nm ArF excimer lasers. One possibility is an optical projection system using a 157-nm
F2 excimer laser. a. Assuming a numerical aperture of 0.8 and k1 = 0.75, what is the expected
resolution of such a system using a first order estimate of resolution?
(A) 147 nm (B) 165 nm
(C) 294 nm (D) 73.5 nm

46. The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate
the direction of rotating.?
(A) Two D flip flop and one Sensors (B) Two sensors and D flip flop
(C) One Sensor only (D) One sensor and D flip flop

VLSI Design & Technology 13 [P.T.O.

47. Which of the following is not a way to reduce clock skew to zero?
(A) Use pure H tree
(B) clock layout strategies
(C) process variations in R and C across the chip
(D) buffering, and clock gating

48. If x = 6’b101110, then x << 2 will result in

(A) 6’b101011 (B) 6’b101100
(C) 6’b001010 (D) None of the above

49. What is the SWAMI in VLSI, and what it signifies?

(A) SWAMI stands for Silicon Wafer Advanced Manufacturing Integration, optimizing chip
fabrication processes.
(B) SWAMI refers to Silicon Wafer Analysis for Microchip Integration, aiding in chip processing
design.
(C) SWAMI represents Silicon Wafer Analysis Management Interface, enhancing integration
efficiency.
(D) SWAMI denotes Side Wall Masked Isolation, utilized for reducing bird’s beak effect.

50. In a CMOS inverter circuit configuration (PMOS and NMOS transistors connected in series with
common input Vin) with Vin = 2.5 V, V DD = 5 V. If the transconductance parameters of the
A
NMOS and PMOS are kn  k p  20 , VTn = VTp = 1 V the Current I flowing through the
V2
PMOS to NMOS is
(A) 0 µA (B) 45 µA
(C) 25 µA (D) 90 µA

VLSI Design & Technology 14

 ROUGH WORK

VLSI Design & Technology 15 [P.T.O.

 ROUGH WORK

VLSI Design & Technology 16