LOGICAL INSTRUCTION

instructions, which are used to perform operations such as AND, OR,

Compare, Rotate etc.

Opcode Operand Description

R Compare register or memory with

CMP
M accumulator

8-bit
CPI Compare immediate with accumulator
data

R Logical AND register or memory with

ANA
M accumulator

8-bit
ANI Logical AND immediate with accumulator
data

R Logical OR register or memory with

ORA
M accumulator

8-bit
ORI Logical OR immediate with accumulator
data

R Logical XOR register or memory with

XRA
M accumulator

8-bit
XRI XOR immediate with accumulator
data

RLC None Rotate accumulator left

RRC None Rotate accumulator right

RAL None Rotate accumulator left through carry

 RAR None Rotate accumulator right through carry

CMA None Complement accumulator

CMC None Complement carry

STC None Set carry

Top

1) CMP instruction:

The contents of the given register or addressed memory location are

compared with the accumulator contents. In fact the contents of the register
or addressed memory location are subtracted from the contents of
accumulator and the accumulator contents remain unchanged. However, as
a result of the subtraction the flags are modified as per the result. The
possible combinations of this instruction are as given below:
CMP reg (Compare Register)
CMP M (Compare Memory)
The result of the comparison is shown by setting the flags as follows:

if (A) < (reg/mem): carry flag(CY = 1) is set

if (A) = (reg/mem): zero flag(Z = 1) is set

if (A) > (reg/mem): carry(CY = 0) and zero(Z = 0) flags are reset.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All 1 4

Memory 1 All 2 7

2) CPI instruction:

It is similar to CMP instruction with the difference that the 8-bit data is
directly given with the instruction. In this instruction the given data is
compared with the accumulator contents. The flags will be modified as per
the result.

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All 2 7

3) ANA instruction:

In this instruction each bit of the given register or memory location

addressed by H-L register pair contents are ANDed with each bit of the
accumulator contents (bit by bit). The result is saved in the accumulator. It
does not affect the contents of the given register.

The ANA reg/M instruction clears (resets) the CY flag and all other flags
are modified according to the data conditions of the result. This instruction is
one byte instruction. The possible combinations of this instruction are as
given below:
ANA reg (AND Register)
ANA M (AND Memory)
For example A = 73 H, C = C3 H, CY = 1,

ANA C

after the execution of the instruction ANA C we get the CY = 0,A = 43 H.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All,CY=0,AC=1 1 4

Memory 1 All,CY=0,AC=1 2 7

4) ANI instruction:

In this instruction each bit of the given 8-bit data is immediately ANDed
with each bit of the accumulator contents (bit by bit). The result is stored in
the accumulator. The difference between ANA reg and ANI data instruction is
that in ANA reg the data given in the register where as in the ANI data
instruction, the data is given with the instruction itself.

For example, if A = AB H and CY = 1,

ANI 06H

after the execution of the instruction ANI 06 H we get the CY = 0,A = 02

H.

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All,CY=0,AC=1 2 7

5) ORA instruction:

In this instruction each bit of the given register or memory location

addressed by H-L register pair contents are ORed with each bit of the
accumulator contents (bit by bit). The result is saved in the accumulator. It
does not affect the contents of the given register.

The ORA reg/M instruction clears (resets) the CY flag and all other flags
are modified according to the data conditions of the result. This instruction is
one byte instruction. The possible combinations of this instruction are as
given below:
ORA reg (OR Register)
ORA M (OR Memory)
For example A = 73 H, C = C3 H, CY = 1,

ORA C

after the execution of the instruction ORA C we get the CY = 0,A = F3 H.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All,CY=0,AC=0 1 4
 Memory 1 All,CY=0,AC=0 2 7

6) ORI instruction:

In this instruction each bit of the given 8-bit data is immediately ORed
with each bit of the accumulator contents (bit by bit). The result is stored in
the accumulator. The carry flag will be reset after the execution of this
instruction and other flags will be affected as per the result.

For example A = AB H, CY = 1,

ORI 16H

after the execution of the instruction ORI 16H we get the CY = 0,A = BF
H.

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All,CY=0,AC=0 2 7

7) XRA instruction:

In this instruction each bit of the given register or memory location

addressed by H-L register pair contents are XORed with each bit of the
accumulator contents (bit by bit). The result is saved in the accumulator. It
does not affect the contents of the given register.

The XRA reg/M instruction clears (resets) the CY flag and all other flags
are modified according to the data conditions of the result. This instruction is
one byte instruction. The possible combinations of this instruction are as
given below:
XRA reg (Exclusive OR Register)
XRA M (Exclusive OR Memory)
For example A = 19 H, H = 22 H, L = 00 H, M2200 = 37 H and CY = 1,

XRA M
 after the execution of the instruction XRA M we get the CY = 0,A = 2E
H.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All,CY=0,AC=0 1 4

Memory 1 All,CY=0,AC=0 2 7

8) XRI instruction:

In this instruction each bit of the given 8-bit data is immediately XORed
with each bit of the accumulator contents (bit by bit). The result is stored in
the accumulator. The carry flag will be reset after the execution of this
instruction and other flags will be affected as per the result.

For example A = AB H, CY = 1,

XRI 12H

after the execution of the instruction XRI 12H we get the CY = 0,A = B9
H.

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All,CY=0,AC=0 2 7

9) RLC instruction:

This is mnemonic for Rotate Accumulator Left.In this instruction, the

bits of the accumulator contents are shifted or rotated left. The LSB of the
accumulator is changed as MSB (before the execution). The CY flag is modified
as MSB (before the execution).

[An+1] < - [An] , [A0] < - [A7] also [CY] < - [A7]

Operand Bytes Flags Affected M-Cycles T-States

 None 1 Only CY 1 4

For example A = AE H, CY = 0,

RLC

after the execution of the instruction RLC we get the A = 5D H, CY = 1.

MSB is saved in CY flag and also in the LSB of the accumulator. The other bits
are shifted left as shown in figure

10) RRC instruction:

This is mnemonic for Rotate Accumulator Right.In this instruction, all

the bits of accumulator are shifted or rotated right. The MSB of the
accumulator is changed as LSB (before the execution). The CY flag is modified
as LSB (before the execution).

Operand Bytes Flags Affected M-Cycles T-States

None 1 Only CY 1 4
For example A = 93 H, CY = 0,

RRC

after the execution of the instruction RRC we get the A = C9 H, CY = 1.

LSB is saved in CY flag and also in the MSB of the accumulator. The other bits
are shifted left as shown in figure

11) RAL instruction:

This is mnemonic for Rotate Accumulator Left Through Carry.In this

instruction, the bits of the accumulator contents will be shifted / rotated left
through carry. The content of carry flag CY will be stored in LSB of the
accumulator and MSB of the accumulator will be stored in CY flag. All other
bits of the accumulator will be shifted to the left.

Operand Bytes Flags Affected M-Cycles T-States

None 1 Only CY 1 4

For example A = 6A H, CY = 1,
 RAL

after the execution of the instruction RAL we get the A = D5 H, CY = 0.

the accumulator contents will be shifted as shown in figure

12) RAR instruction:

This is mnemonic for Rotate Accumulator Right Through Carry.In this

rotate instruction, all the bits of the accumulator contents will be shifted /
rotated right through carry. The content of carry flag CY will be stored in MSB
of the accumulator and LSB of the accumulator will be stored in CY flag; and
all other bits of the accumulator will be shifted to the right.

Operand Bytes Flags Affected M-Cycles T-States

None 1 Only CY 1 4

For example A = 76 H, CY = 1,

RAR
 after the execution of the instruction RAR we get the A = BB H, CY = 0.

the accumulator contents will be shifted as shown in figure

13) CMA instruction:

This is mnemonic for Complement Accumulator.This is one byte

implied addressing instruction as no operand is required with the instruction.
The execution of this instruction inverts each bit of the accumulator contents
and the result is saved in the accumulator. Basically it produces 1’s
complement of the accumulator contents. No flag is affected with this
instruction.

[A] < - [A∁]

For example, if A = 0B H,

CMA

after the execution of the instruction CMA we get the A = F4 H.

 Operand Bytes Flags Affected M-Cycles T-States

None 1 None 1 4

14) CMC instruction:

This is mnemonic for Complement the carry.This instruction

complements the carry flag.

If CY = 1 before the execution of CMC instruction, the carry flag will be

reset (CY = 0) after the execution of this instruction. Similarly, If CY = 0 before
the execution of CMC instruction, the carry flag will be set (CY = 1) after the
execution of this instruction.In this only carry flag will be affected and all other
flags will not be affected.

[CY] < - [CY∁]

Operand Bytes Flags Affected M-Cycles T-States

None 1 Only CY 1 4

15) STC instruction:

This is mnemonic for Set the carry.It sets the carry flag.

The carry flag will be set (CY = 1) irrespective of the carry flag is set or
reset before the execution of this instruction STC.Only carry flag gets affected
with this instruction.

[CY] < - [1].

BRANCHING INSTRUCTIONS
 instructions, which are used to for conditional and unconditional jump,
subroutine call and return and restart. The branching instruction alter the
normal sequential flow.

❖ Unconditional Jump Instructions :

Opcode Operand Description

JMP 16-bit address Jump unconditionally

1) JMP instruction:

The format for this instruction is JMP address or JMP LABEL.

This is an unconditional jump instruction. With the execution of this

instruction, the program jump to the address (or label) specified with the
instruction. This is a three byte instruction and no flag is affected. In fact
during the execution of JMP address (label) instruction, the address of the
label is copied in the program counter; and whenever the program fetches
the next instruction the program counter will send the address of this given
label.

[PC] < - [LABEL]

Operand Bytes Flags Affected M-Cycles T-States

16-bit address 3 None 3 10

❖ Conditional Jump Instructions :

Opcode Description Status Flags

JNZ Jump if No Zero Z=0

JZ Jump if Zero Z=1

 JC Jump if Carry CY = 1

JNC Jump if No Carry CY = 0

JP Jump if Positive S=0

JM Jump if Minus S=1

JPE Jump if Parity Even P=1

JPO Jump if Parity Odd P=0

The format for These instruction are INSTRUCTION address or INSTRUCTION

LABEL. like,
JNZ LABEL.

Condition Bytes Flags Affected M-Cycles T-States

True 3 None 3 10

Not True 3 None 2 7

1) JNZ instruction:

This is mnemonic for Jump if the result is not zero.When this

instruction is executed, the program jumps to the instruction specified by the
address (or label), if the result is not zero; otherwise it will proceed to the next
instruction. Here the result of the preceding instruction is considered.

In this case the address (or label) is copied in the program counter if
zero flag is reset (Z = 0).

[PC] < - LABEL if Z = 0.

For example,
Label Mnemonics Operand
----
----
 DCR C
JNZ NEXT
MOV A,M
NEXT STA 2500H
HLT

For the execution of JNZ instruction, the result of C-register will be

considered. If [C] ≠ 0 (Z = 0), it will jump to the instruction (STA 2500 H)
specified by the label NEXT, otherwise it will jump to the next instruction
(MOV A, M).

2) JZ instruction:

This is mnemonic for Jump if the result is zero.The condition of this

instruction is reverse to that of JNZ address. In this case the program will jump
to the instruction specified by the address (or label), if the result of the
preceding instruction is zero (Z = 1) otherwise it will proceed to the next
instruction in the normal sequence.

The address of the label will be copied in the program counter if Z flag
is set (or result is zero).

[PC] < - LABEL if Z = 1.

3) JC instruction:

This is mnemonic for Jump if carry.The program will jump to the

instruction specified by the address (label) if the CY flag is set (CY = 1) which
is modified by the preceding instruction. However, if the carry is reset (CY =
0), it will proceed to the next instruction of the normal sequence. The
condition of this instruction is opposite to that of the JNC address.

In this case the address of the label will be copied in the program
counter if CY = 1 or CY is set.

[PC] < - LABEL if CY = 1.

4) JNC instruction:
 This is mnemonic for Jump if no carry.During the execution of this
instruction, it will check up the Carry flag modified by the preceding
instruction. If there is no carry (CY = 0 or CY flag is reset), the program will
jump to the instruction specified by the address (or label) otherwise it will
proceed to the next instruction of the normal sequence.

In this case the address of the label will be copied in the program
counter if CY = 0 or CY is reset.

[PC] < - LABEL if CY = 0.

5) JP instruction:

This is mnemonic for Jump if Positive.If the result of the preceding

instruction is positive or sign flag is reset (S = 0), the program will jump to the
instruction specified by the address (label). However, if the condition is not
satisfied it will proceed to the next instruction of the normal sequence.

[PC] < - LABEL if S = 0.

6) JM instruction:

This is mnemonic for Jump if Minus.When this instruction is executed,

the program will jump to the instruction specified by the address (label) if the
result of the preceding instruction is minus or sign flag is set (S = 1) otherwise
it will proceed to the next instruction of the normal sequence.

[PC] < - LABEL if S = 1.

7) JPE instruction:

This is mnemonic for Jump if Parity is Even.If the parity is even or parity
flag is set (P = 1) as a result of the preceding instruction, the program will jump
to the instruction specified by the address (label) otherwise next instruction
of the normal sequence will be executed.

[PC] < - LABEL if P = 1.

8) JPO instruction:

This is mnemonic for Jump if Parity is Odd.If the parity is odd or parity
flag is reset (P = 0) as a result of the preceding instruction, the program will
jump to the instruction specified by the address (label) otherwise next
instruction of the normal sequence will be executed.

[PC] < - LABEL if P = 0.

ARITHMETIC INSTRUCTION

instructions, which are used to perform arithmetic operations such as

addition, subtraction, increment or decrement of the content of a register or
memory. the result is stored in the accumulator.

Opcode Operand Description

R
ADD Add register or memory to accumulator
M

R Add register or memory to accumulator

ADC
M with carry

ADI 8-bit data Add immediate to accumulator

ACI 8-bit data Add immediate to accumulator with carry

Register
DAD Add register pair to H-L pair
pair

R Subtract register or memory from

SUB
M accumulator

R Subtract register or memory from

SBB
M accumulator with borrow
 SUI 8-bit data Subtract immediate from accumulator

Subtract immediate from accumulator

SBI 8-bit data
with borrow

R
INR Increment register or memory by 1
M

Register
INX Increment register pair by 1
pair

R
DCR Decrement register or memory by 1
M

Register
DCX Decrement register pair by 1
pair

DAA None Decimal adjust accumulator

1) ADD instruction:

(i) ADD reg

where reg = A, B, C, D, E, H or L

It adds the content stored in given register with the accumulator. The
result of this addition is stored in accumulator.All the flags are affected with
this instruction. For example A = 10101111(AF H), E = 10110101(B5 H), CY = 0
, S = 1, Z = 0 and P = 1,

ADD E

after execution of ADD E instruction A = 01100100(64 H), CY = 1 , S = 0,

Z = 0, P = 0.

(ii) ADD M
 It adds the content of memory location whose address is given in H-L
register pair with the accumulator and the answer is stored in accumulator.
For example A = 40 H H = 21 H L = 00 H, M2100 = 3A H

ADD M

after execution of the instruction ADD M will produce the result A = 7A H.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All 1 4

Memory 1 All 2 7

2) ADC instruction:

This is mnemonic for Add with carry. It adds the content stored in given
register or memory location whose address is given in H-L register pair and
content of CY flag with the content of accumulator. The result of this addition
is stored in accumulator. All the flags are affected with this instruction

[A] < - [A] + [reg] or [MHL] + [CY ]

For example A = 50 H, CY = 1, H = 25 H, L = 00 H,M2100 = 3B H,

ADC M

after execution of the instruction ADC M will produce the result:A = 8C.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All 1 4

Memory 1 All 2 7

3) ADI instruction:
 This is mnemonic for Adds immediately the data. It immediately adds
the given 8-bit data with the accumulator and the answer will be stored in
Accumulator.This is a two-byte instruction. All flags will be affected with this
instruction.

[A] < - [A] + data

For example A = 50 H, after execution of ADI 3AH will produce the result:A =
8A H.

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All 2 7

4) ACI instruction:

This is mnemonic for Adds immediately the data with Carry. It

immediately adds the given 8-bit data to the accumulator with carry and the
answer will be stored in Accumulator. This is a two-byte instruction. All flags
will be affected with this instruction.

[A] < - [A]+ data +CY

For example A = 50 H,CY = 1 after execution of ACI 3AH will produce the
result:A = 8B H. if CY = 0 then result: 8A H.

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All 2 7

5) DAD instruction:

The format for this instruction is DAD rp

where rp = BC,DE,HL
 This is mnemonic for Double Add. This instruction adds the contents of
given register pair with the contents of H-L register pair. The answer will be
stored in H-L register pair. Only carry flag will be affected in this instruction.

For example D = 2A H, E = B6 H, H = 01 H, L = 27 H,

DAD D

After the execution of this instruction we H = 2B H, L = DD H.

[HL] < - [HL]+ [rp]

Operand Bytes Flags Affected M-Cycles T-States

Register pair 1 Only CY 3 10

6) SUB instruction:

(i) SUB reg

where reg = A, B, C, D, E, H or L

It subtracts the contents stored in given register from the accumulator.

The result of this subtraction is stored in accumulator. All flags will be affected
as per the accumulator contents. The Carry flag is set, when the unsigned
value subtracted is greater than the unsigned value it is subtracted from.

For example A = 10101111(AF H), D = 10110101(B5 H), CY = 0 , S = 1, Z = 0 and

P = 1,

SUB D

after the execution of the instruction SUB D we get the following

result:CY = 1,A = 11111010

(ii) SUB M
 This instruction is one byte instruction and subtracts the contents of
memory location whose address is given in H-L register pair from the
accumulator and the answer is stored in accumulator.

For example A = 56 H, H = 22 H, L = 01 H and M2201 = 2C H,

SUB M

after execution of the instruction SUB M will produce the result:A = 2A

H.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All 1 4

Memory 1 All 2 7

7) SBB instruction:

This instruction subtracts the contents stored in given register or

memory location addressed by H-L register pair with borrow bit (carry flag)
from accumulator. The answer will be stored in accumulator.All the flags are
affected in the operation of this instruction.The Carry flag is set, when the
unsigned value subtracted is greater than the unsigned value it is subtracted
from. The possible combinations of this instruction are as given below:

SBB reg (Subtract with Borrow)

SBB M (Subtract memory with Borrow)

[A] < - [A] - [reg / MHL] - [CY]

For example A = 10101111, H = 10110101, CY = 0 , S = 1, Z = 0 and P = 1,

SBB H

after the execution of the instruction SBB H we get the following

result:A = 11111001, CY = 1.
 Operand Bytes Flags Affected M-Cycles T-States

Register 1 All 1 4

Memory 1 All 2 7

8) SUI instruction:

It immediately subtracts the given 8-bit data with the accumulator

contents and the answer will be stored in Accumulator.The 8-bit data is
subtracted from the contents of the accumulator. The Carry flag is set, when
the unsigned value subtracted is greater than the unsigned value it is
subtracted from.

For example A = 50 H,

SUI 45H

after the execution of the instruction SUI 45H we get the A = 05H.

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All 2 7

9) SBI instruction:

SBI data instruction subtracts the given 8-bit data with borrow bit (carry
flag) from the accumulator contents and it stores the answer in
accumulator.The Carry flag is set, when the unsigned value subtracted is
greater than the unsigned value it is subtracted from.

For example A = 50H,

SBI 45H

after the execution of the instruction SBI 45H if CY = 0 then we get the
A = 05H.if CY = 1 then A = 04H.
 [A] < - [A] - [8-bit data] - [CY]

Operand Bytes Flags Affected M-Cycles T-States

8-bit data 2 All 2 7

10) INR instruction:

It increments the contents of memory location addressed by H-L

register pair or contents of given register by 1 and stores the answer in the
addressed memory location or given register.all flags except carry flag will be
affected after the execution of this instruction. The possible combinations of
this instruction are as given below:

INR reg (Increment Register)

INR M (Increment Memory)

For example H = 22 H,

INR H

after the execution of the instruction INR H we get the H = 23 H.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All,except CY 1 4

Memory 1 All,except CY 3 10

11) INX instruction:

INX rp instruction increments the contents given in register pair by one

and the result is stored in the given register pair.No flag is affected with the
execution of this instruction.

[rp] < - [rp] + 1

 where rp = BC,DE,HL

For example H = 21 H, L = 02 H,

INX H

after the execution of the instruction INX H we get the H = 21 H, L =

03H.

Operand Bytes Flags Affected M-Cycles T-States

Register pair 1 None 1 6

12) DCR instruction:

It decrements the contents of memory location addressed by H-L

register pair or contents of given register by 1 and stores the answer in the
addressed memory location or given register.all flags except carry flag will be
affected after the execution of this instruction. The possible combinations of
this instruction are as given below:

DCR reg (Decrement Register)

DCR M (Decrement Memory)

For example H = 22 H,

DCR H

after the execution of the instruction DCR H we get the H = 21 H.

Operand Bytes Flags Affected M-Cycles T-States

Register 1 All,except CY 1 4

Memory 1 All,except CY 3 10

DCX instruction:
 DCX rp instruction decrements the contents given in register pair by
one and the result is stored in the given register pair.No flag is affected with
the execution of this instruction.

[rp] < - [rp] - 1

where rp = BC,DE,HL

For example H = 21 H, L = 02 H,
DCX H
after the execution of the instruction DCX H we get the H = 21 H, L =
01H.

Operand Bytes Flags Affected M-Cycles T-States

Register pair 1 None 1 6

A = 38 H, 0 0 1 1 1 0 0 0
Adds 87 H, 1 0 0 0 0 1 1 1
----------------------------------
1 0 1 1 1 1 1 1 Lower 4-bits
0 0 0 0 0 1 1 0 is > 9

----- DATA TRANSFER INSTRUCTION

instructions, which are used to transfer data from one register to

another register, from memory to register or register to memory are Data
Transfer Instruction. when data transfer instructions is executed, data is
transferred from the source to the destination without altering the contents
of the source.

Opcode Operand Description

 Rd,Rs
MOV M,Rs Copy from source to destination
Rd,M

Rd,Data
MVI Move immediate 8-bit
M,Data

LDA 16-bit address Load Accumulator

LDAX B/D Register Pair Load accumulator indirect

Register pair, 16-

LXI Load register pair immediate
bit data

LHLD 16-bit address Load H-L registers direct

STA 16-bit address Store accumulator direct

STAX Register pair Store accumulator indirect

SHLD 16-bit address Store H-L registers direct

XCHG None Exchange H-L with D-E

Copy H-L pair to the Stack Pointer

SPHL None
(SP)

XTHL None Exchange H–L with top of stack

Load program counter with H-L

PCHL None
contents

PUSH Register pair Push register pair onto stack

POP Register pair Pop stack to register pair

8-bit port Copy data from accumulator to a

OUT
address port with 8- bit address
 8-bit port Copy data to accumulator from a
IN
address port with 8- bit address
Top

1) MOV instruction:

This instruction copies the contents of the source register into the
destination register. The contents of the source register are not altered.If one
of the operands is a memory location, its location is specified by the contents
of the HL registers.These instructions are of one byte instruction and no flag
is affected in these instructions.

(i) MOV reg1, reg2 (Moves to register from register)

where reg = A, B, C, D, E, H or L

This instruction is moves / copies the data in the given register to the given
register.
i.e

[reg1] < - [reg2]

(ii) MOV reg, M (Moves to register from memory)

This instruction is indirect read instruction. It moves / copies the data stored
in memory location whose address is given in H-L register pair, to the given
register.
i.e

[reg] < - [MHL]

(iii) MOV M, reg (Moves to memory from register)

This instruction moves / copies the data in the given register to the memory
location addressed by H-L register pair.
i.e
 [MHL] < - [reg]

For example let D = 4E H, H = 23 H, L = 00 H Then after execution of the

instruction MOV M, D will produce the result:

[M2300] < - [4E]

Operand Bytes Flags Affected M-Cycles T-States

Rd,Rs 1 None 1 4

Rd,M 1 None 2 7

M,Rs 1 None 2 7

2) MVI instruction:

This an instruction to load register with 8-bit value. This instruction uses
immediate addressing for specifying the data.If the operand is a memory
location, its location is specified by the contents of the H-L registers.These
instructions are two byte instructions and no flag is affected.

(i) MVI reg, 8 bit data (Moves 8 bit data to register)

This instruction transfers the given data to the register.

i.e

[reg] < - [8 bit data]

(ii) MVI M, 8 bit data (Moves 8 bit data to memory)

This instruction transfers the given data to the memory location pointed by
H-L pair.
i.e

[MHL] < - [8 bit data]

For example the given data 2BH will be copied into the memory location
whose address is given in H-L register pair. If H = 21 H, L = 00 H then,

MVI M,2B

[M2100] < - [2B]

Operand Bytes Flags Affected M-Cycles T-States

Rd,data 2 None 2 7

M,data 2 None 3 10

3) LDA instruction:

This is mnemonic for Loads the accumulator direct. It transfers the

content stored in the addressed memory location (given by address) to
accumulator. No flag is affected in this instruction. It is three byte instruction.

[A] < - [Maddress]

For example if 2A H data is stored in memory location 2500H before the

execution of

LDA 2500H

instruction, then after the execution of this instruction, the data 2AH
will be transferred to accumulator.

[A] < - [2A]

Operand Bytes Flags Affected M-Cycles T-States

16-bit address 3 None 4 13

4) LDAX instruction:
 This is mnemonic for Loads the Accumulator Indirect. the contents
already stored in the memory location addressed by the register pair (rp).
Here rp represents B-C or D-E register pair.

The H-L register pair is not included in this instruction.the instruction

LDAX H does not exist, because the contents stored in the memory location
addressed by H-L register pair may be loaded to accumulator by the
instruction MOV A, M.The possible combinations of the instruction are:

LDAX B

LDAX D

For example, if [D] = 25 H, [E] = 00 H and M2500 H = 34 H, then after the

execution of the instruction LDAX D, the accumulator will have:

[A] < - [M2500] , A = 34 H

Operand Bytes Flags Affected M-Cycles T-States

B/D Register Pair 1 None 2 7

5) LXI instruction:

This is mnemonic for Load eXtended register Immediate. Here, a

register pair is termed as extended register. It is an instruction that loads
register pair 'rp' with the 16-bit data. This instruction uses immediate
addressing for specifying the data.

where rp = BC,DE,HL

i.e LXI rp,16 bit data

For example if you want to load HL with F850 H then,

LXI H,F850H
 Operand Bytes Flags Affected M-Cycles T-States

Reg. pair,16-bit data 3 None 3 10

6) LHLD instruction:

This is mnemonic for Loads the H-L pair direct.This instruction loads the
H-L pair direct with two bytes already stored in two consecutive memory
locations starting at the specified memory address. The contents stored in the
memory location whose address is given with the instruction will be loaded
to the L-register; and the contents stored in the next memory location
(address + 1) will be loaded to the H-register.

LHLD 2100 H

after the execution of the instruction LHLD 2100 H , the L-register will have
2A H and H-register will have 2B H.

Operand Bytes Flags Affected M-Cycles T-States

16-bit address 3 None 5 16

7) STA instruction:

This is mnemonic for Stores the accumulator direct.It transfers the

content stored in the accumulator to addressed memory location (given by
address).

16H data is stored in the accumulator before the execution of STA 2100H
instruction

STA 2100 H

after the execution of this instruction, the data 16H will be transferred
to the addressed memory location.

[Maddress] < - [A]

 Operand Bytes Flags Affected M-Cycles T-States

16-bit address 3 None 4 13

8) STAX instruction:

This is mnemonic for Stores the Accumulator Indirect.The STAX rp

instruction does the reverse operation of LDAX rp. This instruction stores the
accumulator contents in the memory location addressed by the register pair
(rp). Here too rp represents B-C or D-E register pair.

The combination STAX H is not included in this instruction as MOV A, M

performs the same operation.The possible combination of this instruction
are:

STAX B

STAX D

For example, if B = 21 H, C = 00 H and A = 3A H,

STAX B

after the execution of the instruction STAX B, 3A H will be stored in the

memory location 2100 H.

[Mrp] < - [A]

Operand Bytes Flags Affected M-Cycles T-States

B/D Register Pair 1 None 2 7

9) SHLD instruction:

This is mnemonic for Stores the H-L pair direct.This instruction does the
reverse operation of LHLD. The instruction SHLD address stores the contents
of L-register to memory location whose address is given with the instruction;
and the contents of H-register are stored in the next consecutive memory
location (address + 1).

For example, if [L]= 3A H and[H] = 3B H,

SHLD 2200 H

after the execution of the instruction SHLD 2200 H will result.

[M2200H] < - 3A

[M2201H] < - 3B

Operand Bytes Flags Affected M-Cycles T-States

16-bit address 3 None 5 16

10) XCHG instruction:

This is mnemonic for Exchange the contents of H-L register with D-E
register.This is one byte instruction and no operand is needed with it. It
exchanges the contents of H and L register with D and E registers respectively.

For example:If H = 25 H , L = 32 H and D = 12 H, E = 1B H,

XCHG

after the execution of XCHG instruction, we have:H = 12 H, L = 1B H and D =

25 H, E = 32 H.

[H] < - > [D] and [L] < - > [E]

Operand Bytes Flags Affected M-Cycles T-States

None 1 None 1 4

11) SPHL instruction:

 This is mnemonic for Copies HL to Stack Pointer SP.This is also one byte
instruction as no operand is used. The SPHL instruction copies the contents of
H-register to high order byte stack pointer (SP) and the contents of L-register
to low order byte of stack pointer (SP).

For example if H = 23 H and L = 45 H and SP = 2501 H,

SPHL

after the execution of the instruction SPHL will result SP = 2345 H.

[SP] < - > [HL] i.e. [SPH] < - > [H] and [SPL] < - > [L]

Operand Bytes Flags Affected M-Cycles T-States

None 1 None 1 6

12) PCHL instruction:

This is mnemonic for Copies H-L to program counter (PC).This is one

byte instruction and no operand is needed with this instruction. It copies the
contents of H-register to high-order byte of the program counter (PC) and the
contents of L-register to low order byte of the program counter.

For example if PC = 2106 H and HL = 2500 H,

PCHL

after the execution of the instruction PCHL will result: PC = 2500 H.

[PC] < - > [HL] i.e. [PCH] < - > [H] and [PCL] < - > [L]

Operand Bytes Flags Affected M-Cycles T-States

None 1 None 1 6

-----------------------------
1 1 0 0 0 1 0 1 AC = 1
0 1 1 0 0 0 0 0 Upper 4-bits
---------------------------------- is > 9
100100101
A = 38 H, 0 0 1 1 1 0 0 0
Adds 87 H, 1 0 0 0 0 1 1 1
----------------------------------
1 0 1 1 1 1 1 1 Lower 4-bits
0 0 0 0 0 1 1 0 is > 9
----------------------------------
1 1 0 0 0 1 0 1 AC = 1
0 1 1 0 0 0 0 0 Upper 4-bits
---------------------------------- is > 9
100100101