Internal Use Only

Encounter® Conformal® ECO

Kenneth Chen
 Course Agenda
 Introduction to Conformal ECO
 Conformal ECO Flows
 Configuring and Reporting Rule-Based ECO Setup Checks
 Conformal ECO basic commands (PRE/POST-Mask)
 Streamlined Setup for ECO Patch Validation
 Hier-FEF Flow -Block level Flattened ECO
 NEQ Module Analysis in RTL for Hier-FEF flow
 ECO Cut Point Flow (ECP)
 Sequential Change
 Equivalent Signal Analysis for manual ECO
 ECO Variations

© 2023 Cadence Design Systems, Inc. All rights reserved,. 2

Introduction to Conformal ECO

3 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Nomenclature
Engineering Change Order (ECO) is the process of making local changes
to the design netlist without rerunning the entire synthesis and place and
route (P&R) flow.

ECO Types
 Functional ECO
 Changes the functionality of the design

 Nonfunctional (Timing) ECO

 Fixes timing, crosstalk, DRV, and routing violations with minimal effort

ECO Stages
 Premask (pre-tapeout) ECO
 Uses normal logic gates to implement change

 Postmask (metal-only ECO)

 Uses spare gates only to implement change

© 2023 Cadence Design Systems, Inc. All rights reserved,. 4

 ECO Challenges
mArch Golden RTL GDS Mask

RTL-GDS
rRTL Metal

Goal: Rapid “what-

if” exploration for usb
design derivatives IP “Can this RTL ECO be
ARM IP comm
and logic bug fixes a
implemented using a
t
a
metal change only?”
security

encode b
u video IP
Yes = J
s

transport de-
No = $$$$
IP code

© 2023 Cadence Design Systems, Inc. All rights reserved,. 5

 Manual ECO Challenges
Where do I
make the
change?
Impact?

Genus

Innovus

Where do I
make the Will this ECO
change? meet timing, is
Impact? it DRC clean?

Innovus

© 2023 Cadence Design Systems, Inc. All rights reserved,. 6

 RTL-to-GDSII Flow

© 2023 Cadence Design Systems, Inc. All rights reserved,. 7

 Conformal ECO Solution Flow

New RTL Old RTL

(R2) (R1)

Synthesis SDC Synthesis

Back-end ECO
Test Insertion

EDIS
P&R
Pre-mask ECO
ECO placement & routing

Post-mask ECO
New Netlist Old Netlist DEF GA/SG incr. opt & eco
(G2) (G1) (G1) routing

Functional Tech Map

ECO & ECO Netlist Final Netlist
Patch
Patch
Analysis Patch Optimize (G3) (G4)
Front-end ECO
Mapping
Guidance
Conformal ECO

© 2023 Cadence Design Systems, Inc. All rights reserved,. 8

Conformal ECO Flows

9 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 CECO Flow
 Conformal ECO provides three main ECO flows :
Flattened ECO Flow (FEF )
Hierarchical ECO Flow
Hierarchical Flattened ECO Flow (Hier-FEF)

© 2023 Cadence Design Systems, Inc. All rights reserved,. 10

 Conceptual View
Old P&R Netlist (G1)

o1
o2

Conformal ECO
o3 o1

o2’

o3
O1
ECO

O2 New Netlist (G3)

 Compare the designs
O3
 Extract the ECO
 Generates minimal patch
New Synthesis Netlist (G2)
 Apply and optimize the patch
 Write out a new netlist

© 2023 Cadence Design Systems, Inc. All rights reserved,. 11

 ECO - Preparation
 Find out as much about ECO as possible.
 Utilize your RTL Designer.
 Utilize your R1-R2 LEC run

 Utilize the SAME synthesis script to generate SYN2.

 Ensure R1-G1 and R2-SYN2 (G2)is LEC clean before starting ECO.
 Ensure your SYN2-G1 Hierarchies MATCH where you are doing the
ECO.
 Avoid auto_ungroup and boundary optimization in ECO area
 Preserve hierarchy on tough blocks
 Keep as much Hierarchy in the netlist as possible.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 12

 Functional ECO Flow: Step 1
Required Data Preparation

Compare old RTL (R1) vs. old P&R netlist (G1)

 Expected EQ!
Old RTL New RTL
(R1) (R2)
Synthesize new RTL : G2
 To provide a structurally similar netlist Conformal
Synthesis
ECO EC

Compare new RTL (R2) vs. new netlist (G2)

 Expected EQ! Old Netlist New Netlist
(G1) (G2)
Compare old RTL (R1) to new RTL (R2)
 Expected non-EQ!

 Identify ECO modules & logic cones

Conformal
ECO EC
Compare old P&R netlist (G1) vs. new netlist (G2)
 Expected non-EQ!
Non-Equiv
 Identify ECO modules & logic cones, target for patch Report

generation.
Note: Result should match with R1-vs-R2 comparison
© 2023 Cadence Design Systems, Inc. All rights reserved,. 13
 Functional ECO Flow: Step 2A
Pre-mask ECO

 ECO patch creation

New Netlist Old Netlist
– Identify ECO logics among G1 & G2 (G2) (G1)

– Preserve scan chain

Conformal ECO
– Preserve clock gating Analyze
SDC

ECO
 Tech Mapping & Optimization Tech
Library
– Optimize ECO logics Patch
Patch

– Map ECO logics to Technology library

 ECO netlist generation Optimizatio
n&
– Write out ECO netlist (G3) Technology
Mapping

 ECO netlist validation

– Run G2 vs. G3 comparison
New Netlist
(G3)

Equivalence
SOCE
Check Post-mask
P&R

© 2023 Cadence Design Systems, Inc. All rights reserved,. 14

 Functional ECO Flow: Step 2B
Post-mask ECO – Spare Gates
In addition to all pre-mask steps, the following
are required for post-mask ECO, targeting New Netlist Old Netlist
(G2) (G1)
Spare Gates
Conformal ECO SDC
Analyze
 DEF is used to derive ECO QRC
– Spare cell types and instance quantities SPEF
Patch
Patch
– Spare physical location LEF

 Also used Lib

Physically
– LEF, QRC tech file [SPEF optional] Aware
Spare Gate DEF
 In addition to technology mapping, Tech.
mapping
– Maps ECO logics to spare & freed up gates (G1)
– Considers spare gate’s physical location
New Netlist SG Map
– Reports inadequate spare cell resources (G3) File

Note: Enabled by ECOGXL license

Equivalence
SOCE
Check Post-mask
P&R

© 2023 Cadence Design Systems, Inc. All rights reserved,. 15

 Functional ECO Flow: Step 2C
Post-mask ECO – Gate Array
In addition to all pre-mask steps, the following
are required for post-mask ECO, targeting Gate New Netlist
(G2)
Old Netlist
(G1)

Array
Conformal ECO SDC
Analyze
 DEF is used to derive ECO QRC
SPEF
– Instances of GA filler cells
Patch
Patch
– Physical location of GA filler cells LEF

 Also used Lib

Physically
– LEF, QRC tech file [SPEF optional] Aware DEF
GA Tech.
 In addition to technology mapping, mapping

– Maps ECO logics to GA lib cells (G1)

– Considers physical location of filler cells
New Netlist GA Map
– Reports inadequate filler cell resources (G3) File

Note: Enabled by ECOGXL license SOCE

Equivalence
Check Post-mask
P&R

© 2023 Cadence Design Systems, Inc. All rights reserved,. 16

 Starting and Exiting
Starting Conformal ECO
 Menu mode: lec [-eco | –ecogxl]
 Command mode: lec [–eco | -ecogxl] –nogui [-color]

 Switch between menu and command modes: set gui [on | off]

 Batch mode
lecq { -m job1g_128 } -eco -dofile <batch_file> -nogui
dofile <batch_file>

Resetting the Software without Exiting

reset

Closing
exit [-force]
Conformal automatically closes all windows upon exit.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 17

 Environment Setup

When perform G1 vs. G2 comparison, make sure to

 Enable ECO intention
– set eco option -flat

 Constrain designs to function mode

– add pin constraint 0 scan_se -golden
– add pin constraint 0 scan_tm_i -both
– add ignored output scan_out_* DFT_sdo* -golden

 Other modeling directives if needed

– set flatten model -seq_constant
– set flatten model -gated_clock

© 2023 Cadence Design Systems, Inc. All rights reserved,. 18

 Set the intention of the subsequent dofile commands
Command :
SET ECo Option [-LEC | -FLAT | -hier_FLAT | -HIErarchical]

-FLAT : Specifies that the intention is to run the Flattened ECO flow.
Enable the following :
SET FLATTEN MODEL -ECO
SET FLATTEN MODEL -ENABLE_ANALYZE_HIER_COMPARE

If ANALYZE HIER_COMPARE use “eco_aware” option :

-CONstraints
-NOEXact_pin_match
-FUNCTION_Pin_mapping
-INPUT_OUTPUT_Pin_equivalence
-THRESHOLD 0

© 2023 Cadence Design Systems, Inc. All rights reserved,. 19

 Set the intention of the subsequent dofile commands
-HIER_FLAT : Specifies the intention is to run the Hier. flattened ECO low.
Enable the following :

SET FLATTEN MODEL –ECO

when executing “write hier dofile” , automatically add :

-CONstraints
-NOEXact_pin_match
-Balanced_extration
-FUNCTION_Pin_mapping
-INPUT_OUTPUT_Pin_equivalence
-extract_icg
-THRESHOLD 0

© 2023 Cadence Design Systems, Inc. All rights reserved,. 20

 Set the intention of the subsequent dofile commands
Note>
To specify “-Hier” : Specifies that the intention is to run the
Hierarchical ECO flow.

This will enable the following :

SET FLATTEN MODEL -ECO

If "WRITE HIER_COMPARE DOFILE“ use “eco_aware” option

-CONstraints
-NOEXact_pin_match
-FUNCTION_Pin_mapping
-INPUT_OUTPUT_Pin_equivalence
-BALANCED_EXTRACTIONS

© 2023 Cadence Design Systems, Inc. All rights reserved,. 21

 Unbalanced Hierarchies in Designs
 Unbalanced hierarchies between two designs can result in
patch quality degradation or even failure in path generation.
 The common cause is turning on auto-ungroup in
synthesis or G1 wants to do hierarchy removing.

 There are two scenarios in unbalanced hierarchies.

1. G1 has more hierarchies than G2 :
Resynthesis G2 with disabling auto-ungroup

2. G1 has less hierarchies than G2 :

to flatten extra hierarchies in G2. See next page!

© 2023 Cadence Design Systems, Inc. All rights reserved,. 22

 Matching of Hierarchies between Blocks
Auto-ungrouping of netlists occurs during synthesis for optimization
reasons.
 This can cause problems from Conformal ECO because the hierarchy
where the ECO is supposed to be run no longer exists.
For example, a boundary such as in submodule A is dissolved into
submodule U4.

Old P&R Netlist (G1) New Synthesis Netlist (G2)

TOP TOP

U3 U4 U3 U4

U1 U2 B U1 U2 A B

Submodules with changes

© 2023 Cadence Design Systems, Inc. All rights reserved,. 23
 Matching Hierarchies Between G1 and G2
Solution
 Ensure that the levels of hierarchy between SYN1 and G1 match by disabling
auto-ungroup.
 Use the following automatic method to solve

flatten –nolibrary -revised -matchhierarchy

 The opposite scenario, to be done correctly, requires a hierarchical flattening

in the P&R netlist and in the database.

TOP TOP

U3 U4 U3 U4

U1 U2 B U1 U2 A B
© 2023 Cadence Design Systems, Inc. All rights reserved,. 24
 Uniquify netlist

Top Top

Block_0 Block_1 Test_1 Block_0 Block_1 Test_1

Block_2 Block_3 Block_4 Block_5

<golden> <revised>

To consistent module names for

matched instances in the revised Top

design :
Block_0 Block_1 Test_1

uniquify –all –nolib -revised

Block_2 Block_3

© 2023 Cadence Design Systems, Inc. All rights reserved,.

Configuring and Reporting Rule-Based ECO Setup
Checks

26 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Conformal ECO Checks
 Start the version 19.10.
 Flagging potential issues and suggesting possible resolutions early in
the ECO process
 The checks are performed automatically after the following commands
executing

--set system mode lec

--compare
--compare eco hierarchy
--analyze eco
--write hier_compare dofile (Hier-FEF flow)

© 2023 Cadence Design Systems, Inc. All rights reserved,. 27

 ECO check rule categories
 Each check has a name and a default severity.
 When an error is detected, the run is forced to stop. This is the default.
(The ”set dofile abort” command can affect this behavior)
 “report eco check –help” would list all rules and the default severity
 Rule categories
--after 19.1-s300 and 37 rules now in the version 21.20

ECO1.* - After the set_system_mode lec command

(modeling and mapping).

ECO2.* - After the compare command.

ECO3.* - After the compare_eco_hierarchy command.
ECO4.* - After the analyze_eco command.
ECO5.* - After the write_hier_compare_dofile command.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 28

 Configure ECO checks
 Command usage
SET ECo Check
<check_name*...>
[-Warning |
-Error [-CONTinue] |
-Note |
-Ignore]
(Setup Mode)

LEC>compare
…..
//Warning: (ECO2.3) The scan enable pin(s) of non-
equivalent DFF(s) is not constrained to functional mode in
Golden. (occurrence 1)

SETUP> set eco check ECO2.3 -error

© 2023 Cadence Design Systems, Inc. All rights reserved,. 29
 Diagnosing ECO Setup Checks
 A check with Error severity can cause a patch generation failure or an
incorrect patch.
 By default, the process is stopped when an error is detected.
 To diagnosis the details of eco setup check, use “ report eco check”
command to find the issue.
 Command usage
REPort ECo Check
[-ALL | <check_name* ...>]
[-Summary | -Verbose]
[-Help]
[-Ignore]
[-Note]
[-Warning]
[-Error]
[-MAX_PRINT_COUNT <limit>]

© 2023 Cadence Design Systems, Inc. All rights reserved,. 30

 Report check result
 Example for the summary report

LEC>report eco check -summary

//Warning: (ECO2.3) The scan enable pin(s) of non-equivalent DFF(s) is

not constrained to functional mode in Golden. (occurrence 6)
//Warning: (ECO2.4) The test enable pin(s) of DLAT(s) in non-equivalent
cone is not constrained to functional mode in Golden. (occurrence 2)

 Example for the detail report

LEC>report eco check -verbose
// Error: (ECO1.12) Golden design hierarchy is changed by the 'resolve' or
'flatten' command. (occurrence 2)
Golden design hierarchy is changed by the 'resolve' command. (occurrence 1)
1. resolved_module
Golden design hierarchy is changed by the 'flatten' command. (occurrence 1)
1. flattened_module

© 2023 Cadence Design Systems, Inc. All rights reserved,. 31

Flattened ECO Flow (FEF)

32 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Flattened ECO Flow (Recommended Flow)
In the flattened ECO flow, you run a Original Netlist Modified Netlist
flat compare on a hierarchical (G1) (G2)

design.
Advantages. Flat Compare Analyze Hierarchy

Nonequivalence points Identify module

 Creates all ECO patches with boundaries

one command.

Conformal ECO
Compare eco hierarchy

Disadvantages Breakdown nonequivalences

into submodules

 Flattened comparison may

Analyze ECO -Hierarchy
encounter aborts and lead to
longer compare times. Patch

 Can be harder to diagnose, if

the patch is not equivalent. Patch Optimization

Guidance
Command
Netlist with ECO File
(G3)

© 2023 Cadence Design Systems, Inc. All rights reserved,. 33

 Introduction to Flatten ECO Flow
The following slides present a dofile for running the FEF (flatten ECO flow).

Each step will be explained.

<Note>. The commands and options in green would be used in the Post-
mask ECO.

 Golden : ECO target netlist

 Revised : New function

 Constraint scan enable to keep original scan path

© 2023 Cadence Design Systems, Inc. All rights reserved,. 34

 Flatten ECO Template
set log file fef_premask_eco.log.$LEC_VERSION -replace
usage -auto -elapse

// always use this

set eco option -flat

read library <lib_files> -replace -liberty

read design <netlist1> -replace -golden
read design <netlist2> -replace -revised

flatten –nolibrary -revised -matchhierarchy

uniquify –all –nolibrary –revised

© 2023 Cadence Design Systems, Inc. All rights reserved,. 35

 Flatten ECO Template (continued)
//* Set the modeling directives
set flatten model -gated_clock
set flatten model –seq_constant
//set flatten model –all_seq_merge

report mismatch pin > misPIN.do Find the top ECO pin
dofile misPIN.do

add pin constraint 0 scan_enable -both

//add ignore output DFT_so* -golden
add ignore input DFT_si* -golden

© 2023 Cadence Design Systems, Inc. All rights reserved,. 36

 Flatten ECO Template (continued)
// prepare hierarchical patch creation
set analyze option –auto –noanalyze_abort
set system mode lec

// Analyzes the hierarchy of the flattened designs

analyze hier_compare -dofile hier.eco.do \
-replace \
-eco_aware -verbose Must be executed for each
ECO run

// Compare the flattened designs

add compare points -all
Compare –gate_to_gate

// Break down the nonequivalent points to their submodules

compare eco hierarchy
report eco hierarchy –verbose (-hierarchy)
© 2023 Cadence Design Systems, Inc. All rights reserved,. 37
 Flatten ECO Template (continued)
// Create the hierarchical patch.
// This command also creates the ecopin.do dofile
analyze eco -hierarchical –preserve_clock\
patch.v \
-ecopin_dofile ecopin.do -replace

Find the block ECO

set system mode setup pin

// Add and/or delete extra pins

dofile ecopin.do

// Apply the hierarchical patch to the flat netlist

apply patch –auto -gold –keephierarchy \
–freescan –stitchscan –shiftenable scan_enable 1 \
-tiefreed0

© 2023 Cadence Design Systems, Inc. All rights reserved,. 38

 Flatten ECO Template (continued)
// Post-mask ECO only
// spare cell / gate array cell / freed cell declaration
add spare cell -deffile LAY1.def -sparecell *spare*
add spare cell -deffile LAY1.def -gafiller *gafiller*
add spare cell –freedcell
report spare cell

© 2023 Cadence Design Systems, Inc. All rights reserved,. 39

 Flatten ECO Template (continued)
// technology mapping
optimize patch \
-verbose -workdir <working_directory> \
-library <lib_file_list> \
-sdc <sdc_filename> \
-instancenaming "ECO2inst_%d" \
-netnaming "ECO2net_%d" \
-sequentialnaming "ECO2reg_%s" \
-rcexec “genus" \
-usespare \
-lef <LEF list> \
-def <Placement File.Def> \
-galibcell <list_of_cell-name> \
-mapscript <Map File Name>

© 2023 Cadence Design Systems, Inc. All rights reserved,. 40

 Flatten ECO Template (continued)
// write scripts for EDI and in generic format
report eco changes –encounter -file eco.encounter -replace
report eco changes -script –file eco.generic –replace

//* Writes out the G3 ECO netlist

write eco design -newfile %s.pre.G3 -replace \
-report ECOprelogics.rpt

© 2023 Cadence Design Systems, Inc. All rights reserved,. 41

Conformal ECO Basic commands
For Pre-Mask flow

42 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Flatten ECO dofile
set log file logfile.$LEC_VERSION –replace
read design –file G1.v -verilog –golden
read design -file G2.v -verilog –revised
add pin constraint 0 scan_en –gold // Scan chain control
set flatten model –gated_clock // Gated clock control
set eco option -flat
set system mode lec
analyze hier –eco_aware
add compare point –all
compare
compare eco hier
analyze eco patch.v -replace –hier –ecopin ecopin.do
set system mode setup
dofile ecopoin.do
apply patch -auto
optimize patch -workdir rc_work -library typical_scan.lib \
-synexec "genus -legacy_ui“ -sdc core.sdc -verbose
write eco design -newfile %s.cfmECO -replace
report eco change
© 2023 Cadence Design Systems, Inc. All rights reserved,. 43
 When ECO need to add new pins
 Automatic method :
ROOT used only :
SETUP> REPort MIsmatched Pin > rootECO_PIN.do
SETUP> dofile rootECO_PIN.do

top
report mismatched pin
in0 ctr01
in0
in1 ECO in1 ECO
in2
in2
analyze eco

Sub-Block Level only :

LEC> analyze eco –ecopin_dofile ecopins.do

© 2023 Cadence Design Systems, Inc. All rights reserved,. 44

 Automatic method to add new pins for ROOT module

REPort Mismatch Pin

[-Gold <module_name> ]
[-Revised <module_name>]
[-TYPE <Input | OUTput>]
(Setup Mode)

// Command: report mismatch pin > new_ecopin.do

// Command: dofile new_ecopin.do
add eco pin g1_top in2 –input -gold
// Command: set system mode lec

NOTE
Always review ECO pin matching ECO version

© 2023 Cadence Design Systems, Inc. All rights reserved,. 45

 Manual method to add new pins
ADD ECo Pin
<module_name>
<pin_name> | <bus_name <size>> ...
[-INput | -OUTput | -IO]
[-FORce]
(Setup Mode)

add eco pin test_1 dc1 –input

// create eco bus pin
add eco pin mod_A wr_data[15:0] -output

 Work only on the golden design!

 If the Revised module has extra ports, use this command to add new
pins to the Golden module.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 46

 Deleting an ECO Pin on a module

DELete ECo PIn

<module_name>
<pin_name> | <bus_name <size>> ...
(Setup Mode)

del eco pin test_1 dc1

// delete eco bus pin
del eco pin mod_A wr_data[15:0]

If the Golden module has extra ports, use this command to delete the pins
to match the Revised module.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 47

 Analyze hier_compare

ANAlyze Hier –ECO_aware

[-dofile <output_dofile> ] [-verbose]
(LEC Mode)

 Must be executed for each ECO run

 Must be executed before applying “compare eco hierarchy”

// Command: analyze hier -eco

// Total Matching Moudle Instance Pairs = 5
// Gathering instance boundary information
// 1 modules are not written because of mismatched ports
// 4 modules are written for hierarchical comparison

© 2023 Cadence Design Systems, Inc. All rights reserved,. 48

 Compare ECO Hierarchy

COMpare ECo Hierarchy

[-THREADS <integer> [,<integer>] ] [-verbose]
(LEC Mode)

 Use this command in the LEC mode and after “analyze hier” and
“compare”
 Compare eco hier takes the flattened compare results, along with the
boundary information from ANALYZE HIER and breaks down the
nonequivalent points to their associated submodules
NEQ
U3 U3

U2 U2

U1 U1

© 2023 Cadence Design Systems, Inc. All rights reserved,. 49

 COMpare ECO HIerarchy
LEC> compare –gate_to_gate
LEC> compare eco hierarchy -verbose
// Analyzing Non-equivalent logic cones
(G) MODULE vga_vtim INSTANCE pixel_generator/vtgen/ver_gen
(R) MODULE vga_vtim INSTANCE pixel_generator/vtgen/ver_gen
// Non-Equivalent 1
(G) 696 DFF /pixel_generator/vtgen/ver_gen/state_reg[2]/U$1
(R) 691 DFF /pixel_generator/vtgen/ver_gen/state_reg[2]/U$1
[DATA]
(G) 26701 MUX /pixel_generator/vtgen/ver_gen/state_reg[2]/U$1
(R) 11173 INV /pixel_generator/vtgen/ver_gen/g6093/U$1
// Non-Equivalent 2
(G) 660 DFF /pixel_generator/vtgen/ver_gen/state_reg[0]/U$1
(R) 689 DFF /pixel_generator/vtgen/ver_gen/state_reg[0]/U$1
[DATA]
(G) 26665 MUX /pixel_generator/vtgen/ver_gen/state_reg[0]/U$1
(R) 11178 NAND /pixel_generator/vtgen/ver_gen/g6095/U$1
========================================================================
Compared points DFF Total
--------------------------------------------------------------------------------
Non-equivalent 2 2
========================================================================
Total non-equivalent modules = 1
*note: You will see the same results from “report eco hierarchy –verbose”

© 2023 Cadence Design Systems, Inc. All rights reserved,. 50

 REPort ECO Hierarchy

LEC> report eco hierarchy -hierarchy

// Command: report eco hierarchy -hierarchy
TOP (NEQ:2)
core_dft (INS:u_core) (NEQ:3)
SYS_dft (INS:u_SYS) (NEQ:57)
CTLREG_dft (INS:u_cltreg) (NEQ:57)
zara_top_dft (INS:u_zara) (NEQ:1)
ldp_top_dft (INS:u_ldp) (NEQ:1)
efuse_0_dft (INS:efuse_top) (NEQ:9)
Total non-equivalent modules = 7

===========================================================

© 2023 Cadence Design Systems, Inc. All rights reserved,. 51

 Patch Generation

Old Netlist (G1) ECO’ed Gate

o1 o1
o2 O2’

o3 o3

EQ O1’
• Compare Designs
NEQ O2’ • Analyze ECO patch : G2-G1 = ΔG
• Apply patch : G2 = G1+ΔG
EQ O3’

New Netlist (G2)

52
 Simple example

Old RTL (R1) : assign B = A; ECO RTL (R2) : assign B = ~A;

A B A B
Old Gate (G1) : Old Gate (G2) :

Patch: ECO Netlist (G3)

Module top_eco(.A(A), .B(B)); Freed cell

Input A; A
X X
Output B; B
INV GATE1(.A(A), .B(B)); top_eco
endmodule
A B

53
 Analyzing the ECO Change
ANAlyze Eco <patch_filename>
[-REPlace | APPend]
[-EFFort <HIGH | MEDIUM | ULTRA >]
[-PRESERVE_clock | -NOADD_ICG]
[ -THREADS <integer> [,<integer>] ]
[-ECOPIN_dofile <file name>]
(LEC Mode)
// Command: compare
================================================================
Compared points PO DFF Total
------------------------------------------------------------------------
Equivalent 38 100 138
------------------------------------------------------------------------
Non-equivalent 0 2 2
================================================================
// Warning: There are extra POs in Golden
………………………………………………………………………………………………………………………….
// Command: analyze eco patch.v -rep
// Grouping
// Note: 1 group(s) added
// Note: 0 library cell(s) is in the patch
// Note: 17 primitive(s) are in the patch

Note: Only the logic cone under nonequivalent points are analyzed by the
command.
© 2023 Cadence Design Systems, Inc. All rights reserved,. 54
 ANALYZE ECO
ANAlyze ECo –effort ultra

 Will enable new post-optimization engine to further optimize the patch

 Expensive algorithm and will increase runtime

ANAlyze ECo –POST_OPTimization

 Independently activates the algorithm without ultra effort to create the

patch
Example: analyze eco –effort medium –post_optimization

 This will skip expensive grouping and boolean analysis and spend
time on patch size

© 2023 Cadence Design Systems, Inc. All rights reserved,.

 ANALYZE ECO (conti.)
ANAlyze ECo –CONNECT_ICG_TESTENABLE [AUTOmatic | MANual]

 This option is off by default.

 Would descript them in Page 75!

© 2023 Cadence Design Systems, Inc. All rights reserved,.

 ANALYZE ECO (conti.)
ANAlyze ECo –ABORTASNoneq

 By default, abort point(s) would be considered as EQ

 Use this option to consider aborts as NONEQ.

© 2023 Cadence Design Systems, Inc. All rights reserved,.

 Selective ECO Analysis
 analyze eco” will work on each non-eq point.

To skip certain nonequivalent points, do not add them to the compare list.

set system mode lec

add compare point –all
delete compare point A_REG*
compare
analyze eco patch.v –rep

Golden Revised
U1 U1
U2
U2
A A X

© 2023 Cadence Design Systems, Inc. All rights reserved,. 58

 Clock Tree Preservation in CECO
 To avoid changes to the clock tree during the ECO process, CECO
preserves the Clock Tree Implementations
 CECO also can preserve the enable function in clock gating netlists
 CECO can now preserve the clock tree by using a Data-Hold structure
as an alternative gating method

Gated by ICG Gated by Data-holding

D Q
DFF Q
EN D DFF
CKO
CK EN
ICG CK

© 2023 Cadence Design Systems, Inc. All rights reserved,. 59

 Clock Path Change : Clock Preservation

// Command: analyze eco patch.v -rep ICG removed

// Note: 0 library cell(s) is in the patch EN
DFF2

CKO
// Warning: 2 DFF clock(s) are changed in the patch CK

// Note: 25 primitive(s) are in the patch

DFF1

G1 G2
DFF2 DFF2
EN
CKO CK
CK

ICG DFF1 DFF1

DFF2
EN
// Command: ana eco patch.v -rep -preserve_clock CKO
CK
// Note: 0 library cell(s) is in the patch
// Note: 30 primitive(s) are in the patch ICG
DFF1

© 2023 Cadence Design Systems, Inc. All rights reserved,.

 ANALYZE ECO with "-noadd_icg"
 Worked on the mapped DFFs , not for the new added DFF.
 Use MUX feedback (Data-Hold ) structures to preserve the clock tree.
 If there is no corresponding DFF in Golden, Conformal ECO can only
replicate the revised netlist in the patch and cannot prevent generating
ICGs.
G1 G2 G3

DFF2 DFF2
EN1 EN2
CKO
CK CKO D2_in DFF1
CK
ICG New ICG CK
DFF1 EN2

DFF1
EN1
CKO D1_in
CK
DFF1
ICG EN1
CKO
CK

ICG

© 2023 Cadence Design Systems, Inc. All rights reserved,. 61

 Applying a Patch
APPly PAtch
<module_under_ECO_name>
<patch_module_name>
[-KEEPHierarchy]
[-KEEPFREED| -FREENONSCAN <0|1> | -STITCHSCAN ]
[-FREESCAN]
[-AUTO]
[-Golden | -Revised]
(Setup Mode)

// Command: apply patch -auto

// Note: read design patch1.v -append -lastmod -norulesummary
// Parsing file patch1.v ...
// Note: Read VERILOG design successfully
// Note: 6 library cells are in the patch
// Note: 3 primitives are in the patch
// Note: 6 library cells were freed
// Note: No library cells were recycled

© 2023 Cadence Design Systems, Inc. All rights reserved,. 62

 Sequential ECO with deleted ECO flops (1)

G1.v G3.v
D
si DFF1 DFF2 DFF3 so
D
si DFF1 DFF2
SI
DFF3 so

apply patch
Keep both scan and data logic
(DFFs on scan chain will not be freed)
ECO
G2.v 1’b0/1
G3.v
D
si DFF1 DFF2 DFF3 so
si DFF1 DFF3 so

apply patch –freednonscan <0|1>

Keep scan logic
Free data logic by tied a constant in DFF D-pin

© 2023 Cadence Design Systems, Inc. All rights reserved,. 63

 Sequential ECO with deleted ECO flops (2)

Apply patch Apply patch -freescan

SI SO SI SO
SI Q SI Q SI Q SI Q SI Q

CK CK CK CK X SI Q X CK

DFF1 DFF2 DFF3 DFF1 DFF3

CK

DFF2

Force CECO to free DFFs on chain

“scan chain” is broken

SI SO
SI Q SI Q Apply patch –freescan –stitchscan
CK X SI Q X CK –shiftenable scan_se 1
DFF1 DFF3
CK
DFF is freed
DFF2 Scan chain is stiched

© 2023 Cadence Design Systems, Inc. All rights reserved,. 64

 scan chain being touched
 No DFF deleted
Why scan chain being touched ??

Shifter register
Shared function & scan path

If adding a gate in this DFF

input path, it will broken the
scan chain
ECO2.7 may be flagged
after comparison

© 2023 Cadence Design Systems, Inc. All rights reserved,. 65

 Check Scan chain
REPort SCan Chain
[-SI <pin>] [-SO <pin>] [-se <pin*> <scan_active_value>]
(Setup Mode)

// Command: report scan chain -si DFT_sdi_1 -so DFT_sdo_1 -se se 1

bit 1 del_hcount/regout_reg[0]
bit 2 del_hcount/regout_reg[1]
bit 3 del_hcount/regout_reg[2] The SI/SO should
bit 4 del_hcount/regout_reg[3]
bit 5 del_hcount/regout_reg[4]
be the ECO top
bit 6 del_hcount/regout_reg[5] ports
bit 7 del_hcount/regout_reg[6]
bit 8 del_hcount/regout_reg[7]
bit 9 wrapn_reg
// Command: apply patch -auto -freescan -KEEPHierarchy -stitchscan -shiftenable se 1
// Warning: 3 DFFs were freed
// Command: report scan chain -si DFT_sdi_1 -so DFT_sdo_1 -se se 1
bit 1 del_hcount/regout_reg[0]
bit 2 del_hcount/regout_reg[1]
bit 3 del_hcount/regout_reg[2]
bit 4 del_hcount/regout_reg[5]
bit 5 del_hcount/regout_reg[6]
bit 6 wrapn_reg

© 2023 Cadence Design Systems, Inc. All rights reserved,. 66

 ECO Scan Link Reports

ECO Scan Link Reports

 Report the scan flops and the drivers to their scan input pins.
 Command Syntax
REPort ECo Scan_input
[ -FILE <repor> ] [-REPlace] ]
[ -GOLden | REVised ]
(LEC Mode)

 Example
// Command: report_eco_scan_input -file g1_scan_input.lst
/ Info: total 2 scan input(s) are collected

 Library Requirements

© 2023 Cadence Design Systems, Inc. All rights reserved,. 67

 Output Message and Format
 Report format :
<full path name of scan input pin>: <+|-> <full path name of the driver>

 Example

© 2023 Cadence Design Systems, Inc. All rights reserved,. 68

 Sample Usage
 G1-G2 ECO Stage

 G3-G2 Validation Stage

 use text diff to see if the report is same as G1 report.

exec diff g1_scan_input.lst g3_scan_input.lst > g1_g3_scan_diff.lst

© 2023 Cadence Design Systems, Inc. All rights reserved,. 69

 Case 1 : No New Flops Added to G3
 When the ECO does not add any new flops to G3, the text comparison
of the two reports should be identical.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 70

 Case 2 : New Flops Added to G3
 The text comparison of the two reports is the same except for the newly
added flops.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 71

 Test Enable Connection For Newly Added ICGs
 CECO follows one of rules below to patch the test enable pin function of
the ICG cell.
1: Follows the ICG cell connection in G2 (Default setting)

2: Connects the TE pin to the test enable signal in G1 that enabled by

“analyze eco –connect_icg_testenable automatic”

3: Connects the TE pin to the signal manually by command

 Library Requirement Identified as an ICG

Identified as the TE pin

© 2023 Cadence Design Systems, Inc. All rights reserved,. 72

 Method to connect the new ICG test-enable pin
 Manual : Connect the test-enable pin to user specified driver

SET ECo Icg_testenable

[-NET | -PORT | -DRIVER_PIN <name>]
[-MODULE_INST <path_name> | -MODULE <module_name>] [-INVERT]
(Setup Mode)

 Example
SETUP> set eco icg_testenable -port TEST_EN -module_inst /m1/m2
SETUP> set eco icg_testenable -driver_pin Dff/Q -module_inst /m3/m4
LEC> analyze eco -connect_icg_testenable manual

<Note> The specified signal must be a G1 signal or the command will error
out.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 73

 Method to connect the new ICG test-enable pin
 Automatic : Identify the proper test-enable (TE) driver and connects it

LEC> analyze eco -connect_icg_testenable automatic

// Command: analyze_eco -hier patch.v -ecopin ecopin.do -connect_icg_testenable automatic

// Analyzing top (path:/)
// Note: 1 group(s) added
// Note: 1 library cell(s) is in the patch
// Warning: 2 DLAT(s) is in the patch
// Warning: 1 DFF clock(s) is changed in the patch
// Note: 1 ICG test-enable pin driver is found and connected.
// Note: 1 ICG test-enable pin driver cannot found. Connected the test-enabe
pin to constant.

No TE Driver is Found,
connected to constant
as default.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 74

 Current Setting Report : report eco icg_testenable
 To displays a list of all user specified test-enable signals to drive the
new ICGs by the command “set eco icg_testenable”
 Example

LEC> report eco icg_testenable

Test Enable Control Rule Report:
1 set_eco_icg_testenable -port teA -module_inst /m1
2 set_eco_icg_testenable -port teB -module_inst /m2
3 set_eco_icg_testenable -net n3 -module_inst /m1/m3
4 set_eco_icg_testenable -driver_pin /m1/e -module mod_5

© 2023 Cadence Design Systems, Inc. All rights reserved,. 75

 Test-Enable Connection Report
 To check the test-enable pin connection of new ICG DLAT, use the
command ”report_eco_changes -detail_seq_report”
 Example

© 2023 Cadence Design Systems, Inc. All rights reserved,. 76

 New report for ICG cell Test Enable Connection
 In general, users would expect no test enable pin change for ICGs that
exists in both G1 and G3
 Users can use the report to check if the test enable pin connection of
newly added ICG meets their expectation.
 Command Syntax
REPort ECo Testenable_input
[ -FILE <report> ] [-REPlace] ]
[ -GOLden | REVised ]
(LEC Mode)

 Example
add_pin_constraint 0 TE -both
set_system_mode lec
report_eco_testenable_input -file g1.testenable.rpt -golden
report_eco_testenable_input -file g2.testenable.rpt -revised

© 2023 Cadence Design Systems, Inc. All rights reserved,. 77

 Output Message and Format
 Report format :
<full path name of ICG's test enable pin>: <+|-> <full path name of the driver>

 Example:

© 2023 Cadence Design Systems, Inc. All rights reserved,. 78

 Example of G1-G3 Report Text-Diff
 By comparing G1 and G3 reports, users can check if there are
any ICG or test enable connection changes.

Line1: No difference. The test enable connections of ICG0 are the same.
Line2: The test enable connection of ICG1 has changed to TE2 in G3.
Line3: ICG2 is removed in G3.
Line4: ICGN is a newly added ICG in G3.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 79

Technology Mapping ECO function

80 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Patch Technology Map Process

 Map the generated patch to the OPTimize PAtch

target technology library
MOD
 Pre-mask : all cells are usable
MOD_eco
 Post-mask: limited cell type. Not (n1, A);
Not (n2, B);
and (n1, n2, C);
 Flatten mapped patch
 Timing driven optimization active by
feeding SDC A C
 Optimize patch –sdc <sdc_file> B

 SDC must match ECO root module

MOD
<Note> Use “-SUPPRESS_SDCError” A
C
B
to suppresses errors related to the reading
in of the SDC file
© 2023 Cadence Design Systems, Inc. All rights reserved,. 81
 Optimize Patch with GENUS
 Generate a synthesis script (cfm_eco_rc.tcl). This script will include any
specified user scripts.
 Writes out the optimized patch and returns to CECO
OPTimize Patch
-WORKdir <working_directory>
[-RELATIVE2CWD]
[-LIBrary <library_file_list>]
[-SYNExec <GENUS_executable>]
[-SDC <sdc_filename>]
[-VERbose]
[-KEEPHierarchy]
[-CLEANUP]
[-AVOID <cell_name>*]
[-USE <cell_name>*]
(Setup Mode)

 –SYNExec /site/mtktools/Genus/2x.xx/tools.lnx86/bin/genus

© 2023 Cadence Design Systems, Inc. All rights reserved,. 82

 To review the patch optimization log
 The log file would be in the directory specified by “-WORKdir” option
and named ”rc.log”

........
Sourcing '../presyn.tcl' (Thu Feb 24 20:30:24 -0700 2022)...
Setting attribute of root '/': 'unmap_scan_flops' = false
Setting attribute of design 'cfm_eco_patch_1': 'dft_scan_map_mode' = preserve
Info : Mapping. [SYNTH-4]
: Mapping 'cfm_eco_patch_1' using 'high' effort.

Global mapping target info

==========================
Cost Group 'm_clk' target slack: 1130 ps
Target path end-point (Port: cfm_eco_patch_1/FE_OFN413_scan_se_2o)

Global mapping status

==========================

© 2023 Cadence Design Systems, Inc. All rights reserved,. 83

 Optimize Patch Options: Naming Styles
-NETnaming <format_string>
Specifies the net-naming format of the ECO nets. For example,
for eco_net_%d, the %d will be an integer that makes the net
name unique.
-INStancenaming <format_string>
Specifies the instance-naming format of the ECO
combinational cells. For example, for eco_instance_%d, the
%d will be an integer that makes the instance name unique.
-SEQuentialnaming <format_string>
Specifies the instance naming format of the ECO registers and
latches. For example, eco_%s, where %s is the original
register name.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 84

 Example : Naming Styles

// Command: optimize patch -work SYN_WORK -lib /home/LIB/std_cell.lib \

// -NETnaming “eco_net_%d” \
// -INSTancenaming “eco_inst_%d”
// Note: Wrote VERILOG design successfully
// Parsing file OPT_PAT/abc_eco.gv ...
// Note: Read VERILOG design successfully
// Note: Flatten patch abc -instance abc_eco
// Command: write design eco.v

ECO.v
INVCKHHD eco_XXX_ctrl_rst_dd_inv(.O(rst_dd_inv), .I(Net13542));
OAI13BHD eco_inst_1(.O(XYZ_nxt_8_), .A1(eco_net_10), .B1(eco_net_14), .B2(
eco_net_13), .B3(abc34));
AO222CHD eco_inst_2(.O(XYZ_nxt_1_), .A1(eco_net_15), .A2(eco_net_12), .B1(
eco_net_23), .B2(eco_net_16), .C1(n663), .C2(N123));

© 2023 Cadence Design Systems, Inc. All rights reserved,. 85

 Optimize Patch Options: Avoid/use cells

 Restrict mapping cell types

 The order that specify the –avoid and –use options is
significant.
SETUP> optimize patch –avoid *HVT
 Cells name with HVT can not be used

SETUP> optimize patch –avoid * -use *LVT

 Only cells name with LVT can be used. (HVT, RVT are not allowed)

SETUP> optimize patch –avoid * -use AN2* INV*

 Only 2 input AND and Inverter are allowed

SETUP> optimize patch -use AN2* INV* –avoid *

 No cells can be used
© 2023 Cadence Design Systems, Inc. All rights reserved,. 86
 Integrate User-Created Synthesis Scripts
 The following modify the RC run script at various points:

[-PRELIBscript <script_name>] Runs before reading in libraries

[-PRESYNscript <script_name] Runs before each patch is synthesized
[-POSTSYNscript <script_name>] Runs after each patch is synthesized

 By default, CECO generates Genus Common UI script.

 When using with option –synexec genus –legacy_ui, it generates a Legacy UI
script
 The user scripts that included in cfm_eco_rc.tcl have to be the same
format

© 2023 Cadence Design Systems, Inc. All rights reserved,. 87

 Issue : Need to map the Scan-DFF
 In the pre-mask flow, CECO will use Non-scan DFF as the default for
the new added DFF due to ECO size consideration.
 New methods to get the scan-DFF mapped when optimizing the patch :
After version 16.2 , use the option “PRESYNscript” :

apply patch –auto …………

optimize patch -workdir SYN_WORK -library .slow.lib \
-PRESYNscript “../presyn.tcl”

proc eco_pre_synthesis_cmd {patch} {

set_db [vfind $patch] .dft_scan_map_mode preserve
}

set_db [get_db designs *] .dft_scan_map_mode preserve

© 2023 Cadence Design Systems, Inc. All rights reserved,. 88

 Issue : Keep user added module

 C-ECO default ungroup any module instance in patch

Appended module will be flatten

G1 G2 G3
U1 U1 U1
E U2 REG1 REG1

 Do not flatten (keep the hierarchy) of patches smaller than 10k gates

Optimize patch –noflatten_small

© 2023 Cadence Design Systems, Inc. All rights reserved,. 89

 Solution : Keep user added module
 User added module will be kept by optimize patch sourcing
below PRESYNscript

apply patch mod1 mod1_eco -gold –keephierarchy

optimize patch -workdir SYN_WORK -library .slow.lib \
-PRESYNscript “../presyn.tcl”

presyn.tcl

 In Genus common UI mode :

set_db [get_db design .modules *ECO_MOD*] .ungroup_ok false

© 2023 Cadence Design Systems, Inc. All rights reserved,. 90

 Keeping Constants in the Patch

 By default, patch optimization implements Boolean constants in the

patch by connecting them to tie-hi or tie-low cells.

//BUFCHD rm_net_12(.I (1'b0), .O (\net[12]_1o ));

BUFCHD rm_net_12(.I (logic_0_1_net), .O (\net[12]_1o));
TIE0DHD tie_0_cell(.O (logic_0_1_net));

 Option “-NOUSETIEcell” to preserve the patch constants.

And the “assign statement “ would be kept.

apply patch -auto

optimize patch -workdir SYN_WORK -library .slow.lib –verbose \
-NOUSETIEcell

© 2023 Cadence Design Systems, Inc. All rights reserved,. 91

 Issue : Can not insert Tie Cell
 If fail to use tie cell :
 No tie cell in library
 TIE cell in library with “dont_use” attribute

// Command: optimize patch -work Genus_work -lib ../typical.lib -verbose

………
Warning : No tie hi/lo cell found for tiecell insertion. [UTUI-204]
: Could not find a tie hi/lo cell to insert tiecells in /designs/TIME_STATE_MACHINE_eco.
: Possible reason is that the tiecells in library are avoided, if present. Unavoid them to use for tiecell
insertion.
Error : Cannot proceed with tiecell insertion. [UTUI-216] [new_tiehilo::insert_tiehilo_cells]

: Fix the problems reported above.

 Option [-use <tie_cell_name*>] to disable “dont_use” attribute

// Command: optimize patch -work Genus_work -lib ../typical.lib –verbose –use TIE*
………
Info : Connecting all 1'b0 and 1'b1 to TIELO/TIEHI cells. [UTUI-207]
Info : Done connecting 1'b0 and 1'b1 to TIELO/TIEHI cells. [UTUI-210]

© 2023 Cadence Design Systems, Inc. All rights reserved,. 92

 Issue : Specify Tie cell Types
 If there are multiple tie cells in the library and you want to specify the
tiecell type for constant mapping

apply patch –auto …………

optimize patch -workdir SYN_WORK -library .slow.lib \
-use LOGIC0_X1 LOGIC1_X1\
-avoid TIE0*

© 2023 Cadence Design Systems, Inc. All rights reserved,. 93

 Issue : Only one Tie cell type existed
 If only one type of tie cell exists in the library or spare cell , use the option
-allowtiecellinversion to allow inverted use of the tie cell.

Example : only tie low cell (LOGIC0_X1) is available

apply patch –auto …………

optimize patch -workdir SYN_WORK -library .slow.lib \
-allowtiecellinversion -use LOGIC0_X1

Optimize patch
1’b1 TIEL

© 2023 Cadence Design Systems, Inc. All rights reserved,. 94

 Issue : Constants Still Exist
 Constant assign exist when OPTimize Patch –NOUSETIE
 Assign will be removed by optimize patch sourcing the following
PRESYNscript

apply patch -auto

optimize patch -workdir SYN_WORK -library .slow.lib \
-PRESYNscript “../remove_assign.tcl”

remove_assign.tcl

set_db remove_assigns true

remove_assigns_without_optimization -dont_skip_unconstrained_paths

© 2023 Cadence Design Systems, Inc. All rights reserved,. 95

 Sequential Constant and Sequential Merge in Patch
Optimization
 Prior to 20.10-s200, sequenital mergeing and constant optimization is
default on.
 Starting from 20.10-s200, the default changes to off.

apply patch -auto

optimize patch -workdir SYN_WORK -library .slow.lib \
-PRESYNscript “../seqOPT.tcl”

seqOPT.tcl

# Genus Common UI version

set_db / .optimize_merge_flops true
set_db / .optimize_constant_0_flops true
set_db / .optimize_constant_1_flops true
set_db / .optimize_constant_feedback_seqs true

© 2023 Cadence Design Systems, Inc. All rights reserved,. 96

ECO result output

97 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Reporting ECO Changes

REPort ECo Changes

[-MODule <module_name>]
[-SUMmary | -SCRipt | -INNOVUS]
[-FILE <filename> [-REPlace]]
[-detail_dff_report ] (Setup Mode)

// Command: report_eco_changes CONNECT PIN : 76

================================ 1: present_state_reg[1].D->ECO1net_2
MODULE arb 2: present_state_reg[0].D->ECO1n
================================ DISCONNECT PIN : 42
RENAME NET : 1 1: present_state_reg[1].D <-> n_21
1: n_2 -> ECO1net_1 2: present_state_reg[0].D <-> n_22
ADD NET : 21 ADD INSTANCE: 21
1: n_21_3 1: ECO1inst_1 (NOR2_X1)
2: n_22_3 2: ECO1inst_2 (XOR2_X2))
DEL NET : 10 DEL INSTANCE: 11
1: n_22 1: p6843D (OAI22_X1)
2: n_21 2: p6691D (OAI21_X2)
3: n_15 …

© 2023 Cadence Design Systems, Inc. All rights reserved,. 98

 Report ECO change on Sequential Element and
Clock
 report eco change –detail_seq_report

© 2023 Cadence Design Systems, Inc. All rights reserved,. 99

 Example : ECO instructions Set
// Command: report eco changes –script > change_script.tcl

Example change_script.tcl
Example
# ===============================================
is
# MODULE chip truncated.
# ===============================================
set_root_module chip
# DISCONNECT PINS : 230
disconnect_pin {icd_core/mc_top/u5/p4379A/A2} ;# net:icd_core/mc_top/u5/state[59] , dir:in
# DEL INSTANCES : 212
delete_instance {icd_core/dbg_top/p29680A} ;# OAI22D0
# ADD INSTANCE : 1
add_instance {chip_eco} {chip_eco}
# ADD NET : 27
add_net {icd_core/mc_top/u5/state[59]_1}

© 2023 Cadence Design Systems, Inc. All rights reserved,. 100

 Writing an ECO Design
WRIte ECo Design [-OVERWrite | -NEWFILE [filename_fmt]
| -DIR <dir_name> [-GZIPNEWFILE]]
[-REPORT <filename>] [-REPlace]

// Command: write eco design

-newfile %s.G3 -replace
-report ECOlogics.rpt

Notes:
1. ECO netlist filename will have a format of <G1name>.G3.
2. Stored in the same location as G1 netlist if no “DIR” option

UNIX tkdiff-friendly format:

© 2023 Cadence Design Systems, Inc. All rights reserved,. 101

WRIte ECo Design -timestamp
write eco design -newfile %s.pre.G3 -replace -timestamp ver1.1
// ECO ver1.1
// SDFF_X2 \state_reg[0] (.SI(n_396),
// .SE(FE_OFN265_scan_se),
// .QN(n_397),
// .Q(\state[0] ),
// .D(rst),
// .CK(rc_gclk_10009));
SDFF_X2 \state_reg[0] (.CK(clk),.D(ECO2net_1),.SE(FE_OFN265_scan_se),.SI(n_396),.Q(\state[0]
state[0] )

write eco design -newfile %s.pre.G3 -replace –timestamp

// ECO 2021-12-24
// SDFF_X2 \state_reg[0] (.SI(n_396),
// .SE(FE_OFN265_scan_se),
// .QN(n_397),
// .Q(\state[0] ),
// .D(rst),
// .CK(rc_gclk_10009));
SDFF_X2 \state_reg[0] (.CK(clk),.D(ECO2net_1),.SE(FE_OFN265_scan_se),.SI(n_396),.Q(\state[0] )

© 2023 Cadence Design Systems, Inc. All rights reserved,.

 Conformal ECO Basic commands
For Post-Mask flow

103 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Postmask Manual ECO Process
A postmask manual ECO process,
 Requires designers to
 Check availability of different kinds of spare cells
 Map to optimal spare cells
 Check whether the ECO created a timing or DRV problem

 Is usually a multi-iteration process

 Can take days or weeks

Placed design
*
Spare gate
*
*
Unmapped gate

© 2023 Cadence Design Systems, Inc. All rights reserved,. 104

 Automated Postmask ECO Process
Automated postmask ECO process includes:
 Automatic decomposition of functions into actual resources available in the design

 Automatic physical remapping from unmapped gates to spare gates and freed cells
 Accurate timing that is placement-aware

 Spare cell swap file for use when needed

Example: Postmask ECO

Spare gate/ Placed design

Freed cell

Automatic!

Unmapped gate

© 2023 Cadence Design Systems, Inc. All rights reserved,. 105

 Command APPly PAtch
Post-mask ECO – Spare Gates
APPly PAtch …
[ | -KEEPFREED | -TIEFREED0 | -TIEFREED1]
(Setup Mode)

Keep Freed cell

Apply patch Apply patch -keepfreed
Freed cell Freed cell
A B A B
X X X
top_eco top_eco
A B A B

Apply patch –tiefreed0 Apply patch –tiefreed1

Freed cell Freed cell

A B A B
X X
top_eco top_eco
A B A B

© 2023 Cadence Design Systems, Inc. All rights reserved,. 106

 Freed cell handling
 Pre-mask ECO should delete as many free cells as possible
 Post-mask ECO is not allowed to delete any cell.
 -keepfreed cells are not allowed for recycle.
 -tiefreed0/1 cells can be recycled

 Apply patch can be independently on specified modules

 Apply patch –auto on the rest modules

analyze eco patch.v –hier –rep

set system mode setup
read design patch.v –append
apply patch U1 U1_eco –tiefreed0
apply patch A A_eco –tiefreed0
apply patch –auto -keepfreed

© 2023 Cadence Design Systems, Inc. All rights reserved,. 107

 Adding Spare Cells
Post-mask ECO – Spare Gates
ADD SPare Cell
[-DEFfile <filename>]
[-FReedcell]
[-SParecell <cell_INS_name*> ... ]
(Setup Mode)

 Adds the spare cells or freed cells as the available cells for the
OPTIMIZE PATCH command in the post-mask flow.
 Need to be applied before “optimize patch”

© 2023 Cadence Design Systems, Inc. All rights reserved,. 108

 Reporting Spare Cell :
Summary report
REPort SPare Cell
[-FReedcell] [-Sparecell]
[-SUMMARY ]
(Setup Mode)

© 2023 Cadence Design Systems, Inc. All rights reserved,. 109

 Reporting Spare Cell
Post-mask ECO – Spare Gates

REPort SPare Cell

Displays all of the spare cells that have been

specified

// Command: add spare cell -def ./DEF/tapeout.def -spare *spare*

// Note: 225 cells added
// Command: add spare cell -freedcell
// Note: 10 cells added
// Command: report spare cell
(1) (F) /chip/smb/cmdreg_0_ <hxth1qb>
(2) (F) /chip/smb/cmdreg_1_ <hxth1q>
(3) (F) /chip/smb/cmdreg_2_ <hxth1q>
…
(11) (S) chip/spare_18 <NAND2_X4> (372020, 145600)
(12) (S) chip/spare_19 <NAND2_X4> (385320, 145600)
(13) (S) chip/spare_20 <SDFFRS_X1> (401280, 179200)
…

© 2023 Cadence Design Systems, Inc. All rights reserved,. 110

 Command Add | Report Spare Cell
Post-mask ECO – Gate Array

ADD SPare Cell

[-DEFfile <filename>]
[-FReedcell]
[-gafiller <instancename*> ... ]
(Setup Mode)

// Command: add spare cell -def ../pr/g1.pr.def -gafiller GAFILL*.

// Note: 1975 cells added
// Command: add spare cell -freedcell
// Note: 0 cells added
// Command: report spare cell
(1) (G) GAFILL_impl3_1 <GDCAP4BWPLVT> (16240, 16240)
(2) (G) GAFILL_impl3_2 <GDCAP4BWPLVT> (21840, 16240)
(3) (G) GAFILL_impl3_3 <GDCAP4BWPLVT> (89040, 16240)
(4) (G) GAFILL_impl3_4 <GDCAP4BWPLVT> (94640, 16240)
(5) (G) GAFILL_impl3_5 <GDCAPBWPLVT> (100240, 16240)
(6) (G) GAFILL_impl3_6 <GDCAP2BWPLVT> (103040, 16240)
…

© 2023 Cadence Design Systems, Inc. All rights reserved,. 111

 Deleting Spare cell
DELete SPare Cell
[-FReedcell <hier_ins_name*> ... ]
[-Sparecell <hier_ins_name*> ... ]
[-CELLtype <cell_name*>…]
[-ALL]
(Setup Mode)
Deletes the spare cells or freed cells that were added
with the ADD SPARE CELL command. In essence, it
enables discriminating use of certain spare gates for
particular ECOs.

// Command: delete spare cell -freedcell chip/smb/cmdreg_*

// Command: delete spare cell -sparecell chip/spare/spare_1*
…
// Command: delete spare cell –celltype NAND2*
// Command: report spare cell

© 2023 Cadence Design Systems, Inc. All rights reserved,. 112

 Physically Aware Mapping and Optimization
Post-mask ECO – Spare Gates

OPTimize PAtch
… -USESPARE: Enables spare gate mapping and/or
[-USESPARE] gate array mapping
[-MAPscript <output file>] -MAPscript <filename>: Writes out the location-
aware spare gate mapping result in the form of an
|-SPEF <input file>] SoC Encounter TCL script. This option should be
[-DEF <input file> ] used with the -DEF option.
[-LEF <input file> ]

// Command: optimize patch … -lib ../lib/std.lib \

// -usespare \
// -mapscript SGmapping.tcl \
// -def ./DEF/tapeout.def \
// -lef ./LEF/FreePDK45_lib.lef
Note: read design rc_work/execute_i_eco.gv -append -lastmod -norulesummary
Parsing file rc_work/execute_i_eco.gv ...
Warning: Total black box modules referenced in Golden = 2
Note: Read VERILOG design successfully

© 2023 Cadence Design Systems, Inc. All rights reserved,. 113

 Physically Aware Mapping and Optimization
Post-mask ECO – Spare Gates (conti.)
 Mapped spare cell information in the RC log:

ECO-INFO: Final summary of Spare / Freed instance usage

Spare / Freed Type of Instance Patch

instance used spare instance within patch name

--------------------------------------------------------------------------------
spare_1/s_gate9 SPARE g80 U1/U22/FM_CTRL_eco
spare_1/s_gate1 SPARE NOT_USED NOT_USED
spare_1/s_gate22 SPARE NOT_USED NOT_USED
spare_1/s_gate15 SPARE g85 U1/U22/FM_CTRL_eco
spare_1/s_gate18 SPARE g100 U1/U30/PWR_CTRL_eco
ECO-INFO: Total ECO Violations - 0
ECO-INFO: SYNTHESIS PASSED WITH NO VIOLATIONS

© 2023 Cadence Design Systems, Inc. All rights reserved,. 114

 Physically Aware Mapping and Optimization
Post-mask ECO – Gate Array

OPTimize PAtch
…
[-USESPARE]
[-MAPscript <output file>]
|-SPEF <input file> ]
[-DEF <input file> ]
[-LEF <input file> ]
[-GAlibcell <cellname*> ]

// Command: optimize patch … -lib ../lib/std.lib \

// -usespare \
// -mapscript GAmapping.tcl \
// -def ./DEF/tapeout.def \
// -lef ./LEF/FreePDK45_lib.lef \
// -GAlibcell GINV* GDF* GO* GMUX* GN*
Note: read design rc_work/execute_i_eco.gv -append -lastmod -norulesummary
Parsing file rc_work/execute_i_eco.gv ...
Warning: Total black box modules referenced in Golden = 2
Note: Read VERILOG design successfully
© 2023 Cadence Design Systems, Inc. All rights reserved,. 115
 Physically Aware Mapping and Optimization
load QRC technology file to Synth. Tool
 CECO have an option “Captable” in the “optimize patch” command used
when doing the post-mask ECO.
 But below 40 nm, most customers would like to use QRC technology
file instead of a capacitance table file.

<For Genus>

optimize patch -workdir rc_work -library .slow.lib \

- QRCtech “../qrc_tech_FILE”

© 2023 Cadence Design Systems, Inc. All rights reserved,. 116

 Spare Gate Mapping File Used in PnR
Post-mask ECO – Spare Gates

Placed design New Netlist SG Map Old design db

(G3) File

Load Configuration

Read G3 netlist

SOC ENCOUNTER
ecoDefIn

Load SG Map File

ecoRoute
ECO gates (G3) Spare Gates Signoff

File “SGmapping.tcl”:
#######Spare Gate Mapping file Generated by Conformal ECO Designer############
ecoSwapSpareCell pixel_generator/vtgen/ver_gen/ECO2inst_1 spare_10/spr_gate025
ecoSwapSpareCell pixel_generator/vtgen/ver_gen/ECO2inst_2 spare_10/spr_gate021
ecoSwapSpareCell pixel_generator/vtgen/ver_gen/ECO2inst_3 spare_10/spr_gate023

© 2023 Cadence Design Systems, Inc. All rights reserved,. 117

 Gate Array Mapping File Used in PnR
Post-mask ECO – Gate Array

Placed design New Netlist GA Map Old design db

(G3) File

Load Configuration

Read G3 netlist

SOC ENCOUNTER
ecoDefIn

Load GA Map File

ecoRoute
ECO gates (G3) Gate Array Signoff

File “GAmapping.tcl”:
#######Gate Array Mapping file Generated by Conformal ECO Designer############
addInst -cell GOR2D2BWPLVT -inst pixel_generator/vtgen/ver_gen/ECO2inst_1 -loc 18.620 87.500 -ori R0
addInst -cell GND2D1BWPLVT -inst pixel_generator/vtgen/ver_gen/ECO2inst_2 -loc 12.320 84.980 -ori R0
addInst -cell GND2D1BWPLVT -inst pixel_generator/vtgen/ver_gen/ECO2inst_3 -loc 15.820 84.980 -ori R0
addInst -cell GND2D1BWPLVT -inst pixel_generator/vtgen/ver_gen/ECO2inst_4 -loc 16.520 79.940 -ori R0
© 2023 Cadence Design Systems, Inc. All rights reserved,. 118
 Streamlined Setup for ECO Patch Validation

119 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 ECO netlist is NEQ ??
 Try to Do the 2nd ECO.
 Check if missing pin constraints or need “analyze setup” command
 False NEQs : Design Constraints missing

Example:
add primary input ……

This kind of command result would be deleted or missed

if the following commands are executed after the above command

uniquify (CFM)
apply patch (CECO)

© 2023 Cadence Design Systems, Inc. All rights reserved,. 120

 Streamlined ECO Patch Validation
 The streamlined ECO verification is able to carry over the before-ECO
design and ECO changes such as new flops' mapping to help patch
validation.
 This solution can reduce setup and comparison runtime, and can
eliminate setup related NEQs due to mapping or sequential modeling
issues.
 A complete streamlined ECO verification flow contains two stages:

1. Setup, collect and save the before-ECO design information and ECO
changes in G1-G2 stage

2. Apply verification information to LEC compare for G3-G2 for patch

validation

© 2023 Cadence Design Systems, Inc. All rights reserved,. 121

 ECO Patch Generation stage :
 Setup, collect and save the before-ECO design information and ECO
changes to verification information

G1

Compare ECO G3

G2

Verification
Information

© 2023 Cadence Design Systems, Inc. All rights reserved,. 122

 Patch Generation : Command Syntax and Usage
set verification information <verification_information_directory>
 A directory to save the verification information.

 Run at the beginning of patch generation stage to capture all the verification
information.

write_verification_information <verification_information_directory>
 Save the verification information to the specified directory.

 Run at the very last step of patch generation stage, after “optimize patch”

© 2023 Cadence Design Systems, Inc. All rights reserved,. 123

 Sample Dofile : Setup and Collect Verification Information
 The following illustrates an improved dofile that captures the verification
information, during patch generation
// Enable the capturing of verification information
set verification information ceco_uvi
read library ...
read design ...
<constraint, modeling directives such as gated_clock, seq_const..>
dofile DFT.do

set analyze option -auto –report_map

analyze eco patch.v -replace ...

set system mode setup

...
apply patch ... ....
optimize_patch ……..

// Write out the information when ECO patch is generated

write verification information ceco_uvi
write eco design …………….

© 2023 Cadence Design Systems, Inc. All rights reserved,. 124

 Patch Generation : Streamlined ECO Information Reporting
 When running the command “optimize patch”, the keypoint mapping and
flop merging information will be collected to the verification information.

...
// Command: set_verification_information ceco_uvi
// Verification information is set to ceco_uvi.
...
...
// Command: optimize_patch
...
// Note: Collect 185 mapping information(s) in the patch to verification information.
// Note: Collect 86 merge flop(s) in the patch to verification information.
...
// Command: write_verification_information ceco_uvi
// Verification information is written to ceco_uvi.
...

© 2023 Cadence Design Systems, Inc. All rights reserved,. 125

 Streamlined ECO Patch Validation :
 Apply verification information to LEC compare for G3G2 validation

G3

Compare

G2 Ensures
successful
validation

Verification
Information

© 2023 Cadence Design Systems, Inc. All rights reserved,. 126

 Patch Validation : Command Syntax and Usage

set verification information <verification_information_directory> -setup all

 A directory for LEC to load the verification information.

 Run at the beginning of patch validation stage

set flatten model -specified_setup_only -noauto_modeling

 Specify that LEC only performs sequential constant and sequential

merge modeling specified in verification information. Also enables
mapping from the verification information.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 127

Sample Dofile - Patch Validation
 It is strongly recommended to run patch validation in a separate run.
// Enable the capturing of verification information
set verification information ceco_uvi -setup all
read library ...
read design ...

set analyze option -auto –report_map

set flatten model -specified_setup_only -noauto_modeling

<constraint, modeling directive such as gated_clock, seq_const..>
dofile DFT.do

set system mode lec

add compared points -all
compare

 Note the same DFT constraints should be applied on G3 when validating

the patch.
 Currently, such external constraints are not captured by the verification
information.
© 2015 Cadence Design Systems, Inc. All rights reserved. 128
t

Patch Validation : Streamlined ECO Information Reporting

 After switching to LEC mode in the validation stage, the modeling
message F21 shows merged flops defined from verification
information.

 Mapping from verification information are shown in USER class.

// Command: set verification information ceco_uvi -setup all
// Verification information is set to ceco_uvi
// Command: set flatten model -specified_setup_only -noauto_modeling
...
// Command: set system mode lec
// Read in 329 merge group(s) from verification information.
// Processing Golden ...
// Modeling Golden ...
// (F21) Merged 88 DFF/DLAT(s) due to added instance equivalences (flatten)
...
// Mapping key points
...
// Mapped 11310 key points by verification information
...
Mapped points: USER class
----------------------------------------------
Mapped points PI PO DFF Total
-----------------------------------------------
© 2023 Cadence Design Systems, Inc. All rights reserved,. 129
 Block level Flattened ECO
: To avoid the long run time in the big design

130 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Flatten ECO

 Positive: easily setup

 Negative: Run time increase as design increase

© 2023 Cadence Design Systems, Inc. All rights reserved,. 131

 Block level / Partition ECO

 Divide design into blocks

 Automatically identify changed or unchanged blocks
 Perform FEF on changed modules

© 2023 Cadence Design Systems, Inc. All rights reserved,. 132

 When to use HFEF ECO ?

 ECO occurs in a deep hierarchy.

 Flattened-comparison and modeling for the entire design take a
long time.
 ECO block(s) are relatively small compared to the whole design.
 There are no changes on the ECO block interface

© 2023 Cadence Design Systems, Inc. All rights reserved,. 133

 Hier-FEF Recommended Scenarios
 Hier-FEF runs FEF on each ECO block where an ECO block is a
module including ECO submodule(s).
 The ECO block has no interface changes which enables it to be
written out during hierarchical dofile generation.

the ECO is to “modA_1” , ”modA_2”

User can set modA as ECO block!
The modA should have no interface
changes

© 2023 Cadence Design Systems, Inc. All rights reserved,. 134

 Hier-FEF Flowchart

Support multiple ECO blocks

in one run

© 2023 Cadence Design Systems, Inc. All rights reserved,. 135

 1. Common setting

set eco option –hier_flat

usage –auto
set analyze option –auto –noanalyze_abort –report_map
set compare option –gate_to_gate

read library .....

read design g1.v .....
read design g2.v .....

flatten –nolibrary –revised –matchhierarchy

uniquify –all –nolibrary –revised

set flatten model –seq_constant –gated_clock

//Disable SCAN path

add pin constraint 0 scan_se –both

© 2023 Cadence Design Systems, Inc. All rights reserved,. 136

 2. Tag ECO block
tclmode
set eco_blocks [list moduleA ]
foreach module $eco_blocks {
add_module_attribute $module -flat_eco_module -both }
vpxmode

ADD MOdule Attribute

<MODULE* >
[-FLAT_ECO_MODULE]
[-analyze_eco_string <commad_string>]

 During hierarchical dofile generation in Hier-FEF, the output of

command analyze eco is replaced with <command string> for the
specified <module>.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 137

 2. Tag ECO block (conti.)
 Example :
--Original commands for the output ECO module

--With “analyze_eco_string” option :

analyze_eco –hierarchical –ecopin_dofile A.ecopins.do A.patch.v –preserve_clock

–replace

© 2023 Cadence Design Systems, Inc. All rights reserved,. 138

 3. Generate hierarchy dofile

write hier_compare dofile hfef.hier.do -replace -verbose

 Only the ECO block(s) in the hierarchy dofile.

 ECO setup Check for hierarchy dofile generating:
ECO5.1 : Failed to output ECO module with the attribute “flat_eco_module”

 Example :

© 2023 Cadence Design Systems, Inc. All rights reserved,. 139

 4. Run FEF on ECO blocks
tclmode
foreach module $eco_blocks {
run_hier_compare hfef.hier.do –root_module $module $module
–nodynamic_hierarchy }
vpxmode

 ECO setup check for “compare_eco_hierarchy”

ECO3.1 : The output port of ECO block is a function and scan shared port

© 2023 Cadence Design Systems, Inc. All rights reserved,. 140

 5. apply patch, optimize_patch, write out eco design

set system mode setup

set root module top –both

tclmode
foreach module $eco_blocks {
if { [file exists ${module}.ecopins.do ] } { dofile ${module}.ecopins.do}}
vpxmode

delete black box –hier –all –both

report black box
apply patch –auto
optimize patch –workdir SYN_work –library …..
write eco design –newfile g3.v –replace

© 2023 Cadence Design Systems, Inc. All rights reserved,. 141

 NEQ Module Analysis in RTL for Hier-FEF flow

142 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 RTL NEQ Module Analysis Flow
 In the Hier-FEF , the user needs to provide a list of ECO modules. This
NEQ module list can be obtained by comparing the original RTL (R1)
and the ECOed RTL (R2).

 In the RTL NEQ module flow, we do not run the ”analyze eco” command.

set_eco_option -r2r_eco_module_analysis
Enable:
read design R1.v -golden set x conversion dc –both
set mapping method –name first
read design R2.v -rev –sensitive
set system mode lec set flatten model
–eco
analyze hier_compare –eco_aware
–enable_analyze_hier_compare
add compared points -all
compare
compare eco hierarchy
report eco hierarchy
report eco hierarchy > NEQ_modules.rpt

© 2023 Cadence Design Systems, Inc. All rights reserved,. 143

 ECO Cut Point Flow (ECP)

144 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Why need cut point ?

G1 and G2 netlists have

higher structure similarity

The ECO is quite far away from the NEQ points. If cut points are inserted to the operands
The complex logic and timing optimization in the of the arithmetic operation in the gate-
synthesis stage increase the complexity of the level netlist, then Conformal ECO has
ECO problem.
then CECO patch could be larger than expected..
larger chances to generate a small patch.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 145

 ECO Cut point flow
 The ECP flow is an automated flow that can refine and reduce the
size of a patch by leveraging existing RTL and gate-level netlist
information to create a database of reference (cut) points
 Requirement
 R1, R2, G1, G2

 Creating ECP database by:

 R1R2, R1G1, R2G2 compare.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 146

 ECP Flow Steps

Step 1: Compare RTL1 and RTL2. Store

RTL1 RTL2 RTL nets that are potential cut candidates
in DB.
Step 2: Compare RTL1 and G1. Store
Database
the equivalent (RTL1 net, G1 gate) pairs
in DB.
Step 3: Compare RTL2 and G2. Store
the equivalent (RTL2 net, G2 gate) pairs
G1 G2 in DB.
Step 4: Combine DB entries from Step 2
and Step 3 to form triples: (RTL nets, G1
Analyze eco
gate, G2 gate).
cutpoint
These gates will be used as cut point
candidates.
Analyze ECO Patch

147
© 2023 Cadence Design Systems, Inc. All rights reserved,.
 Step 1: Create R1R2 Database to store Cut
Point Candidates
 Analyze RTL1-RTL2 for the significant signals inside the fanin cone of
the NEQ key points. The RTL-diff are shown in the output db file.
## Design
read design r1.v .....
read design r2.v -revised
set system mode lec
add compare point
compare
analyze eco –create_db R1R2 r1r2.db -replace

FILE r1r2.db
.r1 eq_pre_vol // RTL1 module name
.r2 eq_pre_vol // RTL2 module name
.net data_in[8] U$1/U$9 U$1/U$9
.net tmp[8] U$4/U$49 U$4/U$41
.net U$4/U$54 U$4/U$54 U$4/U$42
.net n17_5 U$5 U$5
.net tmp__3dB[8] add_47/SUM[8] add_47/SUM[8]
...
...
.end

© 2023 Cadence Design Systems, Inc. All rights reserved,. 148

 Step 2: Create R1G1 Database
 It performs the equivalent analysis to search for corresponding signals in
gate-level netlist for the significant signals in step 1.
## Design
read design r1.v .....
read design g1.v .....
set system mode lec
add compare point
compare
analyze eco –create_db R1G1 r1g1.db –import_db r1r2.db –replace

FILE r1g1.db
.r1g1 eq_pre_vol // G1 module name
.gate - n17_5 U90/g1
.gate + n17_5 reg_eq_pre_vol[2]
.gate + n43[17] U56/g1
.gate - n43[17] U15/g2
.gate - n43[19] U80/g1
.gate + n43[19] U114/g2
...
.end

© 2023 Cadence Design Systems, Inc. All rights reserved,. 149

 Step 3: Create R2G2 Database
 The same process is applied to search for the corresponding signals in
G2 for the RTL2.
## Design
read design r2.v .....
read design g2.v .....
Set system mode lec
add compare point
compare
analyze eco –create_db R2G2 r2g2.db –import_db r1r2.db -replace

FILE r2g2.db
.r2g2 eq_pre_vol // G2 module name
.gate + n17_5 U115/g1
.gate + n17_5 U116/g1
.gate - add_43/B[20] U166/g1
.gate + add_43/B[20] U143/g2
.gate - n17_4 U90/g1
...
...
.end

© 2023 Cadence Design Systems, Inc. All rights reserved,. 150

 Step 4: Combine DB and create the patch
 From the DB in step2 and step3, a pair of G1 signal and G2 signal are
selected
 This action doesn't create new non-equivalence except this cut point.
## Design FILE cut.do
read design g1.v ..... // 1: Cutpoint data_in[16]
read design g2.v ..... add eco cutpoint data_in[16] \
set eco option -flat -GOLDEN + U45/g4 \
set system mode lec -REVISED + U179/g1/__UU$3 \
analyze hier -eco // 2: Cutpoint data_in[19]
add eco cutpoint data_in[19] \
add compare point
-GOLDEN + U35/g4 \
compare -REVISED + U173/g1/__UU$3 \
report eco cutpoint –auto –file cut.do –import_db r1g1.db r2g2.db // 3: Cutpoint data_in[23]
dofile cut.do add eco cutpoint data_in[23] \
analyze eco cutpoint -GOLDEN + U97/g3 \
analyze eco patch.v -REVISED + U164/g1/__UU$3 \

© 2023 Cadence Design Systems, Inc. All rights reserved,. 151

 Step 4 (conti.) :
 Example for cut point output

// Command: analyze eco cutpoint

// Compare results against original non-equivalent compare points
================================================================================
PO Total
--------------------------------------------------------------------------------
Equivalent 24 24
--------------------------------------------------------------------------------
Non-Equivalent 0 0
================================================================================

© 2023 Cadence Design Systems, Inc. All rights reserved,. 152

 Time to use ECP
 Control path change can get better quality if FEF patch size not good
 Dataptah change may not help if Datapath module get ungrouped
 Adding new function will not help.

©153
2023 Cadence Design Systems, Inc. All rights reserved,.
 Patch Size Improvement with Automatic Cut Insertion
 The automatic cut insertion would insert cut-points before ECO analysis
to limit the ECO search space and improve the patch size.

 With automatic cut insertion, CECO adds cuts in the fan-in cone of the
NEQ keypoints. The added cuts focus on reducing NEQ keypoints.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 154

 Automatic Cut Insertion
 Command usage
set eco option
-PATCH_OPTIMIZATION_ALGORITHM name_cut

© 2023 Cadence Design Systems, Inc. All rights reserved,. 155

 Sequential Change

156 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Sequential Changes
Clock

Clock tree
 Conformal ECO pick up one of clock leaf for new sequential cells

 Not ensure to be best leaf

 Need user to review the result.

G1.v G2.v G3.v

clk clk
clk ECO_DFF ECO_DFF

clk_1 clk_1
DFF DFF DFF

clk_2 DFF clk_2 DFF

DFF

© 2023 Cadence Design Systems, Inc. All rights reserved,. 157

 Swapping DFF in patch
 No DFF added or deleted in RTL change
 WHY adding DFF and free DFF in patch ????

R1 always @(posedge clk))

A <= Z;

R2 always @(posedge clk or posedge rst))

if ( rst) A <= 1’b0
else A <= Z;

// Command: analyze eco patch.v –rep

// Warning: 1 DFF(s) is in the patch
// Command: apply patch –auto
// Warning: 1 DFF is in the patch
// Warning: 1 DFF were freed

© 2023 Cadence Design Systems, Inc. All rights reserved,. 158

 Async-rst, Async-set, Aync-set-rst DFF ECO
 In CECO, async type DFF change can be a patch with or without new
DFF type change.

S
ECO
A D Q C D Q C
A
ECO
R

B
G1 G2

Way 1: Way 2:
• Add a new DFF (A-set ) • Set DFFs as Inverted mapping
• ECO cone A • ECO cone A
• Connect cone B to S • Add one inverter at Q
• Connect cone C to Q

 Add one new DFF  NO new DFF

© 2023 Cadence Design Systems, Inc. All rights reserved,. 159

 DFF type change for set/reset swapping
 If the DFF type change could be done just by adding the INV cell,

RST
S
IN D Q OUT

Golden U1_reg
CLK
R

S
IN D Q OUT

Revised U1_reg
CLK
R
RST

 Please add the following command before switching to LEC mode

SETUP>set mapping method –phase

© 2023 Cadence Design Systems, Inc. All rights reserved,. 160

 ECO check : ECO2.8
 MESSAGE :
The non-equivalent DFF(s) in Golden uses a different
asynchronous/synchronous set/reset DFF cell than the Revised.

 Example :

LEC>compare
// Warning: (ECO2.8) The non-equivalent DFF(s) in Golden uses a different
asynchronous/synchronous set/reset DFF cell than the Revised.

LEC>report eco check ECO2.8 -verbose

// Warning: (ECO2.8) The non-equivalent DFF(s) in Golden uses a different
asynchronous/synchronous set/reset DFF cell than the Revised.
1: (G) 6 DFF /dout_reg/U$1

© 2023 Cadence Design Systems, Inc. All rights reserved,. 161

 MB change principle
No DFF type change
CECO try to minimize the patch change by reusing the existing DFFs.

No function change no touch.

 G1 multibit, G2 single bits. Both bits compared to be Equivalent

Remain as multibit.
G1 A_reg_1_0_ G2 A_reg_1_
G3 A_reg_1_0_
EQ
A_reg_0_
EQ

 D pin, Q pin function pin change. Keep MB cells

G1 A_reg_1_0_ G2 A_reg_1_ G3 A_reg_1_0_
NEQ
A_reg_0_
NEQ
© 2023 Cadence Design Systems, Inc. All rights reserved,. 162
 MB cells merged bits change
 Always keep original merged bits

G1 G2 G3
MB[7:6] [7] MB[7:6]
MB[6:5]
[5] [5]
[4] [4] [4]
MB[3:2] [3] MB[3:2]
MB[2:1]
[1] [1]
[0] [0] [0]

© 2023 Cadence Design Systems, Inc. All rights reserved,. 163

 MB to SB with function change
 MB cells change only one of merged cell’s shared function (clock, set,
reset …) . MB cells must be split

G1 G2 G3
A_reg_1_0_ A_reg_1_
EQ R
A_reg_1_ R
Local_rst
R Local_rst

NEQ A_reg_0_ R
A_reg_0_
R R
global_rst
Local_rst global_rst

G3
R
A_reg_1_0_

Local_rst
 Keep the original MB cell :
R
A_reg_0_
SET ECo Option -PRESERVE_MULTIbit_flop
global_rst

Only ECOed bits will be replaced by the new flop!

© 2023 Cadence Design Systems, Inc. All rights reserved,. 164

 Structure-Aware Feedthrough Preservation
 The feedthrough structure may not be preserved after ECO. With this
option, CECO not only generates the patch with correct function but also
preserves the feedthrough structured after ECO.

set_eco_option -feedthrough_preserve
(SETUP mode)

© 2023 Cadence Design Systems, Inc. All rights reserved,. 165

 Equivalent Signal Analysis for manual ECO

166 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Find the corresponding nets
 Take a Golden net name and finds the corresponding
equivalent nets and signals in the Revised.

 Command Syntax
WRIte COrresponding Nets
<netnames>
[ -COMbinational ]
[ -INCLUDE_FANIN <netnames>]
[ -INCLUDE_NEQ_FANIN]
[ -module <module_name> ]
[ -EFFort < low | high | medium | ultra > ]
[ -threads <number> ]
[ -replace ]
[ -Golden | -Revised ]
[-verbose]

(LEC Mode)

© 2023 Cadence Design Systems, Inc. All rights reserved,. 167

 Report Correspondence

a Wire F = (a & b) & (c & d)

b f
wire “F” was optimized away
c And net “F” is not found in netlist
d
LEC> write corr nets f -comb
Golden Result: f=g c

a g Conformal ECO will report

b wire “F” in golden can be
d
implemented by Net “g” & net “c”
c F=g&C
e

Revised
© 2023 Cadence Design Systems, Inc. All rights reserved,.
 Option : -include_fanin
 To find the equivalent signals for all gates in the fan-in cone of the
specified signal, not need to run “write corresponding nets” for each
individual signal!
 Assume B and C are in the fanin cone of signal A. To find the equivalent
signals for A, B, and C with this option at the same time by specified A

 Example:

© 2023 Cadence Design Systems, Inc. All rights reserved,. 169

 Option : -include_NEQ_fanin
 To find all of the equivalent signals for all gates in the fanin cone of all
non-equivalent points

 Example :

© 2023 Cadence Design Systems, Inc. All rights reserved,. 170

 Option : -module
 Collect all gates of the user-specified module and report the
corresponding equivalent signals for each gate

 Example :

© 2023 Cadence Design Systems, Inc. All rights reserved,. 171

 ECO Variations

172 © 2022 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 CECO crashed before executing “apply patch”
 1. Check the “patch” file is ready or not.

 2. Restart CECO to read in the new generated patch file back. :

………
read design G1.v
read design patch.v –append
read design G2.v -revised
apply patch *_eco
Optimize patch ……

© 2023 Cadence Design Systems, Inc. All rights reserved,. 173

 Speeding up ECO comparison, analysis and
patch generation
 Now CECO support parallelization for the following commands :

//Setting Global Parallelization

SETUP>set parallel option –threads 4
//Setting Local Parallelization (higher priority)
LEC> compare –threads 4
LEC> compare eco hierarchy –threads 4
LEC> analyze eco patch.v –threads 4

 Example :

Only enabled when the

effort of “analyze eco“ is
high or ultra

© 2023 Cadence Design Systems, Inc. All rights reserved,. 174

 Checking out ECO Pin
// Command: set system mode lec
// Mapping key points …
// Warning: Primary input dc1 in Revised have no
correspondence(s) in Golden

// Command: analyze eco patch.v -rep

// Grouping
// Note: 3 group(s) added
// Error: Patch reaches unmapped pin 'dc1
'// Note: Use command 'add eco pin' to create new port on Golden
// Note: 0 library cell(s) is in the patch
// Note: 193 primitive(s) are in the patch

// Command: apply patch –auto -keeph

// Error: Cannot find net dc1 in module test_1 (pin:test_1_eco.dc1)

 Check the ecopins dofile

 Check the result of “report mismatch pin”

175
 //Internal Error : Cannot find Non-EQ in the fanin
cone (abort:1)
 Occurred when executing “compare eco hierarchy ” command
// Command: compare eco hierarchy –verbose
//Internal Error : Cannot find Non-EQ in the fanin cone (aborts : 1)
(G) ……
(R) …………….
(+) (G)……..
(+) (R) ……..

 Root Cause : Find the eco path would be in the datapath fanin cone
and would have abort occurred.
CFM ECO can not handle this kind of path well
because the default compare engine effort is low
Tool will spend a lot of time to do the analysis also.
 Workaround :
set compare effort ultra (high) before executing the command

© 2023 Cadence Design Systems, Inc. All rights reserved,. 176

 Example 1
// Error: Failed to find corresponding net(s)
 Message
// Command: analyze eco ...
// Error: Failed to find corresponding net(s) in the root module
for the following gate(s) (G) 471 OR /rd_col_ptr_cell_reg_regx0x/U$5

// Error: Failed to find a valid patch

 Suggestion
 Have applied “set eco option –flat ” ?
 Try “-effort medium” when executing “analyze eco” command
 make sure the technology library is read in as the library, not as part of
the design.
 Bug ?? …………… Call tool owner /Cadence

© 2023 Cadence Design Systems, Inc. All rights reserved,. 177

 Example 2 : ICG wrapper module naming
// Error: Failed to find corresponding net(s)
 Message
// Error: Failed to find corresponding net(s) in the root module for the
following gate(s)
(G) 646641 OR /u_ckctrl/u_GTCLK/hc_gtck_cell/sttb_$U1/U$1
(R) 706691 OR /u_ckctrl/u_GTCLK/hc_gtck_cell/sttb_$U1/U$1

// Error: Failed to find a valid patch

 Root cause :
 This gate located in the ICG cell.
 But the wrapper name, hc_gtck_cell, is not supported by CECO.

© 2023 Cadence Design Systems, Inc. All rights reserved,. 178

 Example 2 (conti.) :
 Solution :
 Use “add noblack box” for the wrapper module if this ICG is not
inserted by Genus/DC.
 Change the wrapper module naming when coding :

Right now, CECO will automatically recognize the following naming

pattern :
SNPS_CLOCK
RC_CG
CLK_GATING_CELL
CLOCK_GATING

If the name of the ICG wrapper is not default style, please use
‘add noblack box’ to force CECO to flatten these ICG wrapper

© 2023 Cadence Design Systems, Inc. All rights reserved,. 179

 Example 3 : Hierarchical separator
// Error: Failed to find corresponding net(s)
 Message
// Note: 163 group(s) added
// Error: Failed to find corresponding net(s) in the root module for the following
gate(s)
(G) 352400 OR Adapt_Iu_A0/u_2_reg_15_/U$4
(R) 232419 OR Adapt/Iu/A0/u_2_reg_15_/U$4
(G) 352490 OR Adapt_Iu_A0/SelReg_reg_1_/U$4
(R) 232022 OR Adapt/Iu/A0/SelReg_reg_1_/U$4
// Error: Failed to find a valid patch

 Solution
set naming rule –hierarchical_separator “_” –golden
flatten –matchhier –nolib –revised
uniquify –all –revised -nolib

© 2023 Cadence Design Systems, Inc. All rights reserved,. 180

 //Internal Error : Failed to merge function
 Occurred when executing “analyze eco” command
// Command: analyze eco ………..
// Analyzing xxx_test_0_dft (path:u_A_top/xxx_A)
// Grouping
// Note: 49 group(s) added
// Internal Error: Failed to merge function:
(R) N487 (logic)
(+) (G) 1028233 NAND /u_A_top/xxx_A/U502/U$1
-> (G) 1028441 BUF /u_A_top/xxx_A/clk_gate_lh_reg_0/latch/E
(+) (or,gid:1182328)
(1'b0,gid:246959)
(buf,gid:1182327)
(R) N515 (1182255)

 Workaround : Try to lower the effort of “analyze eco” or Call Cadence

analyze eco –effort medium
© 2023 Cadence Design Systems, Inc. All rights reserved,. 181
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