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Assignment 8 - 2023 - Gate

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S S KASHYAP
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207 views

Assignment 8 - 2023 - Gate

Uploaded by

S S KASHYAP
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Circuits

Assignment 8- Week 8
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

QUESTION 1:

Which of the following options represents the fastest Analog-to-Digital Converter (ADC)?

A) counter-type
B) flash-type
C) successive-approximation
D) dual-slope type

Correct Answer: B
Detailed Solution:
Flash type ADC is fastest among the given ADCs

QUESTION 2:
What is the output of the following circuit for b4 = 0, b3=1, b2=1,b1=1 and Vref =15v

A) 5
B) -5
C) -13.125
D) -8.4375

Correct Answer: C

Detailed Solution:

V0 = - It R = -({(Vref *b4)/16R}+{(Vref *b3)/8R}+{(Vref *b2)/4R}+{(Vref *b1)/2R} ) * R = -13.125v

QUESTION 3:
What is the output of the following circuit for b4 = 0, b3=1, b2=0,b1=1 and Vref =15v?

A) -9.375
B) -4.6875
C) 15
D) -15

Correct Answer: A

Detailed Solution:

V0 = - It R = -({(Vref *b4)/16R}+{(Vref *b3)/8R}+{(Vref *b2)/4R}+{(Vref *b1)/2R} ) * R = -9.375


QUESTION 4:

What is the primary advantage of using a Mealy FSM over a Moore FSM?
A) Simplicity in design.
B) Faster response to input changes.
C) Output stability during state transitions.
D) Reduced state complexity.

Correct Answer: B

Detailed Solution:

QUESTION 5:

The figure below shows a 3-bit flash ADC circuit. What would be the encoded binary output D {D2D1D0}
when V = 8v and Vin = 4.125v?

A) 011
B) 100
C) 010
D) 110

Correct Answer: B

Detailed Solution:

Vin lies between 4 V and 5V which means output of comparator 1,2,3 and 4 would be high, rest will
be at logic 0.
Thus the input to priority encoder would be 0001111.
Thus the priority encoder output = 100
QUESTION 6:

Which of the following statements is TRUE?


A) R-2R ladder DAC requires high precision resistors
B) Binary weighted resistor DAC conversion time is lower compared to R-2R ladder DAC.
C) Binary weighted resistor DAC requires large range of resistors
D) R-2R ladder DAC is the faster conversion time compared to weighted resistor type DAC

Correct Answer: C

Detailed Solution:

R-2R ladder DAC does not need high precision resistors, but binary type DAC requires large

range of resistors.

QUESTION 7:

Which of the following ADC is more expensive to build?


A) Dual slope ADC
B) Successive approximation ADC
C) Flash type ADC
D) None of the above

Correct Answer: C

Detailed Solution:

Flash type ADC requires 2 n -1 comparators.


QUESTION 8:

Let X is the input sequence whereas Z is the output sequence for the state machine shown
below. Which of the following options correctly describes the output Z sequence for input
sequence X given below (Assume FSM initially at state S0)

X=1001100

A) Z=1011000
B) Z=0100110
C) Z=0001000
D) Z=0000100

Correct Answer: D

Detailed Solution:

For X = 1 0 0 1 1 0 0, the transition in states would be


[S0] – S1(0) – S2(0) – S2(0) – S4(0) – S3(1) –S5(0) –S2(0)

The corresponding output Z = 0 0 0 0 1 0 0

QUESTION 9:

In a 5-bit successive approximation ADC with reference voltage of 1V, if an input voltage of 0.9V
is applied, after 5 clock cycles the content of SAR is
A) 10100
B) 01100
C) 10011
D) 11100

Correct Answer: D

Detailed Solution:

Vin = 0.9 V
1st iteration: VDAC = ½ = 0.5
Vin>VDAC SAR content = 10000

2nd iteration: VDAC = 0.5 + 0.25 = 0.75


Vin>VDAC SAR content = 11000

3rd iteration: VDAC = 0.5 + 0.25 + 0.125 = 0.875


Vin>VDAC SAR content = 11100

4th iteration: VDAC = 0.5 + 0.25 + 0.125 + 0.0625 = 0.9375


Vin<VDAC SAR content = 11100

5th iteration: VDAC = 0.5 + 0.25 + 0.125 + 0.03125 = 0.90625


Vin<VDAC SAR content = 11100

After 5 clock cycles SAR content = 11100


QUESTION 10:

Which of the following statements is FALSE?

A) Dual slope ADC has faster conversion time compared to successive approximation ADC
B) Dual slope ADC has slower conversion time compared to successive approximation
ADC
C) Flash type ADC expensive to design compared to dual slope ADC
D) Flash type ADC has higher resolution compared to dual slope ADC

Correct Answer: A

Detailed Solution:

QUESTION 11:
What is the resolution of an 8-bit DAC (Assume Vref = 1v)?

A) 0.0039v
B) 0.0078v
C) 0.0019v
D) 0.0015v

Correct Answer: A

Detailed Solution:
QUESTION 12:

When will offset error occur in DAC?

A) when the slope of the actual output deviates from the ideal output.
B) when there is a constant offset between the actual output and the ideal output
C) Occurs when an increase in digital input results in a decrease in the analog output
D) NOne of the above

Correct Answer: B

Detailed Solution:

QUESTION 13:
Which of the following steps is not present in the ADC conversion process?

A) Sampling and holding


B) Quantization
C) Encoding
D) Decoding

Correct Answer: D

Detailed Solution:

QUESTION 14:
Which of the following element is not present in successive approximation ADC?

A) Sample and hold circuit


B) Comparator
C) DAC
D) inductor

Correct Answer: D

Detailed Solution:
QUESTION 15:
Conversion rate of DAC depends on _______________.
A) clock speed of input signal
B) settling time of convertor
C) both A&B
D) None of the above

Correct Answer: C

Detailed Solution:

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