Decoders and Encoders

Lesson Objectives
In this lesson, we will learm about
Decoders
Expansionof decoders
Combinationalcircuit implementation with decoders
Some examples of decoders
Encoders
Major limitations of encoders
Priority encoders
Some examples of ecnoders

Decoders
As its name indicates, a decoder is a circuit component that decodes an input code. Given
a binary code of nbits, a decoder will tell which code is this out of the 2 possible codes
(See Figure l(a)).

n-to-2m 1.
nInputs
Decoder
2n-1
Figure 1(a): Atypical decoder
Thus, a decoder has n- inputs and 2" outputs. Each of the 2" outputs corresponds to one of
the possible 2" input combinations.

n-t0-2"
n Inputs Decoder 2" Outputs

Enable
Figure 1(b): Atypical decoder
Figure 1(b) shows the block diagram of a typical decoder, which has n input lines, and m
output lines, where m is equal to 2". The decoder is called nto-m decoder. Apart from
this, there is also a single line connected to the decoder called enable line. The
of the enable line will be discussed in the flowing text.
operations
 In general,output iequals Iif and only if the input binary code has a value of i.
Thus,each output line equals Iat only one input combination but is equal to 0 at
all other combinations.

Inother words, cach decoder output corresponds to a minterm of the n input

variables.

Thus, the decoder generates all of the 2" mintems of n input variables.
Example: 2-to-4 decoders
Let us discuss the operation and combinational circuit design of a decoder by taking the
Specific example of a 2-to-4 decoder. It contains two inputs denoted by A and A nd
four outputs denoted by Do, Di, D,and D; as shown in figure 2. Also note that A, is the
MSBwhile Ao is the LSB.

-D,=AA,
-D,-A,A,
A 2-to-4
-D,=AA,
A Decoder
D,=A,A
Figure 2: A 2-t0-4 decoder without enable

Decimal # Input Output

A Ao D D, D: D3
0
1 0
2 1 0 1

3 (0 0 0

Table 1: Truth table for 2-to-4 decoder

As we see in the truth table (table 1), for each input combination, one output line is
activated, that is, the output line corresponding to the input combination becomes 1,
while other lines remain inactive. For example, an input of 00 at the input will activate
line D,. 01 at the input will activate line D,, and so on
 Notice that,cach output of the decoder is actually a minterm resulting from a
certain combination of the inputs, that is
o D, =A, A0, ( minterm m) which corresponds to input 00
o D, -A, Ao, ( minterm m ) which corresponds to input O1
o D, =A,Ao, ( minterm m) which corresponds to input 10
o D; =A, Ao, ( minterm m) which corresponds to input 11

This is depicted in Figures 2 where we see that each input combination will
inovke the corresponding output, where each output is minterm corresponding to
the input combination.

A, A

D,-A,A,
D,=A,A
D,-AA
D,-A,A
Figure 3: Implementation 2-to-4 decoder
The circuit is implemented with AND gates, as shown in figure 3. In this circuit we see
that the logic equation for D is A Ag. D, is Aj Ao, and so on. These are in fact the
minterms being implemented. Thus, each output of the decoder generates a minterm
corresponding to the input combination.

The "enable" input in decoders

Generally, decoders have the "enable" input .The enable input perroms no logical
operation, but is only responsible for making the decoder ACTIVE or INACTIVE.
o If the enable E"
O 1s Zero, then all outputs are zero regardless of the input values.
is one, then the decoder performs its normal operation.

For example, consider the 2-to-4 decoder with the enable input (Figure 4). The enable
input is only responsible for making the decoder active or inactive. If Enable E is zero.
then all outputs of the decoder will be zeros, regardless of the values of A, and Ao.
However, ifE is 1, then the decoder will perform its normal operation, as is shown in the
truth table (table 2). In this table ve sec that as long as E is zero, the outputs D, to D,
will remain zero, no malter whatever value you provide at the inputs A, Ao, depicted by
wo don't cares. When E becomes I, then we see the same behavior as we saw in the case
of 2-to-4 decoder discussed carlier.

A, Ao

D,

Figure 4: Implementation 2-to-4 decoder with enable

Decimal Enable Inputs Outputs

value
A Ao Do DË D, D
X X

1
1
3 1 1 1

Table 2: Truth table of 2-to-4 decoder with enable

Example: 3-to-8 decoders

In a three to eight decoder, there are three inputs and eight outputs, as shown in figure 5.
Ao is the least significant variable, while A, is the most significant variable.
The three inputs are decoded into eight outputs. That is, binary values at the input form a
combination, and based on this combination, the corresponding output line is activated.
 -D,=AAA,
-D,= A,A,A,
3-t0-8 -D,= A,AA
A, Decoder D,=AAA
A, -D,= A,A,A,
+ D,= A,A,A,
D,= A,A,A,
-D,= AA,A
Enable

Figure 5: A3-to-8 decoder with enable

Each output represents one minterm
For example, for input combination AAjAg =001, output line D, cquals Iwhile all
other output lines cqual 0's
It should be noted that at any given instance of time, one and only one output line
can be activated. It is also obvious from the fact that only one combination is
possible at the input at a time, so the corresponding output linc is activated.

Dec. Inputs Outputs

Code A| A, A D, D, D, D, D, D, D,D,
)
0 0
0 1 0 0
3 1 0
0
1 0 0 0
0
7

Table 3: Truth table of 3-to-8 decoder

Since cach input combination represents one minterm, the truth table (table 3) contains
eight output functions, from DÍ to D, seven, where each tunction represents one and only
one minterm. Thus function Do is A Af Ap. Similarly function D is ApAjAo. The
corresponding circuit is given in Figure 6. In this figure, the thrce inverters provide
complement of the inputs, and each one of the AND gates generates one of the minterms.
It is also possible to add an Enable input to this decoder.
 D, =AzA,A,

Ag

D= A, A,

D;= AzÄ Ao

-D, =AzA,

-D, =AgA; Ag

Figure 6: Implementation of a 3-to-8 decoder without enable

Decoder Expansion
It is possible to build larger decoders using two or mnore smaller ones.

For example, a 6-to-64 decoder can be designed with four 4-to-16 decoders and one
2-to-4 line decoder.

Example : Construct a 3-to-8 decoder using two 2-to-4 deocders with enable
inputs.
Figure 7 shows how decoders with enable inputs can be connected to form a larger
decoder. Two 2-to-4 line decoders are combined to build a 3-to-8 line decoder.

The two least signifhcat bits (i.e. Ay and Ao) are connected to both decoders
o Most signifcant bit (A,) is connected to the enable input of one decoder.
The complement of most significant bit (A) is connected to the enable of the
other decoder.
When A, =0, upper decoder is enabled, while the lower is disabled. Thus, the
outputs of the upper decoder correspond to minterms D, through D,
o When A = 1, upper decoder is disabled, while the lower is enabled. Thus, the
outputs of the lower decoder correspond to minterms D, through D,.
 2--10-4
Decoder

1
Ap-
A
-D
Enabie
Ag-

2-10-4
Decoder
-DA
-D,
21 2 -D
3
Enable

decoders
Figure 7: Implementing a 3-to-8 decoder with two 2-to-4
Decoder design with NAND gates
Some decoders are constructed with NAND rather than AND gates.
the input
In this case, all decoder outputs willbe l's except the one corresponding to
code which willbe 0.

Decimal # Input Output

An Do DË D; D3
1
1

2 1
3 1 1

D, =A44, D, =A4,
D, =AA, D, =4A,
Table 4: Truth table of 2-to-4 decoder with NAND gates
This decoder can be constructed without enable, similar to what we have seen in the
design of decoder with AND gates, without enable. The truth table and corresponding
minters are given in table 4. Notice that the minters are in the complemented form.
 -D
Ap

A
- Dg

Figure 8: A 2-to-4 decoder with Enable constructed with NAND gates.

Decimal Enable Inputs Outputs

value
E' A1 An Do D' D> D3
1 X 1 1 1
1 1 1
1 1
2 1 1 1
3 1 1 1 1

D, = EA,A, D, = E4A,
D, D, = E4,4,
Table 5: Truth table of 2-to-4 decoder with Enable using NAND gates
A 2-to-4 line decoder with an enable input constructed with NAND gates is shown in
figure 8. The circuit operates with complemented outputs and enable input E' is also
complemented to match the outputs of the NAND gate decoder. The decoder is enabled
when E' is equal to zero. As indicated by the truth table, only one output can be equal to
zero at any given time, all other outputs being equal to one. The output with the value of
zero represents the minterm selected by inputs Aj and A,. The circuit is disabled when E
is equal to one, regardless of the values of the other two inputs. When the circuit is
disabled, none of the outputs are equal to zero, and nonc of the minterms are selected.
The corresponding logic equations are also given in table 5.

Combinational circuit implementation using decoder

C As known, a decoder provides the 2" minterms of n input variables
Since any boolean functions can be expressed as a sum of minterms, one can use a
decoder to implement any function of n variables.
In this case, the decoder is used to generate the 2" minterms and an additional OR
gate is used to generate the sum of the required minterms.
In this way, any combinational circuit with n inputs and m
outputs can be
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addition to m OR gates.
implemented using an n-to-2" decoder in
Remember, that
? decoder impBcments a function using
The function need not be simplified since the
the minterms, not product terms.
using a single decoder,
Any number of output functions can be implemented same input variables.
provided that all those outputs are functions of the
Adder
Example: Decoder Implementation of a Full
problem. We have two outputs, called
Let us look at the truth table (table 6) for the givencarry. Both sum and carry are functions
S. which stands for sum, and C, which stands for
of X, Y, and Z.

Decimal Input Output

value

1
1
1
1
3

1 1
1 1

1 1 1 1 1

Table 6: Truth table of the Full Adder

The output functions S & Ccan be expressed in sum-ofminterms forms as follows:
o S(X,Y,Z) = }m (1,2,4,7)
o C(X,Y,Z) }m (3,5,6,7)

Looking at the truth table and the functions in sum of minterms form, we observe that
there are three inputs, X, Y, and that correspond to eight minterms. This implies that a
3-to-8 decoder is needed to implement this function. This implementation is given in
Figure 9, where the sum S implemented by taking minterms 1, 2, 4, and 7 and the OR
gates forms the logical sum of minterm for S. Similarly, carry C is implemented by
taking logical sum of minterms 3, 5, 6, and 7 from the same decoder.
 3-t0-8
Decoder 1

3
Y 4

X
C
6

Figure 9: Decoderimplementation of a Full Adder

Encoders
An encoder performs the inverse operation of adecoder, as shown in Figure 10.
It has 2" inputs, and n output lines.
must
Only one input can be logic Iat any given time (active input). All other inputs
be 0's.
Output lines generate the binary code corresponding to the active input.

2"-to-n n Outputs
2" Inputs Encoder

Figure 10: Atypical Encoder

Example: Octal-to-binary encoder
We willuse &-to-3encoder (Figure 11) for this problem, since we have eight inputs, one
for each of the octal digits, and three outputs that generate the corresponding binary
number. Thus, in the truth table, we see eight input variables on the left side of the
vertical lines, and three variables on the right side of the vertical line (table 7).

Decimal
Inputs Outputs Code
E7 E6 E5 E4 E3 E2 E1 E0 A2 A1 A0

1 1
1 0 4
1 1 1
0 1 0 0 1
0 1 7
Table 7: Truth table of Octal-to-binary encoder
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E0
E
A0
E2
8-to-3
3 Outputs
E3
8Inputs AI
E4 Encoder
E. A?
E6
E7

Figure 11: Octal-to-binary encoder

Note that not all input combinations are valid.
Valid combinations are those which have exactly one input equal to bgic I whle all
other inputs are logic 0's.
Since, the number of inputs = 8, K-maps cannot be used to derive the output Boolean
expressions.
The encoder implementation, however, can be directly derived from the truth table
o Since Ao = 1 if the input octal digit is 1or 3 or 5 or 7, then we can write:
Ag = E + Eg + E_t E,
Likewise, A, =E +E, + Eç+ Ez, and similarly
o Az =E+ Es + Es+ E
Thus, the encoder can be implemented using three 4-input OR gates.

Major Limitation of Encoders

Exactly one input must be active at any given time.
If the number of active inputs is less than one or more than one, the output will be
incorrect.
For cxample, if E; =E-1, the output of the encoder AA¡A, =111, which implies
incorrect output.

Two Problems to Resolve.

1. Iftwoor more inputs are active at the same time, what should the output be?
2. An output of all O's is generated in 2 cases:
o when all inputs are 0
o when E is cqual to 1.
How can this ambiquity be resolved?
Solution To Problemn 1:
Use a Priority Encoder which produces the output corresponding to the input with
higher priority.
Inputs are assigned priorities according to their subseript value: e.g. higher subscript
inputs are assigned higher priority.
In the previous example, if E;-E= 1, the output corresponding to E, willbe
produced (AA,Ao = 110) since E, has higher priority than E,.
Solution To Problem 2:
Provide one more output signal Vto indicate validity of input data.
V= 0 if none of the inputs equals 1, otherwise it is 1

Example: 4-to-2 Priority Encoders

Sixteen input combinations
Three output variables Al, A0, and V
Vis needed to take care of situation when all inputs are equal to zero.
Inputs Outputs

E3 E2 E1 E0 A1 A0 Invalid
0 X X Input
0
elel 1
1 1 1 1
0 0
01

1 1 1
1 0 1 1
1 1 0
1 1
1 1
1 1 1 1
1 1
1 1 1 1

Table 8:Truth table of 4-to-2 Priority Encoder

In the truth table (table 8), we have sixteen input combinations. In the output, we have
three variables. The variable V is needed to take care of the situation where all inputs
are zero. In that case V is kept at zero, regardless of the values of A and A. This
combination is highlighted grcen In all other cases, V is kept at 1, because at least one of
the inputs is one.

When E is 1,the output combination of A, and Ao is 00. This combination is highlighted

blue.

Then we have two combinations highlighted yellow. In both these combinations,A and
Ag are 01. This is because in both these combinations is I, regardless of the value of
Eo, and since Ehas higher subscript, the corresponding output value is 01.
This is followed by four input combinations in k. In these four combinations, the
output A|Ag is 10, since E, is 1 in all these combinations, and E, has the highest
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precedence comparcd to E and Ej. Although E and E are also having a valuc of one in
this set of four combinations, but they do not have the priority.
Finally we have the last cight input combinations, whose output is 11. This is because E3
is the highest priority input, and it is equal to 1. Though the other inputs with smaller
subscripts, namely, E2, El, and EO0 are also having values of one in some combinations,
but they do not have the priority.
The truth table can be rewritten in amore compact form using don't care conditions for
inputs as shown below in table 9.

Inputs Outputs
E3 E2 E1 EO A0
0 0 X X
2 0 1
X 1

Table 9: Truth table of 4to-2 priorityencoder (compact form)

With 4 Input variables, the truth table must have 16 rows, with each row
representing an input combination.

With don't care input conditions, the number of rows can be reduced since rows with
don't care inputs willactually represent more than one input combination.
Thus, for example, row #3 represents 2 combinations since it represents the input
conditions Ez E,E,Eo-0010 and 0011.

Likewise, row # 4 represents 4 combinations since it represents the input conditions

E;E,E,E=0100, 0101, 0110 and 0111.
Similarly, row#5represents 8 combinations.
Thus, the total number of input combinations represented by the 5-row truth table =
1+ 1+ 2+ 4 + 8= 16 input combinations.

Boolcan Expressions for V, A, and Ap and the circuit:

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