IT2623

COMPUTER ARCHITECTURE, ORGANIZATION AND LOGIC CIRCUIT

PROF. | PRELIMS | 2ND SEM 2024
Logical Logical Addition / OR
Operation operation
LOGIC GATES
Logical Z=A+B
● Logic gates are the fundamental Expression
components of a digital system. They are
connected together to create a logic Truth Table
circuit. A logic circuit can have multiple
binary inputs and will result in a single A B OUTPUT
binary output.
● These gates are mainly constructed using
diodes or transistors, which function as 000
electronic switches to perform specific
“logic functions”. 011
● Digital Logic Gates
101
○ Electric circuits that takes in one or
more inputs and produces a single 111
output based on those inputs.
NAND
○ Makes logical decisions based on
the combination of digital signals Symbol
present on its inputs.

TRUTH TABLE
● Table of combinations
● No. of Combinations = 2��
○ where n = no. of inputs Logical Not - AND / Inverted AND
Operation

AND Logical Z = (A . B)’

OR Expression Z = (AB)’

Symbol

Symbol

Logical Multiplication / AND

operation
Logical
Operation Z=A·B
Z = AB
Truth Table
Logical
Expression Truth Table A B OUTPUT
A B

0 0
 0 1 0
OUTPUT 0 001011101

100111

1101

IT2624 Lecture Logical Exclusive – NOR, Equivalence

DATA COMMUNICATIONS & NETWORKING II Operation
PRELIMS | 2ND SEM 2024
Logical Z=A⊙B
Expression Z = (A ⊕ B)’
Z = AB + A’B’
NOR
XNOR

Symbol

Symbol

Not -
OR / Inverted OR

Logical
Operation

Logical
Expression
Truth Table

Z = (A + B)’

Truth Table
OUTPUT
A B OUTPUT
A B

001010100110 BUFFER

Symbol
XOR
001

010

100 Logical
Operation
111
 Logical A
Expression

Symbol

Exclusive – OR, Inequality

Logical
Operation

Logical
Expression
Truth Table

Z=A⊕B
Z = AB’ + A’B

Truth Table
A B OUTPUT 0 0 0 0 1 1

INPUT OUTPUT 0 0 1 1

1 0

1 1

2
IT2624 Lecture Logical
DATA COMMUNICATIONS & NETWORKING II Expression
PRELIMS | 2ND SEM 2024

Complementation / Inversion
NOT / INVERTER
Symbol
A’

Truth Table

INPUT OUTPUT
Logical
Operation 01

10
 NAND Gate
3-INPUT GATES ○ All NAND input pins connect to the
input signal A gives an output A’.

● NAND and NOR gates are preferred in ○ One NAND input pin is connected to the input
practice because they are cost-effective signal A while all other
and simpler to manufacture. These gates input pins are connected to logic 1.
serve as the fundamental building blocks The output will be A’.
for all digital logic families in integrated
circuits.

NAND Gate is a Universal Gate

● Implementing an Inverter Using only
O
0 1 1 1 0 0 1
A B C O A N N
R N O A1 0 0 1 0 0 1
D R N ○ An AND gate can be replaced by
0 0 0 D R
0
0 1 XOR
0 0 1 1
1 X
0 0
1● Implementing AND Using only
NAND N NAND gates as shown in the figure
0 1 0 1 0 0 1Gates
○ An OR gate can be replaced by
01 NAND gates as shown in the figure
(The OR gate is replaced by a
10
NAND gate with all its inputs
10 complemented by NAND gate
inverters).
01

10

101100101110100101111110

010

UNIVERSAL GATES 3
● A universal gate is a gate which can
implement any Boolean function without
IT2624 Lecture
need to use any other gate type.
DATA COMMUNICATIONS & NETWORKING
● The NAND and NOR gates are universal II PRELIMS | 2ND SEM 2024
gates.
(The AND is replaced by a NAND NOR Gate is a Universal Gate
gate with its output complemented ● Implementing an Inverter Using only
by a NAND gate inverter). NOR Gate
○ All NOR input pins connect to the
input signal A gives an output A’.

● Implementing OR Using only NAND

Gates
 ○ One NOR input pin is connected to ○ A NOR gate is equivalent to an inverted-input
the input signal A while all other AND gate.
input pins are connected to logic 0.
The output will be A’.

○ An OR gate is equivalent to an inverted-input

NAND gate.
● Implementing OR Using only NOR Gates
○ An OR gate can be replaced by
NOR gates as shown in the figure
(The OR is replaced by a NOR
gate with its output complemented
by a NOR gate inverter) ○ Two NOT gates in series are same as a buffer
because they cancel
each other as A’’ =A.

● Implementing AND Using only NOR

Gates
○ An AND gate can be replaced by OPERATOR PRECEDENCE
NOR gates as shown in the figure
(The AND gate is replaced by a
NOR gate with all its inputs
● The operator precedence for evaluating
complemented by NOR gate
Boolean expression is:
inverters)
1. NOT
2. AND
3. OR
REDUCING LOGICAL CIRCUITS
TO LOGICAL EXPRESSIONS

EQUIVALENT GATES 4
● The shown figures summarizes important
cases of gate equivalence. Note that
IT2624 Lecture
bubbles indicate a complement operation
DATA COMMUNICATIONS & NETWORKING
(inverter). II PRELIMS | 2ND SEM 2024

○ A NAND gate is equivalent to an

inverted-input OR gate.

○ An AND gate is equivalent to an

inverted-input NOR gate.
 shorter expressions.
○ This reduces the number of terms
needed to represent the logic
function.
● Minimization
○ K-Maps minimize the number of
gates required in a digital circuit.
○ Each term in the simplified Boolean
expression corresponds
to a logic gate, so by reducing
terms with K-Maps, you can
minimize hardware resources and
create more efficient circuits.
● Visualization
○ K-Maps provide a visual
REDUCING LOGICAL EXPRESSIONS representation of truth tables,
TO LOGICAL CIRCUITS making it easier to understand the
relationship between input
variables and the logic function's
output.
○ By visually grouping terms on the
K-Map, you can gain a better
understanding of how the function
operates.
UNDERSTANDING K-MAPS

● A K-map is a grid where each cell

represents a unique combination of input
variables.
● The number of rows and columns in the
K-MAP K-map depends on the number of
variables involved.
● Karnaugh Map is the graphical
representation of the truth table Techniques
● It visually represents the relationship
Variable Labeling Rows and
between input variables and the output
columns are
of a logic function. labeled with the
input variables
(both
complemented
and
uncomplemented
● By grouping adjacent terms in a Karnaugh
map, you can efficiently identify simplified
expressions and reduce the number of
gates required in a circuit. 5

BENEFITS OF K-MAPS IT2624 Lecture

DATA COMMUNICATIONS & NETWORKING
II PRELIMS | 2ND SEM 2024
● Simplification forms). This allows
○ K-Maps simplify complex Boolean you to easily track
expressions by highlighting similar the value of each
terms and combining them into variable for a
 specific cell.

Wrapping Around K-maps exhibit a

"wrap-around"
property. The STEPS IN K-MAPPING
leftmost and
rightmost
columns, as well
as the top and Determine The formula 2^n is used,
bottom rows, are the where n is the number of
considered number input
adjacent. This is of cells variables. This determines
crucial for forming the size of the K-map grid.
valid groups of
cells during the Construct Label the rows and columns
simplification process. the map with the variables according
to their complemented and
uncomplemented forms.

Fill the map Place 1's in the cells

corresponding to the
minterms (product terms
where the output is 1) or 0's
for maxterms (sum terms
where the output is 0) based
on the truth table.
Don’t Cares "Don't cares" can be
treated as either 1 or Group Identify adjacent cells with
0 when forming terms the same value (1 or 0) and
groups. In K-maps, form groups containing
"don't powers of 2 (1, 2, 4, 8).
cares" are
represented by the Simplify Create a product term (SOP)
letter "X" or “d”. the or sum term (POS) for each
expressio group by identifying the
n variables that
remain constant within
the group, whether they
are
complemented or
uncomplemented. Remove
Implementation of Techniques any variables that appear in
both forms within a group, as
they do not impact the output
within that particular group.
 possible number of groups while adhering to
Combine Add the product terms (SOP)
the other rules. This reduces the
Terms or multiply the sum terms
complexity of the final expression.
(POS) to obtain the simplified
Boolean Sum-of-Products (SOP) or
Product-of-Sums (POS) form.

6
IT2624 Lecture SOP
DATA COMMUNICATIONS & NETWORKING
II PRELIMS | 2ND SEM 2024
expression. ● We perform Sum of Products also known
as Sum of Minterm.
○ The minterm for each combination
of the variables that produces a 1
GROUPING RULES OF 1’S AND 0’S in the function then taking the OR
of all those terms.
● Adjacency: Cells must be adjacent
horizontally or vertically (including
wrap-around) to be considered for
grouping. Diagonal adjacency is not
allowed.

● Group Size: The number of cells in a

group must be a power of 2 (1, 2, 4, 8, 16,
etc.). Aim for the largest possible valid
groups to minimize the number of terms
in the simplified expression.

● Covering All 1's (or 0's): Ensure that

every 1 (or 0) you want to simplify is
included in at least one group. A single POS
1 (or 0) can belong to multiple groups
as
long as the groups share non-common
elements (i.e., they contribute different ● We perform Product of Sum also known
variables to the simplified term). as Product of Maxterm.
○ The maxterm for each combination
● Minimize Groups: Strive for the fewest of the variables that

2 - Variable 3 - Variable
Map Map

produces a 0 in the function then

taking the AND of all those terms.

4 - Variable Map
IMPORTANT INFO

● Cells containing 1's and 0's cannot be

part of the same group. They represent
 opposite logic values.
● The total number of cells in a group
(including "don't cares") must always be
a power of 2.
● Before using a K-map, ensure the
Boolean expression is in its standard

7
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING
II PRELIMS | 2ND SEM 2024
Example F = ABC + variables.
DEG Minte
SOP
Where F is X Y Z Produc
Abbreviation Sum of the output
Products and A, B, C, 0 0 0 m0
Meaning
D, E, = X’ · Y
Product
and G are = min(X
terms (AND
the input
operation) is
variables. 0 0 1 m1
added (OR
= X’ · Y
operation).
= min(

POS 0 1 0 m2
= X’ · Y
Expression We have to Product of = min(
Included consider the Sum
rows which 0 1 1 m3
The inputs are given to the OR gate = X’ · Y
have the
and the output of the OR gate are = min(
output ‘1’.
Representatio summed
n
Represent up by the AND gate. 1 0 0 m4
ed as ‘m’. =X·Y
We have to consider the rows which = min(X
Variables have the
Written output ‘0’. 1 0 1 m5
If the input =X·Y
is ‘0’, it has Represented as ‘M’. = min(
to be
inverted. If the input is ‘1’, it has to be 1 1 0 m6
inverted. =X·Y
Implementati All the AND = min(
on terms or All the OR
connected terms or 1 1 1 m7
to the OR connected to the AND gate. The =X·Y
gate. The output of the AND gate gives the = min(
output of output
the OR function.
gate
F=
gives the COMBINAT
(A+B+C)(D+E+ G)
output
function. Where F is the output and A, B, C,
D, E,
● Consists of logic gates whose
and G are the input
outputs at any time are determined information-processing operation
directly from the present which is logically specified by a set
combination of inputs without of Boolean functions 8
regard to the previous inputs
PRACTICAL
● Performs a specific
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II SUBTRACTORS
PRELIMS | 2ND SEM 2024
Half ● Subtracts two bits (X
Subtractor and Y) and outputs two
bits:
difference bit (D) and next
1. Minimum number of gates borrow bit (Bn)
2. Minimum number of inputs to a gate 3.
Minimum propagation time of the signal
through the circuit
4. Minimum number of interconnections 5.
Limitations of the driving capabilities of
each gate
Full ● Subtracts three bits: 2
Subtractor input bits (X and Y) and
previous borrow bit (Bp),
ADDERS & SUBTRACTORS
and outputs two bits:
difference bit (D) and next
● ADDERS
borrow bit (Bn)
○ A combinational logic circuit that ● Can be implemented as 2
performs addition half-subtractor and an
OR
● SUBTRACTORS gate
○ A combinational logic circuit that
performs subtraction

ADDERS

inputs (X and Y) and outputs two

binary digits:
Half
sum bit (S) and carry out
Adder
bit (Cout)

HOW

● Accepts two binary digits as its

 Full Adder ● Accepts two binary bits (X and Y) 1+0=1
and an input carry 1 + 1 = 01 → which is the CARRY OUT
(Cin), which overall serves
as three input bits, and ‘1’ ● Implementing HALF ADDER
outputs a sum bit (S) and
carry out bit (Cout) This will generate the truth table below:
● Can be implemented as 2 X Y S (SUM) Cout
half-adder and an OR (CARRY
gate

0+0=0 9
0+1=1
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING
II PRELIMS | 2ND SEM 2024

OUT) 0
0 0
0
0 1 0
1 0 1
1 1

This will generate the K-Map and expression

below:

S (SUM):

This will generate the logic circuit below:

Cout (CARRY OUT):

 This will generate the truth table below:
X Y Cin S Cout
(CA (SUM) (CA
RR Y RR Y
IN) OUT)

0 0 0 0 0

0 0 1 1 0

10
● Implementing FULL ADDER
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING
II PRELIMS | 2ND SEM 2024
1 1 1
0 1

0 1
10011001011
1 0
1
1 0

1 1

This will generate the K-Map and expression

below:

S (SUM):
 ● Implementing HALF SUBTRACTOR Truth
Table:
X Y D Bn
(NEXT
BORRO
W BIT)

0 0 0 0
Cout (CARRY OUT): 0 1 1 1

1 0 1 0

1 1 0 0

11
This will generate the logic circuit below:

IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II
PRELIMS | 2ND SEM 2024

K-Map and Expression:

D (DIFFERENCE):

● Implementing FULL SUBTRACTOR

 Truth Table:
X Y Bp D Bn
(PR (DIF (NEXT
EVI FE BORR
OUS REN OW
BORR C BIT)
OW E)
BIT)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

Bn (NEXT BORROW BIT):

10010

10100

11000

11111

K-Map and Expression:

D (DIFFERENCE):
Logic Circuit:

12
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II
PRELIMS | 2ND SEM 2024
 ENCODERS & DECODERS

● Encoder and Decoder are combinational

logic circuits.
● They have a key distinction: an encoder
produces binary code as its output,
whereas a decoder receives binary code
as its input.

Bn (NEXT BORROW BIT):

 ● Encoder
○ An encoder is a mechanism that
converts data signals into a
readable message for control
devices.
○ In simpler terms, Encoders are
combinational circuits that modify
binary data into N output lines.

Logic Circuit:

13
IT2624 Lecture ● The 4x2 Encoder has 4 inputs (Y3, Y2, Y1,
Y0), and 2 outputs (A1 and A0). Only 1 of
DATA COMMUNICATIONS & NETWORKING II the 4 inputs can be '1' at a time to produce
PRELIMS | 2ND SEM 2024 the corresponding binary code at the
output.
● Block Diagram:
4x2 ENCODER
 OCTAL TO BINARY ENCODER (8X3
ENCODER)
● The 8x3 Encoder has 8 inputs (Y7 to Y0)
and 3 outputs (A2, A1, A0). Each input
● Truth Table: represents an octal digit, and the outputs
INPUTS produce the binary code for that digit.
● Block Diagram:
Y3 Y2 Y1 Y0 A1

0 0 0 1 0

0 0 1 0 0

0 1 0 0 1

1 0 0 0 1 ● Truth Table:
INPUTS OUTPUT

OUTPUT Y7
Y2
A0

0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 0 0 0 1 0
1 0 0 0 0 1 0 0 0 0 1 1

● Logical expression for A1 and A0: 0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1
A1 = Y3 + Y2
A0 = Y3 + Y1

● Implementation using OR Gates: 0100000011010000000111

● Logical expression for A1 and A0:

A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
 INPUTS OUTPUT

Y
Y

0 0 0 0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0 1 0 0 0 0 1

0 0 0 0 0 0 0 1 0 0 0 0 1 0
14
0 0 0 0 0 0 1 0 0 0 0 0 1 1
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II 0 0 0 0 0 1 0 0 0 0 0 1 0 0
PRELIMS | 2ND SEM 2024

● Implementation using OR Gates:

0000100000010100010000000

1100010000000011101000000
DECIMAL TO BCD ENCODER
● The decimal-to-binary encoder typically has 00100010000000001001
10 input lines and 4 output lines. Each input
line represents a decimal digit, and the 4
outputs represent the BCD code. This
encoder takes the decoded decimal data as
input and converts it to the BCD output,
which can be found on the output lines.
● Block Diagram:

● Truth Table:

● Logical expression for A3, A2, A1, and

A0:
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
 ● Implementation using OR Gates:

● Decoder

15
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II PRELIMS | 2ND SEM 2024

○ It is a minterm generator
○ Decoders are the combinational
circuits that transform binary data
��
into 2 output lines.
○ A decoder receives a binary code
on its input lines and activates only
one of its output lines based on the
specific code.

2x4 DECODER
● The 2-to-4 line binary decoder consists of an array of four AND gates. The 2 binary inputs
labeled A and B are decoded into one of 4 outputs, hence the description of a 2-to-4 binary
decoder. Each output represents one of the minterms of the 2 input variables, (each output =
a minterm). ● Block Diagram:
 ● Truth Table:
INPUTS OUTPUTS

A B Q0 Q1 Q2 Q3

001000010100

1 0 0 0 1 0

1 1 0 0 0 1

● Logical expression for Q0, Q1, Q2, Q3:

Q0 = A’B’
Q1 = A’B
Q2 = AB’
Q3 = AB

● Implementation using AND Gates:

BINARY TO OCTAL DECODER (3X8 DECODER)
● In 3 to 8 line decoder, it includes three inputs and eight outputs. Here the inputs are
represented through A, B & C whereas the outputs are represented through D0 to D7.
● Block Diagram:

16

IT2624 Lecture DATA COMMUNICATIONS & NETWORKING II

PRELIMS | 2ND SEM 2024
 ● Truth Table:
INPUTS OUT

A B C D D D D D D5 D6
0 1 2 3 4

0 0 0 1 0 0 0 0 00

0 0 1 0 1 0 0 0 00

0 1 0 0 0 1 0 0 00

0 1 1 0 0 0 1 0 00

1 0 0 0 0 0 0 1 00

1 0 1 0 0 0 0 0 10

1 1 0 0 0 0 0 0 01

1 1 1 0 0 0 0 0 00 BCD TO DECIMAL DECODER

● The circuit translates from BCD
(binary-coded decimal) to decimal
numbers. It consider a decoder that
D7 converts from binary digits to a
seven-segment display to illuminate
0
numbers 0 to 9, that is, for lighting up a
0 one-digit decimal number.
● Block Diagram:
0

● Logical expression for D0, D1, D2, D3,

D4, D5, D6, D7:

D0 = A’B’C’
D1= A’B’C
D2 = A’BC’
D3 = A’BC
D4 = AB’C’
D5= AB’C
D6 = ABC’
D7 = ABC

● Implementation using AND Gates:

 INPUTS OUTPUT Number
Displaye
C a b c d e f g d

0 0 0 0 1 1 1 1 1 1 0 1

0 0 0 1 0 1 1 0 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1 2

0 0 1 1 1 1 1 1 0 0 1 3

● Truth Table for 7-segment display:

17
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING
II PRELIMS | 2ND SEM 2024
0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 1 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 1 0 1 1

9
 S
ENCODERS DECODERS

Combinational Combinational
circuits that circuits that convert
transform binary binary ��
data into n output data into 2 output
lines. lines.

The output lines are n. The output lines are

2��

The implemented It receives coded

signal is the actual binary data as input.
signal input.
● Logical expression for a, b, c, d, e, f, g:

a = B’D’ + C + BD + A
b = B’ + C’D’ + CD
c = C’ + D + B microprocessors, and more.
d = B’D’ + B’C + BC’D + CD’ + A
e = B’D’ + CD’ The decoder is at the receiving
f = C’D’ + B’C + B’D + A In terms of side.
g = B’C + BC’ + A + BD’ communication mode, the encoder
is at the transmitting end.

● Implementation using AND The operating The operating

Gates: procedure is simple. procedure is complex.
It is used in videos, E-mail, and It is mainly used in memory chips,
more.

MULTIPLEXER

● A combinational circuit that selects binary

information from one of many input lines and
directs it to a single output line

18
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II PRELIMS | 2ND SEM 2024

● The selection of a particular input line is controlled by a set of select lines, normally there
are 2^n input lines and n select lines whose bit combinations determine which input is
selected
● Also known as data selector, universal logic module, and Boolean generator
● 2-TO-1 LINE MULTIPLEXER

Function Table:

Logic Circuit:

● 4-TO-1 LINE MULTIPLEXER

Function Table:
 Logic Circuit:

19

IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II
PRELIMS | 2ND SEM 2024

● QUADRUPLE 2-TO-1 LINE

MULTIPLEXER
Function Table:
BOOLEAN FUNCTION
IMPLEMENTATION USING
MULTIPLEXER

EXAMPLE 1

Given: F(A, B, C, D) = Π (1, 3, 5, 7, 10, 11)

IMPLEMENTATION TABLE:

Logic Circuit: BLOCK DIAGRAM:

20
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II PRELIMS | 2ND SEM 2024
DEMULTIPLEXER
● A circuit that receives information on a single line and transmits this information to one of
2^n possible output lines

● 1-TO-4 DEMULTIPLEXER

● Function Table:
INPUTS OUTPUT

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 A

0 1 0 0 A 0

1 0 0 A 0 0

1 1 A 0 0 0
 ● Logic Circuit:

PROGRAMMABLE LOGIC DEVICE

● Programmable logic devices or PLDs are used in many applications to replace SSI and
MSI circuits; they save space and reduce the actual number and cost of devices in a given
design
● Consist of a large array of AND and OR gates which can be programmed to achieve
specified logic functions
● Classified according to their architecture 21

IT2624 Lecture point, arrays can be either fixed or

programmable
DATA COMMUNICATIONS & NETWORKING II
PRELIMS | 2ND SEM 2024
PROGRAMMABLE READ ONLY MEMORY
(PROM)
Different Types of PLDs ● Consists of a set of fixed
(non-programmable) AND gates
1. Programmable Read-Only Memory
(PROM) PROM Block Diagram
2. Programmable Logic Array (PLA)
3. Programmable Array Logic (PAL)
4. Generic Array Logic (GAL)

PROGRAMMABLE ARRAYS

● All PLDs consists of programmable arrays ●

BOOLEAN FUNCTION IMPLEMENTATION
Essentially a grid of conductors to form rows
USING ROM
and columns with a fusible link at each cross
 addresses are decoded. The AND array
EXAMPLE does not produce all the minterms as in
the ROM
Given: F1(A1, A0) = Σ (1, 2, 3), F2 (A1, A0) = Σ
(0, 2) PLA Block Diagram

BOOLEAN FUNCTION
IMPLEMENTATION USING PLA

EXAMPLE

Given:
F1 (A, B, C) = Σ (2, 4, 6, 7),
F2 (A, B, C) = Σ (0, 3, 5, 7)
Logic Diagram:

22
IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II
PRELIMS | 2ND SEM 2024

PROGRAMMABLE LOGIC ARRAY (PLA) F1:

● Used to implement circuits in SOP form ●

Can be used to implement combinational
circuit with don’t care conditions unlike ROM
4. Subtract the number of similar terms,
● Connections in the AND and OR plane are
subtract 0 if none
programmable
● The main feature of PLA is that not all
 5. Compute the total number of terms
6. Get the unique term

Below is the solution for getting the unique

term for the given expression:

Program Table:
F2:
Getting the unique term:
1. Figure out all possible combinations: F1 &
F2, F1 & F2’, F1’ & F2, F1’ & F2’ Logic Diagram:
2. Count the number of terms each: 3 terms
each, thus 3 + 3
3. Compare the results of F1, F1’, F2, F2’ and
seeing if there are similar terms
Product Input Outp
Term ABC ut
F1
F2

1 BC’ -10 11

2 AC’ 1-0 11

3 AB 11- 1-

4 A’B’C 001 -1
23
TC = T/C

IT2624 Lecture
DATA COMMUNICATIONS & NETWORKING II
PRELIMS | 2ND SEM 2024
24