Micro-architecture

COMS10015: Computer Architecture

Tom Deakin
Lecture 1
University of Bristol
 Instruction Set Architecture Recap

Instruction Set Architecture forms the interface between software and hardware.
Describes how software controls the hardware.
Abstract model:

• Describes the list of instructions.

• Describes how they interact with registers.
• Execution model.

Can write programs in the ISA (assembly programs).

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 Micro-architecture

Definition:
A micro-architecture is an implementation of an Instruction Set Architecture (ISA).

• Low-level design of the processor.

• Made up of functional blocks connected together.
• Functional blocks made up of logic gates.

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 Instructions

For an instruction:

• The architecture (ISA) says what the instruction should do at a high level, e.g add
two numbers together.
• The micro-architecture is how the processor implements each instruction.

The micro-architecture design is free to choose how to implement, as long as it

performs as specified by the ISA.

• An ISA can be implemented by different micro-architectures.

• Micro-architecture can execute any program written in the ISA.
• Processor vendors manufacture the micro-architecture.

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 Block diagrams

Common to use block diagrams to show Front End Instruction

Cache Tag L1 Instruction Cache
µOP Cache 32KiB 8-Way Instruction
Tag TLB

micro-architecture design. Branch

Predictor
16 Bytes/cycle

Instruction Fetch & PreDecode

(16 B window)
(BPU)

• Here is the block diagram for Intel

64B/cycle
MOP MOP MOP MOP MOP MOP

Instruction Queue Macro-Fusion

(50, 2x25 entries)
MOP MOP MOP MOP MOP

MicroCode 5-Way Decode

Skylake processors. Sequencer

ROM
(MS ROM)
Complex
Decoder
1-4 µOPs
Simple
Decoder
µOP
Simple
Decoder
µOP
Simple
Decoder
µOP
Simple
Decoder
µOP Stack
Engine
4 µOPs (SE)
5 µOPs

• Shows design of one core.

Adder Adder Adder
Decoded Stream Buffer (DSB)
(µOP Cache) 6 µOPs
(1.5k µOPs; 8-Way)
MUX
(64 B window)

Loop Stream
Detector (LSD)
Allocation Queue (IDQ) (128, 2x64 µOPs) Micro-Fusion

• Front-end contains instruction Load

Register Alias Table (RAT)
4µ
OP
µOP µOP µOP µOP µOP µOP Branch Order Buffer
(BOB) (48-entry)

Common Data Buses (CDBs)

FP Move Elimination Rename / Allocate / Retirement Ones Idioms Zeroing Idioms
ReOrder Buffer (224 entries)

fetch-decode.

Int Vect
µOP µOP µOP µOP µOP µOP µOP µOP

Scheduler
Integer Physical Register File Vector Physical Register File
Int Unified Reservation Station (RS)
(180 Registers) (168 Registers)
(97 entries)

• Execution Engine shows registers and

Store

256KiB 4-Way
Port 0 Port 1 Port 5 Port 6 Port 2 Port 3 Port 4 Port 7

Unified STLB

L2 Cache
µOP µOP µOP µOP µOP µOP µOP µOP 32B/cycle
INT ALU INT ALU INT ALU INT ALU AGU AGU Store Data AGU To L3
INT DIV INT MUL Vect Shuffle Branch Load Data Load Data
INT Vect ALU INT Vect ALU INT Vect ALU

functional units. INT Vect MUL INT Vect MUL

FP FMA
AES
Vect String
FP DIV
FP FMA
Bit Scan
LEA
256bit/cycle

EUs
Branch

• Memory Subsystem to support access Execution Engine Store Buffer & Forwarding
(56 entries)

64B/cycle
32B/cycle

32B/cycle
Data TLB
L1 Data Cache
to memory. Load Buffer
(72 entries) 32KiB 8-Way

32B/cycle
Line Fill Buffers (LFB)
(10 entries)
Memory Subsystem

Picture from https://en.wikichip.org/w/images/7/7e/skylake block diagram.svg

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 Micro-architecture constraints

Micro-architectures designed under a number of constraints:

• Costs, area and production yield

• Performance
• Power use/thermal limit
• Reliability, security, etc.
• Many more . . .

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 Example: Intel and x86

x86 ISAs first developed for 16-bit Intel 8086 microprocessor

(1978).
• Complex instruction set computer (CISC) design, with
variable length instructions.
• Extended with SSE, to support a floating-point vector
operations.
AMD also produce implementations of x86, along with
x86 64, the 64-bit extension to x64.

Picture from https://en.wikipedia.org/wiki/Intel 8086#/media/File:Intel D8086 CS.jpg, https://upload.wikimedia.org/wikipedia/commons/a/a8/Intel 8086 CPU Die.JPG

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 Example: Intel, AMD and x86

Intel has produced many micro-architectures:

• 8086 (1978) • ...

• i386 (1985) — 32-bit processor
• P5 Pentium (1993) • Cascade Lake (2019)

All of these are x86.

They are all implementations of the ISA (although some add extensions).
Each generation typically:

• uses smaller lithography process.

• bring performance improvements though micro-architecture design changes.

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 Example: Arm

Arm ISA:

• Arm do not manufacture chips, but license the ISA (under various models) to
others.
• Also provide a reference implementation (a micro-architecture). E.g. Neoverse.

Pictures from: https://en.wikipedia.org/wiki/Apple-designed processors#/media/File:Apple T2 APL1027.jpg, https://www.raspberrypi.org/products/compute-module-3-plus/,

https://www.anandtech.com/show/15578/cloud-clash-amazon-graviton2-arm-against-intel-and-amd/10

©Tom Deakin [email protected] 8

 Next time: The 8-bit processor

In this course, you are all going to build an 8-bit processor.

• Start with the ISA.

• List of instructions, register information, etc.
• You’ll build the micro-architecture.
• The implementation of the ISA.

We’ll walk through the details of the micro-architecture design.

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