MODULE 4

Sequential Circuits
Sequential circuits are digital circuits that store and use the previous state information to determine their
next state. Unlike combinational circuits, which only depend on the current input values to produce
outputs, sequential circuits depend on both the current inputs and the previous state stored in memory
elements.
1. Sequential circuits are commonly used in digital systems to implement state machines,
timers, counters, and memory elements. The memory elements in sequential circuits can be
implemented using flip-flops, which are circuits that store binary values and maintain their
state even when the inputs change.
2. There are two types of sequential circuits: finite state machines (FSMs) and synchronous
sequential circuits. FSMs are designed to have a limited number of states and are typically
used to implement state machines and control systems. Synchronous sequential circuits, on
the other hand, are designed to have an infinite number of states and are typically used to
implement timers, counters, and memory elements.
In summary, sequential circuits are digital circuits that store and use previous state information to
determine their next state. They are commonly used in digital systems to implement state machines,
timers, counters, and memory elements and are essential components in digital systems design.
A combinational circuit produces an output based on input variables only, but a sequential
circuit produces an output based on current input and previous output variables. That means
sequential circuits include memory elements that can store binary information. That binary information
defines the state of the sequential circuit at that time. A latch capable of storing one bit of information.
Difference between sequential and combinational circuits
Latches
The Basic Latch
Basic latch is a feedback connection of two NOR gates or two NAND gates.
It can store one bit of information.
It can be set to 1 using the S input and reset to 0 using the R input.
SR Latch:
The SR latch is a digital circuit with two inputs s and R and two cross-coupled NOR gates or two cross-
coupled NAND gates.
SR Latch with NOR
The cross-coupled NOR gate circuit is shown in Fig. (a) This circuit and its truth table are taken from Fig(b)
In order to analyze the circuit by the transition-table method.

Truth table
S R Q Q’
0 0 No change No change
0 1 0 1
1 0 1 0
1 1 Not used Not used

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and
R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit
is present on the output marked Q.
While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state,
with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is
forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then
the Q output is forced low, and stays low when R returns to low.
Case 1:
When the S =0 and R = 1 and we will study the Q and Q ̅ output
As we are using NOR gate and its truth table is:

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

So we will use this truth table to understand the SR latch as when one of the input is 1 the output of the
NOR gate will be 0. So when S = 0 and R =1 the output Q will be 0 because the input of NOR gate G1 is
1. The output of the G1 NOR gate will be given at the input of NO gate G2 which is 0 and as the S = 0 as
both inputs of the NOR gate G2 are 0 so the output of G2 will be 1. So in Case 1 when S = 0, R = 1 then Q
= 0 and Q ̅=1 Now to check whether this one bit is store in it or not we will remove the inputs. Both the
inputs will be zero. As both the input of G2 are 0 so its output will be 1 and the output of G2 is connected
with the input of G1 as one input of the G1 is 0 while the other input is 1 so the output of the G1 will be 0.
When S = 0, R = 0 then Q = 0 and ̅ 1
Q=
Which shows that one bit is stored in it and it will work like a memory.
Case 2:

When S = 1, R = 0 then we will see that what will be the values of Q and Q ̅ output:
Now in this case the input of NOR gate G2 is 1 so when one of the input of NOR gate will be 1 its output
will be 0 and as the output of G2 is connected with the input of G1, so both the inputs of G1 will be 1 due
to which the output of the G1 will be 1. S = 1, R = 0 then the output will be Q = 1 and Q ̅=0
Now to check again whether the output is store in it we will remove the inputs such that S = 0 and R = 0
Now again one input of G2 is one so the output of G2 will be 0. As this output is connected with the G1 so
both the input of G1 will be 0 and we will get 1 at the output of G1.
S = 0, R = 0 then the output will be Q = 1 and Q ̅=0
Which shows us that it worked like a memory and the bit is stored in it.
Case 3:

When S = 1, R = 1 then we will see that what will be the values of Q and Q ̅ output:
As one of the input of both NOR gate are 1 so whatever will be the other input we will get 0 at the output.
When S = 1, R = 1 then the output will be Q = 0 and ̅ 0
Q=
Now to check whether the bit is store in it or not we will remove the inputs let us consider that the output
of the G1 gate is zero as both the input are zero of the G2 so we will obtain 1 at the output of G2.
Now consider G2 output is 0 so both inputs of G1 will be 0 and we will obtain 1 at the output. It means that
we have not change the inputs but there is change output which shows us that it is contradictory state.
So in the SR latch we will not use S =1 and R =1 state.

SR latch using NAND gate:

In SR latch using NAND gate we will replace NOR gate with the NAND gate. The inputs are interchange
in SR NOR latch we have reset in the upward gate and set in the lower gate. While in this circuit we are
applying set to the upper NAND gate and reset to the lower NAND gate and Q and Q ̅ represents the output
of the latch. The circuit will be set when the Q = 1 and the circuit will be reset when the Q = 0.

To understand the working of SR latch using NAND gate we will first draw the truth table for NAND gate
which is:
S R Q Q’
0 0 Not used Not used
0 1 1 0
1 0 0 1
1 1 No change No change

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Now we will study different cases:

Case 1:
When S = 0 and R= 0 what will be the value of Q and Q ̅. From the above table we see that whenever the
input to NAND gate is 0 we will get 1 at the output. As at G1 the input is 0 so we will obtain Q = 1 at the
output. Similarly the input to G2 is also 0 so we will get 1 at the output. But this type of output is not true
because Q and Q ̅ are complement of each other. So this state will not be used because both output cannot
be 1 and it is undesirable. This type of situation occur in SR latch using NOR gate when the S and R value
was 1.
When S = 0, R = 0 then the output will be Q = 1 and Q ̅=1
Case 2:

When S = 1, R = 0 then the output Q and Q̅ will be:

As the input of G2 is 0 the output Q ̅=1 and when this output is feed to the input of G1. So both the input
of G1 will be 1 and we will get 0 at the output.
When S = 1, R = 0 then the output will be Q = 0 and Q ̅=1.

Case 3:

When S = 0, R = 1 then the output Q and Q̅ will be:

As the input of G1 is 0 so the output Q = 1 and as this output is feed to the input of G2. So both the input
of G2 will be 1 and we will get 0 at the output.
When S = 0, R = 1 then the output will be Q = 1 and Q ̅=0.
Case 4:

When S = 1, R = 1 then the output Q and Q̅ will be:

In this case the previous state to G1 input is 0 because Q ̅=0 and S =1 so as one input is 0 the output Q will
be 1 and as this output is feed to the G2 and R=1 so both the input of G2 will be 1 and we get 0 at the output.
When S = 1, R = 1 then the output will be Q = 1 and Q ̅=0.
We will obtain the previous state and in this case the latch will act as memory by storing the previous state.

The Gated Latch

• Gated latch is a basic latch that includes input gating and a control signal .
• The latch retains its existing state when the control input is equal to0.
• Its state may be changed when the control signal is equal to 1.
• In our discussion we referred to the control input as the clock
 • We consider two types of gated latches:
➢ Gated SR latch uses the S and R inputs to set the latch to 1 or reset it to 0, respectively.
➢ Gated D latch uses the D input to force the latch into a state that has the same logic value as the D
input.

Gated S/R Latch

Gated D Latch
Flip Flops
Flip-flop is a circuit that maintains a state until directed by input to change the state. A basic flip-flop can
be constructed using four-NAND or four-NOR gates. Flip flop is popularly known as the basic digital
memory circuit. It has its two states as logic 1(High) and logic 0(low) states. A flip flop is a sequential
circuit which consists of single binary state of information or data. The digital circuit is a flip flop which
has two outputs and are of opposite states. It is also known as a Bistable Multivibrator.

Comparison between Flip flops and Latches

SlNo Flip Flops Latches

1 Flip-flop is a bistable device i.e., it has Latch is also a bistable device whose states are
two stable states that are represented as 0 also represented as 0 and 1.
and 1.
2 It checks the inputs but changes the It checks the inputs continuously and responds to
output only at times defined by the clock the changes in inputs immediately.
signal or any other control signal.
3 It is a edge triggered device. It is a level triggered device.
4 Gates like NOR, NOT, AND, NAND are These are also made up of gates.
building blocks of flip flops.
5 They are classified into asynchronous or There is no such classification in latches.
synchronous flipflops.
6 It forms the building blocks of many These can be used for the designing of sequential
sequential circuits like counters. circuits but are not generally preferred.
7 A Flip-flop always have a clock signal Latches doesn’t have a clock signal
8 Flip-flop can be built from Latches Latches can be built from gates
9 eg: D Flip-flop, JK Flip-flop Eg: SR Latch, D Latch

Types of flip-flops:
1. SR Flip Flop (Set-Reset)
2. JK Flip Flop (Jack Kilby)
3. D Flip Flop (Data/Delay)
4. T Flip Flop (Toggle)

SR FlipFlop

This simple flip-flop is basically a one bit memory bistable device that has two inputs, one which will
“SET” the device (meaning the output = “1”), and is labelled S and another which will “RESET” the device
(meaning the output = “0”), labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its original state
with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing
inputs and is commonly used in memory circuits to store a single data bit. Then the SR flip-flop actually
has three inputs, Set, Reset and its current output Q relating to it’s current state or history. The term
“Flipflop” relates to the actual operation of the device, as it can be “flipped” into one logic Set state or
“flopped” back into the opposing logic Reset state.
 Circuit Diagram of SR Flip Flop
Working of SR Flip Flop

• Case 1: Let’s say, S=0 and R=0, then output of both AND gates will be 0 and the value of
Q and Q’ will be same as their previous value, i.e, Hold state.
 • Case 2: Let’s say, S=0 and R=1, then output of both AND gates will be 1 and 0,
correspondingly the value of Q will be 0 as one of input is 1 and it is a NOR gate so it will
ultimately gives 0, hence Q gets 0 value, similarly Q’ will be 1.
• Case 3: Let’s say, S=1 and R=0, then output of both AND gates will be 0 and 1,
correspondingly the value of Q’ will be 0 as one of input to NOR gate is 1, so output will be
0 ultimately and this 0 value will go as input to upper NOR gate, and hence Q will become
1.
• Case 4: Let’s say, S=1 and R=1, then output of both AND gates will be 1 and 1 which is
invalid, as the outputs should be complement of each other.

Truth Table

Forbidden = Invalid/Not used states

Characteristic Table of SR Flip Flop

Excitation Table of SR Flip Flop

Timing Diagram of SR Flip Flop
D Flip Flop
A D type (Data or delay flip flop) has a single data input in addition to the clock input .

D flip flop is an electronic device that is known as “delay flip flop” or “data flip flop” which is used to
store single bit of data. D flip flops are synchronous or asynchronous. The clock single required for the
synchronous version of D flip flops but not for the asynchronous one. The D flip flop has two inputs,
data and clock input which controls the flip flop. When clock input is high, the data is transferred to the
output of the flip flop and when the clock input is low, the output of the flip flop is held in its previous
state.
Working of D Flip Flop
D flip flop consist of a single input D and two outputs (Q and Q’). The basic working of D Flip Flop is
as follows:
• When the clock signal is low, the flip flop holds its current state and ignores the D input.
• When the clock signal is high, the flip flop samples and stores D input.
• The value that was previously fed into the D input is reflected at the flip flop’s Q output.
• If D = 0 then Q will be 0.
• If D = 1 then Q will be 1.
• The Q’ output of the flip flop is complemented by the Q output.
• If Q = 0 then Q’ will be 1.
• If Q = 1 then Q’ will be 0.

Truth Table
Characteristic Table

Excitation Table

Timing Diagram of D Flip Flop

JK Flip Flop
One of the most useful and versatile flip flop is the JK flip flop the unique features of a JK flip flop
are:
1. If the J and K input are both at 1 and the clock pulse is applied, then the output will change state,
regardless of its previous condition.
2. If both J and K inputs are at 0 and the clock pulse is applied there will be no change in the
output.
There is no indeterminate condition, in the operation of JK flip flop i.e. it has no ambiguous state.

When J = 0 and K = 0 These J and K inputs disable the NAND gates, therefore clock pulse have no effect
on the flip flop. In other words, Q returns it last value.
When J = 0 and K = 1, The upper NAND gate is disabled the lower NAND gate is enabled if Q is 1 therefore,
flip flop will be reset (Q = 0 , =1)if not already in that state.
When J = 1 and K = 0 The lower NAND gate is disabled and the upper NAND gate is enabled if is at 1, As
a result we will be able to set the flip flop ( Q = 1, = 0) if not already set
When J = 1 and K = 1 If Q = 0 the lower NAND gate is disabled the upper NAND gate is enabled. This
will set the flip flop and hence Q will be 1.
On the other hand if Q = 1, the lower NAND gate is enabled and flip flop will be reset and hence Q will
be 0.
In other words , when J and K are both high, the clock pulses cause the JK flip flop to toggle.
Truth Table

Characteristic Table

Excitation Table

Timing Diagram of JK Flip Flop

T Flip Flop
• T flip flop or to be precise is known as Toggle Flip Flop because it can able to toggle its
output depending upon on the input.
• T here stands for Toggle.
• Toggle basically indicates that the bit will be flipped i.e., either from 1 to 0 or from 0 to 1.
• Here, a clock pulse is supplied to operate this flop, hence it is a clocked flip-flop.

Circuit Diagram

Truth Table of T Flip Flop

Characteristic Table

Excitation Table

Note: refer your DSD Notebooks for Characteristic Equations of different Flip Flops.

Asynchronous Inputs
The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because
they have an effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions.
Asynchronous inputs can set or reset the flip-flop regardless of the status of the clock signal. Typically,
they’re called preset and clear:
When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the
synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-
Q=1), regardless of any of the synchronous inputs or the clock.
Sometimes the designations “PRE” and “CLR” will be shown with inversion bars above them, to further
denote the negative logic of these inputs:

Truth Table
Preset Clear Qn
0 0 Not used
0 1 1
1 0 0
1 1 Noram Flip Flops

Race Around Conditions in JK Flip Flops

From the truth table of the JK flip-flops, it can be observed that when J = 1 and K =1, then output Qn+1 =
Qn', which means for inputs J = 1 and K = 1, the JK flip-flops acts as a toggle switch.

Let us consider the inputs J = 1 and K = 1, and the output Q = 0. After the propagation delay (let Δt) of the
flip-flops, the output of the JK flip-flops changes from 0 to 1. As we know, the output of the JK flip-flops
is connected to its inputs. Hence, the output also acts as input, and thus after the next delay (Δt), the output
will change from 1 to 0. This process will continue till the end of the applied clock signal. Thus, the output
of the JK flip-flops is uncertain. This condition of JK flip-flops is called the race-around condition.

Race-around condition in JK flip-flops is shown in Figure-2, where T is the total duration of clock pulse.
How the Race-around Condition Can Be Avoided?

The problem of the race-around condition does not exist in the flip-flops where the inputs do not change
during the presence of clock pulse. But, in the case of JK flip-flops, the inputs change during the clock
pulse due to the feedback path present between inputs and outputs. Hence, in JK flip-flops, the race around
condition is a major problem.

The problem of race-around condition and the uncertainty of output can be avoided by increasing the delay
of the flip-flops. For that, the delay of the flip-flops must be greater than the duration of the clock signal,
i.e. Δt > T. In another way, the duration of the applied clock signal (T) must be reduced to make it less than
the delay of the flip-flops (Δt).

However, the increase in the delay of the flip-flops is not a good practice because it decreases the speed of
the system. On the other hand, it is also quite difficult to decrease the duration of the clock pulse (T) beyond
the delay of the flip-flops (Δt). This is because, the delay of the JK flip-flops (Δt) is of the order of
nanoseconds.

Hence, the most practical way to solve the problem of race-around condition in JK flip-flops is to use the
JK flip-flops in the Master and Slave Mode. In the master-slave mode of JK flip-flops, two JK flip-flops
are cascaded.

Master Slave Flip Flops

In this combination of two JK flip flop, one acts as a master flip flop and the other acts as a slave flip flop.
In this master-slave flip flop, the outputs of the master JK flip flop are connected to the inputs of the slave
JK flip flop. The outputs of the slave flip flop are fed back to the inputs of the master JK flip flop.

In the master-slave JK flip flop, a NOT gate (Inverter) is also used which is connected to clock signal in a
manner that the inverted clock signal is applied to the slave flip flop.

Therefore, when clock signal to master flip flop is 0, then for slave flip flop the clock signal is 1, and if the
clock signal to master flip flop is 1, then for the slave flip flop it 0.

Operation of Master-Slave JK Flip Flop

When the clock pulse goes to high, the slave flip flop becomes inactive and the inputs J and K can control
the state of the system.

When the clock pulse goes back to low, the information is transferred from master flip flop to the slave flip
flop, and the final output of the system is obtained.
From the circuit, the master flip flop is positive level triggered and the slave flip flop is negative level
triggered. Consequently, the master flip flop responds before the slave flip flop. Now, let us discuss the
operation of the master-slave JK flip flop for different combinations of inputs J and K.

• When J = 0 and K = 0, both JK flip flops remains inactive and hence the output Q remains
unchanged. This is called Hold State of the master-slave JK flip flop.
• When J = 0 and K = 1, the output Q' of the master flip flop is high and goes to the input K of the
slave flip flop. The clock signal forces the slave flip flop to reset. Therefore, the slave flip flop has
the same output has the master flip flop, i.e., high Q' and low Q. This is called reset state of the
master-slave JK flip flop.
• When J = 1 and K = 0, the output Q of the master flip flop is high and goes to the input J of the
slave flip flop, the negative transition of the clock signal sets the slave flip flop. Hence, this is called
the set state of the master-slave JK flip flop.
• When J = 1 and K = 1, for this input combination, the master flip flop toggles on the positive
transition of the clock pulse and the slave flip flop toggles on the negative transition of the clock
pulse. Hence, the problem of the race around condition of the JK flip flop is solved.

Truth Table of Master Slave Flip Flop

Timing Diagram of Master Slave Flip Flop

Counters

Counter is a sequential circuit. A digital circuit which is used for counting pulses is known counter. Counter
is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.

Counter is a sequential circuit. A digital circuit which is used for counting pulses is known counter. Counter
is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.

Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.

Counters are of two types.

➢ Asynchronous or ripple counters.

➢ Synchronous counters

Compare Synchronous and Asynchronous Counters

SlNo Synchronous Counters Asynchronous Counters

1 In synchronous counter we use a universal In asynchronous counter main clock is only
clock that is common to all flip flops through applied to the first flip flop and then for rest
out the circuit. of flip flops the output of previous flip flop
is taken as a clock.
 2 Synchronous Counter is faster in operation as Asynchronous Counter is slower as
compared to Asynchronous Counter. compared to synchronous counter in
operation.
3 Synchronous Counter does not produce any Asynchronous Counter produces decoding
decoding errors. error.
4 Synchronous Counter is also called Parallel Asynchronous Counter is also called Serial
Counter. Counter.
5 Synchronous Counter designing as well as Asynchronous Counter designing as well as
implementation is very easy.
implementation are complex due to
increasing the number of states.
6 Synchronous Counter will operate in any Asynchronous Counter will operate only in
desired count sequence. fixed count sequence (UP/DOWN).
7 In synchronous counter, propagation delay is In asynchronous counter, there is high
less. propagation delay.

Asynchronous counter/Ripple Counter

Asynchronous counters are those counters which do not operate on simultaneous clocking. In
asynchronous counter, only the first flip-flop is externally clocked using clock pulse while the clock input
for the successive flip-flops will be the output from a previous flip-flop.

This means that only a single clock pulse is not driving all the flip-flops in the arrangement of the counter.

Asynchronous counters are also known as ripple counters and are formed by the successive combination of
trailing edge-triggered flip-flops. It is called so because the data ripples between the output of one flip-flop
to the input of the next.

Design of Asynchronous Counters

Question: Design of a two-bit ripple up-counter using negative edge triggered flip flop

Two bit ripple counter used two flip-flops. There are four possible states from 2 – bit upcounting I.e. 00,
01, 10 and 11. The counter is initially assumed to be at a state 00 where the outputs of the tow flip-flops are
noted as Q1Q0. Where Q1 forms the MSB and Q0 forms the LSB. · For the negative edge of the first clock
pulse, output of the first flip-flop FF1 toggles its state. Thus, Q1 remains at 0 and Q0 toggles to 1 and the
counter state are now read as 01. · During the next negative edge of the input clock pulse FF1 toggles and
Q0 = 0. The output Q0 being a clock signal for the second flip-flop FF2 and the present transition acts as a
negative edge for FF2 thus toggles its state Q1 = 1. The counter state is now read as 10. · For the next
negative edge of the input clock to FF1 output Q0 toggles to 1. But this transition from 0 to 1 being a
positive edge for FF2 output Q1 remains at 1. The counter state is now read as 11. · For the next negative
edge of the input clock, Q0 toggles to 0. This transition from 1 to 0 acts as a negative edge clock for FF2
and its output Q1 toggles to 0. Thus the starting state 00 is attained. Figure shown below:

Question: Two-bit ripple down-counter using negative edge triggered flip flop
A 2-bit down-counter counts in the order 0,3,2,1,0,1…….,i.e, 00,11,10,01,00,11 …..,etc. the above fig.
shows ripple down counter, using negative edge triggered J-K FFs and its timing diagram.

• For down counting, Q1‘ of FF1 is connected to the clock of Ff2. Let initially all the FF1 toggles, so, Q1
goes from a 0 to a 1 and Q1‘ goes from a 1 to a 0.
• The negative-going signal at Q1‘ is applied to the clock input of FF2, toggles Ff2 and, therefore, Q2 goes
from a 0 to a 1.so, after one clock pulse Q2=1 and Q1=1, I.e., the state of the counter is 11.
• At the negative-going edge of the second clock pulse, Q1 changes from a 1 to a 0 and Q1‘ from a 0 to a
1.
• This positive-going signal at Q1‘ does not affect FF2 and, therefore, Q2 remains at a 1. Hence , the state
of the counter after second clock pulse is 10
• At the negative going edge of the third clock pulse, FF1 toggles. So Q1, goes from a 0 to a 1 and Q1‘
from 1 to 0. This negative going signal at Q1‘ toggles FF2 and, so, Q2 changes from 1 to 0, hence, the state
of the counter after the third clock pulse is 01.
• At the negative going edge of the fourth clock pulse, FF1 toggles. So Q1, goes from a 1 to a 0 and Q1‘
from 0 to 1. . This positive going signal at Q1‘ does not affect FF2 and, so, Q2 remains at 0, hence, the state
of the counter after the fourth clock pulse is 00.

Practice Problems: Two-bit ripple up/down counter using negative edge triggered flip flop:

Question: Design of a Mod-6 asynchronous counter using T FFs:

To design a asynchronous modulus counter, first we write the sequence , then tabulate the values of reset
signal R for various states of the counter and obtain the minimal expression for R and R‘ using K-Map or
any other method. Provide a feedback such that R and R‘ resets all the FF‘s after the desired count.

A mod-6 counter has six stable states 000, 001, 010, 011, 100, and 101. When the sixth clock pulse is
applied, the counter temporarily goes to 110 state, but immediately resets to 000 because of the feedback
provided. it is ―divide by-6-counter‖, in the sense that it divides the input clock frequency by 6.it requires
three FFs, because the smallest value of n satisfying the conditionN≤2n is n=3; three FFs can have 8 possible
states, out of which only six are utilized and the remaining two states 110and 111, are invalid. If initially
the counter is in 000 state, then after the sixth clock pulse, it goes to 001, after the second clock pulse, it
goes to 010, and so on

After sixth clock pulse it goes to 000. For the design, write the truth table with present state outputs Q3, Q2
and Q1 as the variables, and reset R as the output and obtain an expression for R in terms of Q3, Q2, and
Q1that decides the feedback into be provided. From the truth table, R=Q3Q2. For active-low Reset, R‘ is
used. The reset pulse is of very short duration, of the order of nanoseconds and it is equal to the propagation
delay time of the NAND gate used. The expression for R can also be determined as follows. Therefore,
R=0 for 000 to 101, R=1 for 110, and R=X=for111 R=Q3Q2Q1‘+Q3Q2Q1=Q3Q2 The logic diagram and
timing diagram of Mod-6 counter is shown in the above fig. The truth table is as shown in below.
Question: Design of a mod-10 asynchronous counter using T-flip-flops:

A mod-10 counter is a decade counter. It also called a BCD counter or a divide-by-10 counter. It requires
four flip-flops (condition 10 ≤2n is n=4). So, there are 16 possible states, out of which ten are valid and
remaining six are invalid. The counter has ten stable state, 0000 through 1001, i.e., it counts from 0 to 9.
The initial state is 0000 and after nine clock pulses it goes to 1001. When the tenth clock pulse is applied,
the counter goes to state 1010 temporarily, but because of the feedback provided, it resets to initial state
0000. So, there will be a glitch in the waveform of Q2. The state 1010 is a temporary state for which the
reset signal R=1, R=0 for 0000 to 1001, and R=C for 1011 to 1111.

The count table and the K-Map for reset are shown in fig. from the K-Map R=Q4Q2. So, feedback is
provided from second and fourth FFs. For active –HIGH reset, Q4Q2 is applied to the clear terminal. For
active-LOW reset 4 2 is connected to all Flip-flops
Synchronous Counters

Asynchronous counters are serial counters. They are slow because each FF can change state only if all the
preceding FFs have changed their state. If the clock frequency is very high, the asynchronous counter may
skip some of the states. This problem is overcome in synchronous counters or parallel counters.
Synchronous counters are counters in which all the flip flops are triggered simultaneously by the clock
pulses Synchronous counters have a common clock pulse applied simultaneously to all flip-flops.

Design of synchronous counters:

For a systematic design of synchronous counters. The following procedure is used.

Step 1: State Diagram: draw the state diagram showing all the possible states state diagram which also be
called nth transition diagrams, is a graphical means of depicting the sequence of states through which the
counter progresses.

Step2: number of flip-flops: based on the description of the problem, determine the required number n of
the flip-flops- the smallest value of n is such that the number of states N≤2n --- and the desired counting
sequence.

Step3: choice of flip-flops excitation table: select the type of flip-flop to be used and write the excitation
table. An excitation table is a table that lists the present state (ps) , the next state(ns) and required excitations.

Step 4: Draw the excitation table of the counter.

Step 5: minimal expressions for excitations: obtain the minimal expressions for the excitations of the FF
using K-maps drawn for the excitation of the flip-flops in terms of the present states and inputs.

Step 6: logic diagram: draw a logic diagram based on the minimal expressions

Question: Design of a synchronous 3-bit up-down counter using JK flip-flops:

Design a synchronous counter using D flip flops that goes through states 0, 1, 2, 4, 0. The unused states
must always go to zero on the next clock pulse.
Solution

This synchronous counter is designed as per the following steps −

Step 1 − Number of flip flops required −

This synchronous counter has four stable states, i.e. 0 (000), 1 (001), 2 (010), 4 (100). But we require three
flip flops because it counts 4 (100) as well. Since three flip-flops can count eight states. Thus, the remaining
four states, i.e. 3 (011), 5 (101), 6 (110), and 7 (111) are unused states. As per the problem statement, the
unused states must go to 0 (000) after the next clock pulse. Therefore, there are no don’t care states.

Step 2 − Draw the state diagram −

The state diagram of the 0, 1, 2, 4, 0, … counter is drawn as shown in the following figure.

Step 3 − Chose the type of flip flop and write the excitation table −

The D flip flop is to be used and the excitation table of the counter using D flip flop is written below.
Step 4 − Derive the minimal expression −

From the excitation table, we can see that there is no minimization is possible. Hence, the expressions for
the excitations can be directly written from the excitation table itself as follows −

Step 5 − Draw the logic circuit diagram −

The logic circuit diagram of the counter 0, 1, 2, 4, 0,… as per the expressions is shown in the figure below.
Note: Refer your DSD Class Notes for more problems related to synchronous and asynchronous
counter designs.

Notes of Shift Registers already shared as a separate PDF.