SN65176B, SN75176B

DIFFERENTIAL BUS TRANSCEIVERS

SLLS101B – JULY 1985 – REVISED JUNE 1999

D Bidirectional Transceivers D OR P PACKAGE

D Meet or Exceed the Requirements of ANSI

(TOP VIEW)

Standards TIA/EIA-422-B and TIA/EIA-485-A R 1 8 VCC

and ITU Recommendations V.11 and X.27 RE 2 7 B
D Designed for Multipoint Transmission on DE 3 6 A
Long Bus Lines in Noisy Environments D 4 5 GND
D 3-State Driver and Receiver Outputs
D Individual Driver and Receiver Enables
D Wide Positive and Negative Input/Output
Bus Voltage Ranges
D Driver Output Capability . . . ± 60 mA Max
D Thermal Shutdown Protection
D Driver Positive and Negative Current
Limiting
D Receiver Input Impedance . . . 12 kΩ Min
D Receiver Input Sensitivity . . . ± 200 mV
D Receiver Input Hysteresis . . . 50 mV Typ
D Operate From Single 5-V Supply

description
The SN65176B and SN75176B differential bus transceivers are monolithic integrated circuits designed for
bidirectional data communication on multipoint bus transmission lines. They are designed for balanced
transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations
V.11 and X.27.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low
enables, respectively, that can be connected together externally to function as a direction control. The driver
differential outputs and the receiver differential inputs are connected internally to form differential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0.
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur
at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ,
an input sensitivity of ± 200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN65176B is characterized for operation from – 40°C to 105°C and the SN75176B is characterized for
operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

Function Tables

DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z

RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
A–B RE R
VID ≥ 0.2 V L H
– 0.2 V < VID < 0.2 V L ?
VID ≤ – 0.2 V L L
X H Z
Open L ?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

logic symbol† logic diagram (positive logic)

3
3 DE
DE EN1
2 4
RE EN2 D
2
RE
6 6
4 1 A 1 A
D 7 R 7 Bus
1 B B

1
R 2

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT

VCC VCC VCC

85 Ω
R(eq) NOM

16.8 kΩ 960 Ω
Input NOM NOM

960 Ω
NOM Output

GND
Driver input: R(eq) = 3 kΩ NOM Input/Output
Enable inputs: R(eq )= 8 kΩ NOM Port
R(eq) = equivalent resistor

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10 V to 15 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

recommended operating conditions

MIN TYP MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
12
Voltage at any bus terminal (separately or common mode),
mode) VI or VIC V
–7
High-level input voltage, VIH D, DE, and RE 2 V
Low-level input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, VID (see Note 3) ± 12 V
Driver – 60 mA
High level output current,
High-level current IOH
Receiver – 400 µA
Driver 60
Low level output current,
Low-level current IOL mA
Receiver 8
SN65176B – 40 105
free air temperature,
Operating free-air temperature TA °C
SN75176B 0 70
NOTE 3: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
VIK Input clamp voltage II = – 18 mA – 1.5 V
VO Output voltage IO = 0 0 6 V
|VOD1| Differential output voltage IO = 0 1.5 3.6 6 V
1/2 VOD1
RL = 100 Ω, See Figure 1 V
|VOD2| g
Differential output voltage or 2¶
RL = 54 Ω, See Figure 1 1.5 2.5 5 V
VOD3 Differential output voltage See Note 4 1.5 5 V
Change
g in magnitude
g of differential output
∆|VOD| ± 0.2
02 V
voltage§
+3
VOC Common mode output voltage
Common-mode RL = 54 Ω or 100 Ω
Ω, See Figure 1 V
–1
Change
g in magnitude
g of common-mode
∆|VOC| ± 0.2
02 V
output voltage§
Output disabled,, VO = 12 V 1
IO Output current mA
See Note 5 VO = – 7 V – 0.8
IIH High-level input current VI = 2.4 V 20 µA
IIL Low-level input current VI = 0.4 V – 400 µA
VO = – 7 V – 250
VO = 0 150
IOS Short circuit output current
Short-circuit mA
VO = VCC 250
VO = 12 V 250
Outputs enabled 42 70
ICC Supply current (total package) No load mA
Outputs disabled 26 35
† The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡ All typical values are at VCC = 5 V and TA = 25°C.
§ ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
¶ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
NOTES: 4. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
5. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does
not apply for a combined driver and receiver terminal.

switching characteristics, VCC = 5 V, RL = 110 kΩ, TA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential-output delay time 15 22 ns
RL = 54 Ω
Ω, See Figure 3
tt(OD) Differential-output transition time 20 30 ns
tPZH Output enable time to high level See Figure 4 85 120 ns
tPZL Output enable time to low level See Figure 5 40 60 ns
tPHZ Output disable time from high level See Figure 4 150 250 ns
tPLZ Output disable time from low level See Figure 5 20 30 ns

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 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A
VO Voa, Vob Voa, Vob
|VOD1| Vo Vo
|VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
(
Vt (Test Termination
|VOD3|
Measurement 2)
∆|VOD| | |Vt| – |Vt| | | |Vt – |Vt| |
VOC |Vos| |Vos|
∆|VOC| |Vos – Vos| |Vos – Vos|
IOS |Isa|, |Isb|
IO |Ixa|, |Ixb| Iia, Iib

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIT + Positive-going input threshold voltage VO = 2.7 V, IO = – 0.4 mA 0.2 V
VIT – Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA – 0.2‡ V
Vhys Input hysteresis voltage (VIT + – VIT –) 50 mV
VIK Enable Input clamp voltage II = – 18 mA – 1.5 V
VID = 200 mV,, IOH = – 400 µ
µA,,
VOH High level output voltage
High-level 27
2.7 V
See Figure 2
VID = – 200 mV,, IOL = 8 mA,,
VOL Low level output voltage
Low-level 0 45
0.45 V
See Figure 2
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ± 20 µA
Other input = 0 V,, VI = 12 V 1
II Line input current mA
See Note 6 VI = – 7 V – 0.8
IIH High-level enable input current VIH = 2.7 V 20 µA
IIL Low-level enable input current VIL = 0.4 V – 100 µA
rI Input resistance VI = 12 V 12 kΩ
IOS Short-circuit output current – 15 – 85 mA
Outputs enabled 42 55
ICC Supply current (total package) No load mA
Outputs disabled 26 35
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 6: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.

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SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 21 35 ns
VID = 0 to 3 V
V, See Figure 6
tPHL Propagation delay time, high- to low-level output 23 35 ns
tPZH Output enable time to high level 10 20 ns
See Figure 7
tPZL Output enable time to low level 12 20 ns
tPHZ Output disable time from high level 20 35 ns
See Figure 7
tPLZ Output disable time from low level 17 25 ns

PARAMETER MEASUREMENT INFORMATION

RL VID
2 VOH
VOD2
+IOL – IOH
RL VOL
VOC
2

Figure 1. Driver VOD and VOC Figure 2. Receiver VOH and VOL
3V
Input 1.5 V 1.5 V
CL = 50 pF 0V
(see Note A)
RL = 54 Ω
Generator td(OD) td(OD)
50 Ω Output
(see Note B)
90% ≈ 2.5 V
Output 50% 50%
3V 10% 10%
≈ – 2.5 V
tt(OD) tt(OD)
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 3. Driver Test Circuit and Voltage Waveforms

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 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

Output 3V
S1 Input 1.5 V 1.5 V
0 V or 3 V 0V
tPZH 0.5 V
CL = 50 pF RL = 110 Ω VOH
Generator (see Note A)
(see Note B) 50 Ω Output 2.3 V
tPHZ Voff ≈ 0 V

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 4. Driver Test Circuit and Voltage Waveforms

5V
3V
Input 1.5 V 1.5 V
RL = 110 Ω
S1 0V
Output
3 V or 0 V
tPZL tPLZ
CL = 50 pF
(see Note A) 5V
Generator
50 Ω 2.3 V 0.5 V
(see Note B) Output
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 5. Driver Test Circuit and Voltage Waveforms

3V
Output Input 1.5 V 1.5 V
Generator
(see Note B) 51 Ω
0V
1.5 V
CL = 15 pF tPLH tPHL
(see Note A) VOH
0V
Output 1.3 V 1.3 V
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 6. Receiver Test Circuit and Voltage Waveforms

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SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

PARAMETER MEASUREMENT INFORMATION

1.5 V S1

2 kΩ S2
–1.5 V 5V

CL = 15 pF 5 kΩ 1N916 or Equivalent
(see Note A)

Generator
(see Note B) 50 Ω

S3

TEST CIRCUIT

3V 3V
Input 1.5 V Input 1.5 V
S1 to 1.5 V S1 to –1.5 V
0V S2 Open 0V S2 Closed
tPZH S3 Closed S3 Open
tPZL
VOH
1.5 V ≈ 4.5 V
Output
Output 1.5 V
0V
VOL

3V 3V
S1 to 1.5 V S1 to – 1.5 V
Input 1.5 V S2 Closed Input 1.5 V S2 Closed
S3 Closed S3 Closed
0V 0V
tPHZ
tPLZ
VOH ≈ 1.3 V
0.5 V
Output Output 0.5 V
≈ 1.3 V VOL

VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 7. Receiver Test Circuit and Voltage Waveforms

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 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

TYPICAL CHARACTERISTICS

DRIVER DRIVER
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
5 5
VCC = 5 V VCC = 5 V
4.5 TA = 25°C 4.5 TA = 25°C
VOH – High-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

4 4

3.5 3.5

3 3

2.5 2.5

2 2

1.5 1.5
VOH

1 1

0.5 0.5

0 0
0 – 20 – 40 – 60 – 80 – 100 – 120 0 20 40 60 80 100 120
IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA

Figure 8 Figure 9
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
VCC = 5 V
3.5 TA = 25°C
VOD – Differential Output Voltage – V

2.5

1.5

1
VOD

0.5

0
0 10 20 30 40 50 60 70 80 90 100
IO – Output Current – mA

Figure 10

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SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

TYPICAL CHARACTERISTICS
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER vs
HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE†
vs
HIGH-LEVEL OUTPUT CURRENT 5
VCC = 5 V
5 4.5
VID = 200 mV

VOH – High-Level Output Voltage – V

VID = 0.2 V IOH = – 440 µA
4.5 4
TA = 25°C
VOH – High-Level Output Voltage – V

4 3.5

3.5 3

3 2.5

2.5 2
VCC = 5.25 V
2 VCC = 5 V 1.5

1.5 1
VCC = 4.75 V
VOH
1 0.5
VOH

0.5 0
– 40 – 20 0 20 40 60 80 100 120
0 TA – Free-Air Temperature – °C
0 – 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40 – 45 – 50
IOH – High-Level Output Current – mA † Only the 0°C to 70°C portion of the curve applies to the
SN75176B.
Figure 11 Figure 12
RECEIVER RECEIVER
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
LOW-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE
0.6 0.6
VCC = 5 V VCC = 5 V
TA = 25°C VID = – 200 mV
VOL – Low-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

0.5 0.5 IOL = 8 mA

0.4 0.4

0.3 0.3

0.2 0.2
VOL

VOL

0.1 0.1

0 0
0 5 10 15 20 25 30 – 40 – 20 0 20 40 60 80 100 120
IOL – Low-Level Output Current – mA TA – Free-Air Temperature – °C

Figure 13 Figure 14

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 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

TYPICAL CHARACTERISTICS

RECEIVER RECEIVER
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
ENABLE VOLTAGE ENABLE VOLTAGE
5 6
VID = 0.2 V VID = – 0.2 V
VCC = 5.25 V
Load = 8 kΩ to GND Load = 1 kΩ to VCC
TA = 25°C 5 TA = 25°C
4 VCC = 5.25 V
VCC = 4.75 V

VO – Output Voltage – V
VCC = 5 V
VO – Output Voltage – V

4
VCC = 5 V
3 VCC = 4.75 V

2
2

VO
VO

1
1

0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
VI – Enable Voltage – V VI – Enable Voltage – V

Figure 15 Figure 16

APPLICATION INFORMATION
SN65176B SN65176B
SN75176B SN75176B

RT RT

Up to 32
Transceivers

NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.

Figure 17. Typical Application Circuit

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Copyright  1999, Texas Instruments Incorporated