2013 6th International Congress on Image and Signal Processing (CISP 2013)

Design and Implementation of a 1024-point

High-speed FFT Processor Based on the FPGA
Sheng Zhou, Xiaochun Wang, Jianjun Ji, Yanqun Wang
Institute of Biomedical Engineering
Chinese Academy of Medical Sciences
Tianjin, China

Abstract: To design a Fast Fourier Transform (FFT) processor to Combining the advantages of flexible programming in the
meet the needs for high-speed and real-time signal processing. A software and high-speed by the dedicated integrated circuit,
1024-point, 32-bit, fixed, complex FFT processor is designed based FPGA is suitable for the FFT algorithm and has superiorities in
on a field programmable gate array (FPGA) by using the radix-2 performance, costing and power consumption. It is realized by
decimation in frequency (DIF) algorithm and the pipeline the related EDA (Electronic Design Automation) software and
structure in the butterfly module and the ping-pone operation in hardware description language. In modern signal processing,
data storage unit. When the primary clock is 100 MHz, the the requirements of high-speed and high-reliability are
1024-point FFT calculation takes about 62.95 us. The processor is becoming a hot research point. Furthermore, many researchers
fast enough for processing the high-speed and real time signals.
are researching in combining the real time requirement of FFT
The result provides reference values that theoretical study of the
FFT algorithm can be applied into the adaptive dynamic filter of
with the flexibility design by the FPGA, realizing the optimal
an ultrasonic diagnostic system and an ultrasonic Doppler flow configuration of the parallel algorithm and hardware structure,
measurement system. and improving the FFT processing speed.
According to the actual requirements, this paper presents a
Key words— field programmable gate array; 1024-point FFT; method which realizes the FFT operation based on the FPGA.
Butterfly; Ping-pong operation; Verilog HDL The FFT synthesis and simulation are realized on the Quartus
II 6.0 and Modlesim 6.0 software. Although at last we only
I. INTRODUCTION
realize the 1024-point fixed-point arithmetic, this method can
FFT (Fast Fourier Transform Algorithm) is a fast algorithm be also applied to 2M (M=2，3…) points arithmetic.
of DFT (Discrete Fourier Transformation). A real time
processing of digital signal was becomes realization when the II. THE BASIC PRINCIPLE OF THE RADIX-2-DIF FFT
FFT was appeared, and which was used in many domains such ARITHMETIC
as the ultrasound, the radar and the communication. In the The FFT arithmetic can be divided into two types basically,
process of ultrasonic echo signals processing, the FFT is a which is the decimation-in-time (DIT) and the
most important part. Its computing speed and accuracy are decimation-in-frequency (DIF). This radix-2-DIF is adopted in
directly influence the performance of the system. FFT is a this paper. The discrete Fourier transformation of the
centre part of the Doppler blood flow spectrum analysis, and is sequences x(n) is written as,
the most commonly used signal processing method in the
Doppler imaging system. −j
2π
N −1 WN = e N

Although the Altera and Xilinix have developed the X ( k ) = ∑ x( n)WNkn k, n = 0,1,2..., N −1
n=0
corresponding FFT IP (Intellectual Property) core, the price of
them is so high that they are not used extensively. As a result, In which N is the sequence length. Then the x(n) is divided
many researchers now design the FFT processors which are into two parts, which is include of the odd number part and the
more suitable for themselves. In the engineering realization of even number part. By this method, the N/2-point DFT can be
FFT, the most generally hardware realization methods are continued to divided into the N/4-point DFT, the N/8-point
included of DSP (Digital Signal Processor), FFT dedicated DFT and lastly obtained the 2-point DFT [1]. Figure 1 the
chip and FPGA [1]. The FFT operation in DSP not only frequency decimation operation diagram where N=8.
occupies much more time, but also reduces the throughput rate
of the whole system, and furthermore, the realization
flexibility of the DSP software can not make well. By using
dedicated FFT processing chip, the speed can achieve the
requirement, but has bad expansibility. With the rapid
development of the FPGA recent years, and comparing with
the DSP technique, the FPGA is suitable for the high-speed
signal processing system owing to its parallel signal processing
architecture.

Support by the National Science and Technology Pillar Program (2012BAI13B02), the
Fundamental Research Funds for the Central Universities and the PUMC Youth Fund

978-1-4799-2764-7/13/$31.00 ©2013 IEEE 1112

 Fig.3 The basic butterfly element

As shown in figure 3, the butterfly processing element is

composed of a complex adder, a complex subtractor and a
twiddle factor complex multiplier [3]. The twiddle factor
multiplier is implemented by real number multiplication with 4
times and addition or subtraction with 2 times. Let the input
data and twiddle factor are:
Fig1.The operation diagram of DIF-FFT where N=8
A = Are + jAim, B = Bre + jBim, W Nr = Wre + jWim
III. DESIGN OF THE HARDWARE AND
IMPLEMENTATION OF THE FFT ARITHMETIC Figure 4 is the hardware implementation diagram based on
the FPGA.
A. The structure of the FFT processor
The whole structure of FFT processor is divided into
several modules reasonably. Each module is worked parallel
by the sequential control unit. The whole implementation
diagram is shown in figure 2 which is included of a butterfly
processing unit, a data storage RAM and a ROM unit, a
address generating unit and a sequential control unit [2]. The
design of the butterfly processing unit and the address
generation unit is important for the design of fixed-point FFT.
The implementation methods of each unit are introduced in the
following section.

Fig.4 The hardware implementation diagram of butterfly element

The adder, the subtractor and the multiplier in this butterfly

processing element are generated by the Megafunction in
Quartus II. The operation of the butterfly arithmetic is in
synchronization and needs 4 clock cycles. To avoid the data
overflow, the output results are divided by the number 2 [4].
For the division operation consumes much more resources, in
this design, we adopt the shifting method of binary numbers to
implement the division operation. At the same time, the Xm(k)
is delayed by a group of registers for data synchronization. The
output result of the multiply-accumulate operation is remained
16-bit integer output [5-6].
C. The data storage ROM/RAM
Fig.2 The whole system diagram
The data of the twiddle factor ROM are designed by the
B. The butterfly processing unit MATLAB. The real part and imaginary part of the input data
A and B are all 16-bit signed binary data. The twiddle factor
The Butterfly processing unit is the core of the FFT cos(2k∏ ／N) and sin(2k∏／ N) are quantified to 16-bit
arithmetic. The butterfly element is shown in figure 3. It is signed binary data and saved to a ROM. The operation result is
needed ten steps processing for 1024-point data, and each step divided by 16’b0111111111111111 which is multiplied when
is composed of N/2 butterfly processing elements. The quantization.
operation of each butterfly processing element is as follows,
The data storage RAM is used to store input data and to
X m ( k ) = X m −1 ( k ) + X m −1 ( j )
buffer intermediate operation results. The input/output data are
X m ( j ) = [ X m −1 (k ) − X m −1 ( j )]W Nr needed to write or read respectively form the RAM in each
butterfly operation. Before the next transformation, the last
result should be written to the RAM where read the data from.
In order to achieve high speed FFT processing, in the FFT
module, we use two RAM storage blocks to compose the

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typical Ping-pong operation module [7-8].RAM 1 and RAM 2 operation addresses generating procedure for FFT is
are used for storing the intermediate data in which one RAM is completed.
used as a reading block and the other is used as a writing
block. In the first step of FFT, the data reading from RAM 1 The logic parts of the addresses generator is composed of
are saved into RAM 2 after the butterfly operation element. upper and lower notes and the address logics of twiddle factors
The second step is just the opposite. In the same way until the which are A_address, B_address and rom_address
tenth step is implemented. Figure 5 is the Ping-pong operation respectively.
diagram. E. The sequential control unit
The RAM we adopted is using True DualPort Memory The sequential control unit is used to generate control
module. The reading and writing operations with random signals for each model. Its main task is exactly to coordinate
addresses can be implemented under independent working work and consequently accomplish the whole procedure of the
clock in each side. It is meaning that, the data can be read out FFT operation. In according to many processing elements
from two RAMs, for the butterfly operation and the results can related to FFT operation and the complex controlling, in this
write into two RAMs in the same time. This method greatly unit, we adopt the modeling of Mealy limited state machine.
reduce the writing and reading cycle compared to single port
RAM. The function of the sequential control unit is described as:
first, enter the initial state, and when the external reset signal is
For using the dual-port RAM, when one storage element is valid, all of the functional modules are reset; when the enable
used for data reading output, this storage element can save the signal is in valid, the inputting control unit is in inputting state
data from the upper level. The pipeline structure is suitable for and generate the enable signal to receive the data which is
this FFT structure, and can realize the continuous operations to intend to operate; the following is the butterfly operation state;
signal samples. The intermediate data are saved to a dual-port when the fix-point operation is completed, enter the output
RAM. Then the two complex data from the RAM are split to control state and send out the output enable signal; when the
four real data and then are inputted to the butterfly operation intermediate operation data are read from the RAM, the
element. After the butterfly operation, the data are input into completed signal is generated if all of the data is outputted and
the selecting buffer to constitute two complex data and lastly changed to initial state; the following is the delay operation
to output. The serial-to-parallel and the parallel-to-serial are and prepare for the next step operation.
realized [4].
IV. THE WAVEFORM SIMULATION VERIFICATION
AND THE SEQUENTIAL ANALYSIS
Each functional module is analyzed and realized above
mentioned. The FFT processor is synthesized on the top
module as figure 6.

Fig.5 The ping-pong operation diagram

D. The addresses generator

The addresses generator generate three group addresses,
which is included of the reading addresses of RAM and ROM
for butterfly operation data, the writing addresses of RAM for
butterfly operation results and the lastly output addresses of
FFT operation results. In actually, the reading addresses are the
delay of the writing addresses. The delay time is the adder of
the butterfly operation time and the parallel-to-serial time. The
reading addresses are included of the real part and the
Fig.6 The top module of the FFT
imaginary part, as well as the twiddle factor addresses for
butterfly operation. The addresses generator is composed of The system is developed on the software QuartusⅡ6.0
the counter and some logic parts [9-10]. offered by ALTERA. The chip we selected is EP2C35F484C8.
The addresses generation is related to the step counter and Figure 7 is the compiling result.
the butterfly operation counter in each step, so we design two
counters which are respectively used for the steps counting and
the butterfly operation counting. The shifter registers are used
to count the steps and the butterfly operation counter is in the
general method. When the butterfly operation counter is full,
there is a pulse for the steps counter, and the shifter is worked.
If there is no derive pulse, the steps counter is remain
unchanged. If the shifter work is finished, the butterfly

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 15%. The saving use of logic elements meets the system
requirement of rational utilization of FPGA resource.
In order to verify the accuracy of the system designed, the
simulation result is simulated digitally in Modelsim6.0 [11], as
seen in figure 8. The output is in valid when the signal rdv is
high. When the clock frequency is 100 MHz, it needed 62.95
us to finish a 1024-point 32-bit fixed point complex FFT
transformation.
The verification of algorithm is finished by the Matlab 7.0.
The input signal is x(t)=20000*sin(2*∏*10*t). The output
data from the Modelsim 6.0 are saved in .txt document and
imported into the MATLAB. Then the data format is changed
to the signed decimal from the binary complementary code.
The comparison between the simulation data by the Modelsim
Fig.7 The compiling result by the QuartusⅡ6.0
and the FFT functional computational results by the MATLAB
From the figure 7, we can see that the total logic elements is seen as figure 9.
are only used 2% and the total memory bits are only occupied

Fig.8 The simulation result by the Modelsim

5
x 10
7 real x 10 imag
1 5

0.5

0
y

0
y

-0.5

-1 -5
0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500
f(Hz) f(Hz)
4 4
x 10 modelsim real x 10 modelsim imag
1 2

0.5 1

0 0
b
a

-0.5 -1

-1 -2
0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500
f(Hz) f(Hz)

Fig.9 The comparing between the FFT processor result and the FFT functional computational result

Form figure 9, we can see that the FFT processor results It is seen that the deviation between the two platforms is
and the computational results by the MATLAB are basically very small. So the fixed point FFT processor based on the
the same. The validity of the algorithm is verified. The FPGA get a good application which is in the allowable error
statistical error analysis between 1024-point simulation results range.
by the Modelsim and the testing data are worked on the
MATLAB platform [12-13]. The total average relative error is: V. CONCLUSIONS
Compared to the theoretical values, the errors from the
1024 A(i ) − B(i ) simulation results are quite small. Using the abundant logic
∑
i =1 B(i ) resources in FPGA is the superiority of this system. The
≈ 0.0062 = 0.62% pipeline architecture and the Ping-pong operation are based on
1024
the embedded M4K logic elements and are finally finished the

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high-speed fixed-point FFT operation. Under the clock of 100
MHz, the 1024-point FFT operation is only used 62.95 us
which is reached the high processing requirement. With the
improving of the FPGA resources, the superiority of using this
structure to realize the FFT operation is more and more
significantly. Furthermore, by this structure, it is easy to
expand the FFT operation by increasing the depth of RAM and
ROM, changing the twiddle factor table and adding the times
of the ping-pong operation.
In the design of dynamic filter in the traditional ultrasonic
imaging, when to determine the center frequency, it is only
taken into consideration that the frequency is attenuated with
the depth increased and neglected the nonlinear relationship
between depth and frequency. The assumption of fixed
attenuation coefficient and the frequency is changed linearly
from near field to far field leads to the differences between the
frequency characteristics of real echo signals and the
theoretical model. Consequently, this way weakens the
matched effect of dynamic filter. The fast Fourier transform
processor designed in this paper can analysis the frequency
characteristics of each small section of the echoes in real time
and determine the dynamic filter whose coefficients are
according to the center frequency. By this way, it can attain the
optimal effect of the matched filter and raise the
signal-to-noise ratio. This self-adaptive dynamic filter is very
useful for digital ultrasonography and the ultrasonic Doppler
flow measurement system.

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