Single-Channel, 1.

25-GS/s, 6-bit, Loop-Unrolled

Asynchronous SAR-ADC in 40nm-CMOS
Tao Jiang1, Wing Liu2, Freeman Y. Zhong2, Charlie Zhong2, Patrick Y. Chiang1
1
Oregon State University, Corvallis, OR 97331
2
LSI Corporation, Milpitas, CA 95035

Abstract-A single channel, loop-unrolled, asynchronous successive sent into a digital SAR logic first before being sent to the
approximation (SAR) ADC fabricated in 40nm CMOS is capacitive DAC for settling the charge sharing before the next
presented. Compared with a conventional SAR structure that bit comparison. As pointed out in [2], this logic gate delay
exhibits significant delay in the digital feedback logic, the can occupy up to 75% of the cycle time, thereby greatly
proposed 6b SAR-ADC employs a different comparator for each
bit of conversion, with an asynchronous ripple clock generated
limiting any possibility for future speed improvements.
after each quantization. With the sample rate limited only by the
six delays of the C-DAC settling and comparator quantizations, +
the 40nm-CMOS SAR-ADC achieves a peak SNDR of 32.9dB Capacitive-network
and 30.5dB at 1GS/s and 1.25GS/s, respectively, consuming (DAC)
5.28mW and 6.08mW in a core area less than 170um x 85um. _

I. INTRODUCTION synchronous or
asynchronous clock
High-speed, medium-resolution, low-power ADCs have a
wide range of applications in communication systems such as Digital SAR logic
UWB, mm-wave, serial link transceivers, Ethernet, and digital
oscilloscope [1-5]. Fig. 1. Conventional SAR ADC structure.
With continued technology scaling, the Successive
Approximation ADC (SAR-ADC) has quickly improved its B. Proposed Work: Loop-Unrolled, Asynchronous SAR-ADC
sample rate to 100-1000 MHz, surpassing its flash counterpart As shown in Fig. 2, the proposed SAR-ADC architecture
due to its excellent energy efficiency. However, for here features two methods to reduce the conversion time. First,
applications requiring sampling rate exceeding tens of giga- an asynchronous structure [1, 4] takes advantage of the faster
hertz, a tradeoff must be made between a large number of comparison cycles, as there will only be one conversion where
cascaded channels of time-interleaved, lower-speed sub-ADCs, the input level will occur below 1/2 LSB due to the SAR
or a smaller number of channels with higher-speed sub-ADCs. algorithm. With the global clock cks sampling the signal and
While lower-speed SAR-ADCs [6] typically achieve better starting the quantization in the MSB cell, internal comparisons
FoM values than their higher-speed counterpart, time- from MSB to LSB will be triggered like dominoes from the
interleaving a large number of sub-ADC requires significant outputs of the ready logic.
design effort and complexity, such as the multi-phase clock
generation/distribution, as well as schemes for compensating
the offset, gain and phase skew mismatches between the sub-
channels.
On the other hand, achieving a high sampling rate over
1GS/s with 6b conversion is extremely challenging, even with
continued CMOS scaling. Most previously reported 6b SAR-
ADCs over 1GS/s time-interleave more than two channels
[2][4], with the state-of-art fastest single-channel SAR-ADC
resolving 5b at 800MS/s [3]. Therefore, a fundamental
architectural innovation needs to be developed in order to
improve the sample rate of these feedback-limited SAR-ADCs.

A. Conventional SAR-ADC Approach

Fig. 1 shows the conventional SAR ADC architecture. In
this structure, the most critical bottleneck to increased
sampling rate is the digital logic delay during operation of the
successive approximation algorithm. After the comparator
quantizes and generates an output, the digital result must be
Fig. 2. Proposed loop-unrolled SAR architecture.

978-1-4244-5760-1/10/$26.00 ©2010 IEEE

 Second, different from the conventional SAR architecture Unlike the conventional structure where only one
that uses only one comparator followed by a SAR digital logic comparator is used, each of the six comparators will exhibit a
for determining the conversion bit, the new architecture uses different mismatch such that the offset is no longer a
N comparators for a N-bit conversion, storing the comparison systematic error that can be subtracted during the post signal
result of each bit within the digital output of each comparator. processing. Therefore, offset cancellation of each comparator
In this way, no additional digital logic is needed to perform is performed where an off-die offset cancellation circuit
the SAR process, and the comparison result is directly fed composed of two sets of 7-bit binary current sources is used.
back to the capacitor network without any logic gate delay. Monte Carlo simulations show a reduction in 3s offset below
One additional benefit of the proposed architecture is that 0.5LSB (15mV).
the resolution of the SAR ADC can be easily programmed by
disabling the last LSB cell, using ck0 as the reset signal. This CK CK CK CK
programmability may be useful for applications where higher
sampling rate is preferred over precision. OUTN OUTP
In the next several sections, detailed circuits will be
introduced along with the measurement results, followed by
the conclusion.
CK
II. CIRCUIT IMPLEMENTATION
A. Capacitive DAC and bootstrapped switch INP INN
A normal capacitive DAC is employed, except for a minor
change that the capacitor directly connected to ground is made
17Cu rather than Cu. In this way, the reference voltage is made CK

1.5 times of full scale, and will accelerate the settling speed of
DAC. Considering the parasitics contributed by comparators’ Fig. 4. Comparator design with current steering offset cancellation circuit.
ΔC, the real reference voltage should be trimmed to be
Vref = 1.5 ⋅ VF ⋅ (1 + ΔC 48Cu ) (1) C. Ready signal logic
Bootstrapped switches [7] are employed (Fig. 3) in the As can be seen from Fig. 2, each of the six comparators is
sampling circuit in order to achieve both smaller on-resistance followed by a logic circuit that determines if the current
and minimal signal-dependent sampling distortion. The quantization is complete, followed by generation of an
circuit is carefully designed so that the voltages between all asynchronous clock to trigger the next quantization. The
transistor terminals are below 1V. comparator in the first MSB cell is triggered by the falling
edge of the sampling clock, while the other five comparators
are triggered by the ready signals from each preceding cell.
The comparator in the LSB cell generates a ready signal that is
used to reset all of the six comparators, shorting the bottom
plates of the capacitors in the capacitor network to ground
during the next sampling phase.

Fig. 3. Bootstrapped switch used in capacitive DAC.

B. Comparator design and offset cancellation scheme

Six simple StrongARM comparators (Fig. 4) are used for
the entire 6-bit quantization. Clocked by the ready signal from
the preceding conversion, each comparator evaluates the input
signal and sends its output directly to the capacitive DAC,
maintaining its digital output until it is reset at the end of the
6b conversion. Because each comparator quantizes only once Fig. 5. Ready signal generated logic and DPL XNOR circuit.
per clock period, the total power consumption of the six
comparators does not exceed that of a conventional Since the comparator is precharged to supply every reset
architecture where one comparator evaluates six times every interval, its output can only be changed from “HH” to “HL” or
conversion period.
“LH”. In a time-constrained system such as a high-speed ADC, III. MEASUREMENT RESULTS
a NAND gate for the ready logic might be preferred due to its The SAR ADC is fabricated in a 1V, 40nm CMOS process,
single stage delay. However, the NAND must be carefully with the die shown in Fig. 7. The total active area is only
designed in order to prevent it from making a wrong decision 170μm by 85μm, with a total die size of 1.8mm by 1.5mm.
– for example, if the comparator meets metastability and its The measurements are performed with different supplies
differential outputs result in “LL”. On the other hand, while a across varying sampling rates in order to explore the chip’s
XOR gate is more robust as it will not evaluate with the “LL” maximum performance. Least mean square (LMS) calibration
situation, it suffers from relatively long delay. DPL (double [1] is performed by injecting a slow ramp signal into the
pass-transistor logic) circuit is employed here to reduce the converter, using the output code to determine the bit weights
gate delay while always making the correct decision. The that best correspond to the known input. Because all six
final ready logic is designed according to De Morgan’s law comparators connect to the output of the capacitive DAC, the
and shown in Fig. 5. After the first five MSB cells, each ready large gate capacitances all contribute as parasitic, making the
signals will be reset by the ready signal of the final LSB cell, distortion and non-linearity of this ADC larger than a
signifying that 6b conversion is complete and the comparators conventional structure. LMS calibration helps improve the
need to be precharged. performance considerably, as observed in Fig. 8, where the
SNDR is improved by 2.7dB at 1GS/s sampling rate.
D. Metastability detector
Metastability will occur when the input signal level is so
small that the comparator takes an excessive amount of time to
complete a quantization. The probability for encountering digital logic
metastability is even greater for high sample rates, since less comp comp
time is available for the quantizer’s positive feedback to MSB-2 MSB-3
regenerate to full digital level. Hence, a metastability detector comp comp
is designed to detect its occurrence, stop the current MSB-1 LSB+1
conversion, and force the remaining quantizers’ outputs to a comp comp
digital “1” followed by all digital “0”s. MSB LSB
In the circuit shown in Fig. 6, a delay signal starting from
the input clock ck_in is deliberately generated, with its delay differential
time comparable with that of the delay path through the capacitive
comparator and the ready logic. Signals ck_out and ck_delay network
are sensed by the D flip-flop as the data and clock, and the
bootstrap
output /Q of the D flip-flop is used as a local reset signal that switch
is responsible for stopping the current conversion and setting 85μm
forced values for the remaining bits. If the comparator is not
metastable and generates an asynchronous clock, the length of Fig. 7. Chip die photo and core circuit layout.
the delay in the comparator-ready-logic path will be shorter.
Then the signal ck_out will toggle to “1” when the sampling 0
phase of the D flip-flop ck_delay comes and the conversion 100.219727MHz@1GS/s, SNDR=32.3dB,
-20 w/ LMS calibration
will not be interrupted. In contrast, if the comparator becomes
metastable, the signal lclrst will toggle to “1” and the -40
dBFS (dB)

conversion will be stopped.

-60

-80

-100

-120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
100.219727MHz@1GS/s, SNDR=29.6dB,
-20 w/o LMS calibration

-40
dBFS (dB)

-60

-80

-100

-120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (Fs)

Fig. 6. Metastability detection circuit and its working process. Fig. 8. ADC output spectra with and without LMS calibration.
 0
20.1416MHz@1GS/s, SNDR=32.9dB
contribute to the SNDR losses at low frequency, the ability to
-20 reduce to 5b conversion enables operation well above 1.5GHz
at Vdd=1.1V.
-40
Measurement results are summarized in Table I, along with
dBFS (dB)

-60 a performance comparison versus recent SAR-ADC designs.

-80
TABLE I
-100 COMPARISON WITH PREVIOUS WORKS
[1] [2] [3] [4] This work
-120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Technology
130 130 65 65 40
(nm)
0
449.0967MHz@1GS/s, SNDR=27.7dB Area
0.12 0.09 0.018 0.11 0.014
-20 (mm2)
Resolution 5 or 6
6 6 5 6
-40 (bit) Programmable
dBFS (dB)

Channel # 2 2 1 2 1
-60
Sample rate
0.6 1.25 0.8 1 1 1.25 1.25 1.33
-80
(GS/s)
Peak SNDR
34 34.9 28.2 31.5 32.9 30.5 31.8 31.3
-100 (dB)
FoM
-120 220 - 116 210 148 178 183 188
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 (fJ/conv)
Frequency (Fs) Supply
1.2 1.2 1 - 1 1 1.1 1.1
(V)
Fig. 9. ADC output spectra with different input frequencies with 1GS/s rate. Power
5.3 32 1.97 6.7 5.28 6.08 7.26 7.52
(mW)
35
1V, 1GS/s, 6bit
peak SNDR (dB)

1V, 1.25GS/s, 6bit

30 IV. CONCLUSION

25
A novel loop-unrolled SAR architecture is proposed. With
the comparator outputs directly fed back to the capacitive
20 DAC, the digital FSM logic delay is eliminated, thereby
0 100 200 300 400 500 600 700 800
greatly increasing the sample rate. Fabricated in a 40nm
35 CMOS process, the ADC achieves a sampling rate over
1.1V, 1.25GS/s, 6bit
1.25GS/s for a single channel, 56% faster than the previous
peak SNDR (dB)

1.1V, 1.33GS/s, 6bit

30 fastest single-channel SAR-ADC [3].
25

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20
0 100 200 300 400 500 600 700 800
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comparators, digital logic and internal clock driver, and the
capacitive DAC, respectively. The ADC output spectra with
different input frequencies is shown in Fig. 9, indicating a
peak SNDR of 32.9dB, resulting in a general FoM of
148fJ/conversion-step. When the sampling rate is increased to
1.25GS/s, the peak SNDR is 30.5dB, with a total power
consumption is 6.08mW. While capacitive parasitics