AS703xxB UG001014 1-00

Product
Document
Published by
ams OSRAM Group
User Guide
UG001014
AS7030B/AS7038GB/
AS7038RB
Evaluation Kit
User Guide
v1-00 • 2021-May-06
Document Feedback AS7030B/AS7038GB/AS7038RB
Content Guide
Content Guide
1 Introduction ................................... 3 4.5 ADC and FIFO ............................................ 17

4.6 Digital Interface ........................................... 19
1.1 Kit Content .................................................... 3 4.7 Sampling Sequencer .................................. 19
1.2 Ordering Information .................................... 4
5 Software Description ................... 25
2 Getting Started .............................. 5
5.1 Software Architecture ................................. 25
3 Hardware Description ................... 6 5.2 Graphical User Interface............................. 26
5.3 AS703x Firmware Upgrade ........................ 48
3.1 Hardware Architecture .................................. 6
3.2 Power Supply ............................................... 8 6 Revision Information ................... 52
4 AS7030B/AS7038GB/AS7038RB 7 Legal Information ......................... 53
Overview ........................................ 9
4.1 Optical Front End (OFE) ............................... 9
4.2 ECG Amplifier ............................................. 14
4.3 Electrical Analog Front End (EAFE) ........... 16
4.4 Light-to-Frequency Converter (LTF) .......... 17
Eval Kit Manual• PUBLIC

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Introduction
1 Introduction
The AS7030B/AS7038GB/AS7038RB Evaluation Kit allows evaluation of all functions on the
AS7030B/AS7038GB/AS7038RB Biosensor and test them in various applications.
The initial Evaluation Kit works with USB connection to the PC and comes with a GUI, which enables
the user to change AS7030B/AS7038GB/AS7038RB register settings, see measurement results and
many more.
The Windows GUI software is part of the kit and currently shows the raw data from FIFO with AGC
(Automatic Gain Control) features only. The Evaluation kit also contains firmware. New versions of the
firmware can be flashed onto the ARGON wireless module with an nRF52480 MCU.
1.1 Kit Content

Figure 1:
Evaluation Hardware Board
For full flexibility, the PCB of the evaluation kit has two parts: a controller boards and sensor board
(submodule or SMOD). The controller board has an accelerometer, three electrodes located and a
connector to interface with the submodule located on the breakout board. The break out part can be
re-connected to the Microcontroller part via an FPC cable if it is broken off.
AS7030B/AS7038GB/AS7038RB SMOD sensor board should be connected for the application
Eval Kit Manual • PUBLIC

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Introduction
purposes. There is also an option to attach external electrodes. If an optional Wristband evaluation kit
is used, the AS7030B/AS7038GB/AS7038RB wristband needs to be connected to the Wristband Pico
Blade connector J502 on the Mainboard. As a result, the sensor part of the kit needs to be separated
from the Mainboard.
Any signals important for development are accessible for probing at pin headers.
1.2 Ordering Information
Ordering Code Description
AS703X_EVALKIT_BT Evaluation Kit for AS7030B/AS7038GB/AS7038RB

AS7030B_WRISTBAND Wristband to connect to AS703x EvalKit
AS7038GB_WRISTBAND Wristband to connect to AS703x EvalKit
AS7038RB_WRISTBAND Wristband to connect to AS703x EvalKit

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Getting Started
2 Getting Started
The client software latest version is available for download at https://ams.com/as7030B#tab/tools or
https://ams.com/as7038GB#tab/tools or https://ams.com/as7038RB#tab/tools or the software is
possible to find on the USB stick as a part of the evaluation kit. To install, just double as shown in
Figure 2 (left to right, top to bottom)
Figure 2:
AS703x Software Installation
For updating the FW on the evaluation board over USB, please refer to chapter 5.3.1 for more details.

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Hardware Description
3 Hardware Description
3.1 Hardware Architecture

Figure 3:
AS703x Controller Board – Top View
Wireless Module IEC 60601

Compilant DC-DC SMOD Interface
converter
ECG INN Electrode
Test Point for External ECG REF Electrode

Test Point for External ECG INN Electrode
Test Point for External ECG INP Electrode
Break Out Line

Isolators for all Connector for
Sensor on/off
Signals Sensor Board ECG REF Electrode
Button
ECG INP Electrode

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Figure 4:
AS703x Controller Board – Bottom View
Current
Measurement
ADC ADS114
Connector for
External
Electrodes
Connector for SMOD module

Break out Board Connector
Figure 5:
SMOD703xx – Top View
Internal
LEDs External External External
GREEN LEDs RED LEDs IR LEDs
AS7038RB
AS7038GB
AS7030B
Connector for AS703x

Controller Board

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Figure 6:
Fitting the SMOD703xx Sensor Board with the AS703x Controller Board
Push
Board is Ready
● The controller board supports AS7030B, AS7038GB & AS7038RB SMOD boards.
● The SMOD board should be mounted very carefully as shown in the Figure 6.
● During the mounting or changing of the SMOD board, the controller board should be turned off.
● Always mount the optical adapter on the top on the chip.
3.2 Power Supply

The AS7030B/AS7038GB/AS7038RB Eval Kit is supplied by the USB connector on the wireless
module. In order to avoid a direct connection from the electrodes to the power grid, an IEC 60601-1
compliant RECOM DCDC converter (R1SE - 3.305/H2) is assembled on the board as well as isolator
ICs for all signals passing to the sensor board. This means that there is no galvanic connection
between the sensor board and the power grid.

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AS7030B/AS7038GB/AS7038RB Overview
4 AS7030B/AS7038GB/AS7038RB Overview
Based on the optical filter and photodiode size, there are three types of AS703xxB sensors. AS7030B
& AS7038GB are most sensitive to green/IR light, and AS7038RB is most sensitive to red/IR light. On
the other hand, AS7030B has internal LEDs (two greens and one IR LED), but AS7038GB/RB
supports only external LEDs.
The operation of the AS7030B/AS7038GB/AS7038RB is based on photoplethysmography (PPG) and

electrocardiogram (ECG). PPG is the most used HRM method, which measures the pulse rate by
sampling light modulated by the blood vessels, which expand and contract as blood pulses through
them. ECG is the reference for any measurement of the biopotential generated by the heart.
Additionally, AS7038RB can measure blood oxygen saturation (SpO2).
In addition, the AS7030B/AS7038GB/AS7038RB devices also provide interfaces to external sensors.

These integrate an optical front end, ECG amplifier, electrical analog front end, and light to frequency
(LTF) converter. Features a built-in sampling sequencer, 128-byte FIFO, a 14-bit SAR ADC, four
GPIO pins, and an I²C interface.
Information
The main architecture of the AS703xxB sensor series is the same except a LED configurations,
● AS7030B has internal LEDs but AS7038GB/RB does not.

In this User Guide, the complete AS703xxB sensor series will be explained. Therefore, the chip
number will be emphasized if the dedicated part will come during the explanation. If there is no chip
number is mentioned in a chapter or portion of the chapter, that implies all the chips.
4.1 Optical Front End (OFE)

The Figure 7 below shows the block diagram of the optical front end.

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Figure 7:
Optical Front End
AS7030B
AS7038GB/RB
For AS7030B
The optical front end consists of:

● 4 LED drivers, individually configurable, operated manually or controlled by the built-in sampling
sequencer
● 2 built-in green LEDs (VD1 and VD2)
● 1 built-in IR LED (VD4)
● 1 free for connecting an external LED to VD3
● 6 photodiodes
● 4 with green filters (PD1, PD2, PD3 and PD4)
● 1 with IR filter (B) (PD5)
● 1 Clear (A) (PD6)

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Figure 8:
Photodiode Arrangement for AS7030B
For AS7038GB / AS7038RB
The optical front end consists of:

● 4 LED drivers, individually configurable, operated manually or controlled by the built-in
sequencer
● 6 photodiodes
● 4 with green filters (PD1, PD2, PD3, and PD4) (If AS7038GB)
4 with RED/IR filters (PD1, PD2, PD3, and PD4) (If AS7038RB)
● 1 with IR filter (B) (PD5)
● 1 Clear (A) (PD6)

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Figure 9:
Photodiode Arrangement for AS7038GB and AS7038RB
AS7038GB
AS7038RB

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Trans-Impedance Amplifier (TIA)

● Configurable photodiode connection
● Photodiode input current offset compensation
● Configurable gain
● 2 different modes of operation – photocurrent to voltage converter or photocurrent integrator
● Clip detection
Figure 10:
Trans-Impedance Amplifier
● TIA output filter (Prefilter, see Figure 11)

● Adjustable anti-aliasing low-pass filter
● Configurable high-pass filter to remove DC component
● Adjustable gain stage
● Clip detection
● 2 identical signal conditioning blocks (OFE1 and OFE2, see Figure 11)
● Synchronous demodulator – Used to extract small optical signals in noisy environment
(ambient light)
● Adjustable synchronous demodulator output low pass filter
● Adjustable high pass filter for DC component removal
● 50/60 Hz notch filter
● Adjustable output gain stage
● Adjustable low pass OFE1/2 output anti-aliasing filter (Figure 11)

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Figure 11:
Optical Signal Conditioning
Each of the blocks depicted on Figure 11 can be individually enabled or disabled/bypassed.
4.2 ECG Amplifier

The ECG (electro cardiogram) amplifier is a high impedance, low noise instrumentation amplifier with
analog circuitry to band pass filter the signal. Gain is distributed between 3 gain stages. The gain in
the first stage determines the tradeoff between achievable noise level and achievable input offset
voltage. With the highest gain of 4 at the first gain stage (G1) about 400 mV of offset can be managed.
This value scales up to a max of 1.6 V of offset at gain 1. An optional 50/60 Hz notch filter can be
enabled to attenuate unwanted noise from mains coupling.
The recommended gain settings are 4-6-8 and 4-6-16

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Figure 12:
ECG Amplifier Circuit
ecg_low_leakage_en for diode leakage G_ina=18

reduction on ECG_INP and ECG_INN (programmable 1 .. 48)
Hi gh Pass Filter Stage 2 Di fferential Notch Low Pa s s Anti Al iasing Ga i n Stage

Sta ge1
Ampl i fier Fi l ter Fi l ter Fi l ter
AS7030_ECG_INP G1 G2
1 .. 4 1 .. 12 1 G=1..128 ADC
0.33Hz
50 Hz 40-200 Hz 800Hz
800 Hz
Leads off SIGREF
detect Instrumentational Filter Gain
Amplifier
AS7030_ECG_INN
ecg_ref_en
AS7030_ECG_REF
SIGREF
to electrical
frontend
Figure 13:
Recommended ECG Frontend Filter
Electrodes
ECG
ECG_INP
ECG_INN
ECG_REF

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4.3 Electrical Analog Front End (EAFE)

The four general-purpose pins and ECG_REF can be used as analog input pins for the electrical
analog front end.
The analog inputs configuration sets up different non-inverting amplifier topologies:

● With offset and input voltage divider
● With current source and offset
● With current source and reference path
● With high impedance, GND referenced
● With DC-Blocking, referenced to V_ADCRef/2
● With DC-blocking and fast settling time, referenced to ADCRef /2
Figure 14:
Electrical Analog Front End

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4.4 Light-to-Frequency Converter (LTF)

The LTF module can use any of the photodiodes. Photodiodes connected to the LTF cannot be used
at the same time with TIA. Integration time (itime) is configured in unit steps, one unit step is 3.702 ms.
The unit step can be reduced by 2, 4 or 8, this also reduces the resolution of the conversion. The LTF
modulator can be set to run continuously and write the result of each integration to the FIFO.
Figure 15:
Light-to-Frequency Converter
4.5 ADC and FIFO
4.5.1 ADC
The ADC is a 14-bit successive approximation register type with input clock of 1 MHz. A configurable
clock divider can reduce the input clock. One conversion takes 25 clock cycles plus configurable
number of ADC settling clock cycles (64 the default for ADC settling cycles).The ADC can be manually
triggered by register or automatically triggered by the built-in sampling sequencer. Two channel
selection registers ADC_CHANNEL_MASK_L and ADC_CHANNEL_MASK_H define the channels the
ADC will convert. The ADC will start with the channels in ADC_CHANNEL_MASK_L from the LS
asserted bit to the MS asserted bit, then continue with the channels in ADC_CHANNEL_MASK_H
register again from LS asserted bit to MS asserted bit. Then wraps back to the LS bit of
ADC_CHANNEL_MASK_L. Thus, the ADC will go through each channel in the order as shown in
Figure 16 with TIA being the first (smallest index), OFE1 second, SD1 third and so on to the GPIO2
being the last.

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When triggered from the sequencer, the channel selection is always set to the smallest channel when
the sequencer starts for the first time. When sequencer starts, then stops and starts again, channel
selection will not reset, it will stay at the channel it was on when the sequencer stopped.
When triggered manually, the channel selection resets with every write to one of the channel selection
registers.
After each conversion, the sample goes to the FIFO and the channel selection automatically advances
to the next enabled channel. The current ADC output is also available in the ADC data register, but as
there is no latch mechanism, the data from this register can be inconsistent as the ADC might be
running at the time of ADC data register access.
ADC can trigger an interrupt after conversion has finished.
Figure 16:
ADC Channels

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4.5.2 FIFO
The AS7030B/AS7038GB/AS7038RB FIFO is 256 bytes long. ADC samples are 2 bytes each, which
means, FIFO can hold up to 128 samples. There is a FIFO length register, which indicates how much
samples are currently available in the FIFO. The FIFO can send an interrupt when the number of
available samples reaches a certain configurable threshold.
4.6 Digital Interface
4.6.1 GPIO Pins
All four GPIO pins can be digitally controlled and can have pull up/down enabled. They can also be
used as analog input pins for the EAFE, GPIO2 and GPIO3 can additionally be used with the ADC.
4.6.2 Interrupts
An interrupt output pin INT is used to interrupt the host. Depending on the setting in register INTENAB
each of the interrupt source below can assert INT output pin (active low).
● irq_adc: End of ADC conversion
● irq_sequencer: End of sequencer sequence reached.
● irq_ltf: A light-to-frequency conversion is finished.
● irq_adc_threshold: ADC threshold triggered
● irq_fifothreshold: FIFO almost full (as defined in register fifo_threshold)
● irq_fifooverflow: FIFO overflow (error condition, data is lost)
● irq_clipdetect: TIA output and/or SD output exceeded threshold– see details in CLIPSTATUS
● irq_led_supply_low: LED supply low comparator triggered
4.7 Sampling Sequencer

The sampling sequencer synchronizes the LED pulsing, the synchronous demodulator, the ADC and
the integrator times. The sequencer configuration sets the LED on and off times, synchronous
demodulator positive and negative multiplication times, the ADC start time and the integrator start and
stop times. The sequencer generates the 8-bit timings based on the 1 μs input clock. The input clock
can be reduced with a configurable clock divider.
The sequencer executes measurement cycles with a period defined by Equation 1 where SEQ_PER
and SEQ_DIV are registers of AS7030B/AS7038GB/AS7038RB having values from 0 to 255 (see in
the AS7030B/AS7038GB/AS7038RB datasheet):

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Equation 1:
𝑆𝐸𝑄_𝑃𝐸𝑅 ∗ (𝑆𝐸𝑄_𝐷𝐼𝑉 + 1) ∗ 1𝜇𝑠
SEQ_DIV holds the value of the 1 µs input clock divider.
Within one sequencer cycle, the sequencer will:

● Switch on the LEDs at the specified LED start time and then switch them off at the LED stop
time.
● Start the positive and negative synchronous modulator multiplications at the specified start and
stop times for each operation
● Trigger a conversion of the currently selected ADC channel at the time specified by the ADC
start time. After the conversion has finished, ADC channel selection will advance the next
enabled ADC channel, which is measured during the next cycle that gives one ADC channel per
sequencer cycle. For the TIA channel, two additional ADC timings can be specified. That means
TIA can be measured up to 3 times within the same sequencer cycle:
● A 2nd measurement will be done, if the value for “2nd TIA” is specified (> 0) and is greater
than the one given in “1st” plus the time needed for the ADC to finish one conversion.
● A 3rd measurement will be done, if “3rd TIA” value is specified (> 0) and is greater than the
one given in “2nd TIA” plus the time needed for the ADC to finish one conversion.
● In the case of more than one TIA measurement within the same sequencer cycle, it is
important to make sure that the additional measurements can finish within the time of one
sequencer cycle.

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Figure 17:
Sequencer Block Diagram
4.7.1 Sampling Rate and Subsampling
Throughout this document, sampling rate refers to the rate at which the sequencer produces samples
of the same ADC channel. This depends on the number of enabled ADC channels and on
configuration of the subsampling feature of the sequencer.
Subsampling is used when the application requires lower sample rates than what is possible with the
configured SEQ_PER and SEQ_DIV values, and with the number of enabled ADC channels. Lower
sample rate can also be achieved by setting SEQ_PER and SEQ_DIV to large enough values, but this
is not advisable as SEQ_DIV is multiplied to all the timings of the sequencer, thus the LED pulses will
become very long, which is probably not desired. SEQ_DIV should be kept relatively small for finer
resolution of the times.

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The register SEQ_CFG and SD_SUBS configure how subsampling will be executed:
● sd_subs field in SD_SUBS register defines if subsampling is enabled; when it is 0, no
subsampling is done – every sequencer cycle triggers an ADC measurement (Figure 18);
setting to N>0, enables subsampling and then for N sequencer cycles the sequencer will not
trigger the ADC, followed by one cycle with ADC conversion.
● sd_subs_always bit in SEQ_CFG register defines if all enabled ADC channels are subject to
subsampling. Using this only makes sense for more than one enabled ADC channel.
● sd_subs_always = 1: subsampling of all enabled ADC channels (Figure 19)
● sd_subs_always = 0: subsampling of the first enabled ADC channel only (Figure 20)
The following three figures below show how subsampling is executed by the sequencer. In all of them
ADC cycle means one ADC iteration through all the enabled channels.
Attention
ADC cycle is not the same as sequencer cycle. ADC_SEL is the ADC channel selection;
ADC_ACCESS is an ADC conversion of the currently selected ADC channel; tADC is the configured
ADC start time in the sequencer configuration; tSUB is the sequencer period given by Equation 1.
In Figure 18 three ADC channels are enabled --1 (OFE1), 6 (EAFE) and 11 (GPIO2). No subsampling
enabled (sd_subs=0).
In Figure 19 three ADC channels are enabled -- 0 (TIA), 4 (SD2) and 8 (ECGO). Subsampling is
enabled, every second sequencer cycle will trigger the ADC (sd_subs=2) and all enabled ADC
channels are subsampled.
In Figure 20 three ADC channels are enabled – 0 (TIA), 4 (SD2) and 8 (ECG0). Subsampling is
enabled, every third sequencer cycle will trigger ADC (sd_subs=3) and only the first enabled ADC
channel is subsampled.

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Figure 18:
No Subsampling (sd_subs=0)
Figure 19:
Subsampling of All Enabled ADC Channels (sd_subs=2 and sd_subs_always=1)

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Figure 20:
Subsampling of 1st Enabled ADC Channel Only (sd_subs=3 and sd_subs_always=0)

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Software Description
5 Software Description
5.1 Software Architecture

Figure 21:
SW Modules
AS703xxB

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5.2 Graphical User Interface

This section describes the Graphical User Interface (GUI) of the AS7030B/AS7038GB/AS7038RB
Vital Sign Sensor application. The application is designed to be used with
AS7030B/AS7038GB/AS7038RB sensor series evaluation kits.
Information
● User Guide Version - 1.00

● Valid for the following software version - AS703x_EvalSW_v1-0-1
● Supported hardware - AS7030B_Evalboard v1.1
● Download - Navigate to https://ams.com/as7030B#tab/tools or
https://ams.com/as7038GB#tab/tools or https://ams.com/as7038RB#tab/tools and download
the latest version.

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5.2.1 Overview
Figure 22 shows the main window of the graphical user interface. To connect to the board the
connection control elements are used (1). The measured data is displayed in the main section of the
application (6). Applications such as HRM and SpO2 data are displayed (9).
Figure 22:
AS7030B/AS7038GB/AS7038RB Vital Sign Sensor - Graphical User Interface
1
2 8
7
9
3
10
11
4
5
6
12
1 Connection control elements 7 Graphical representation of data

2 Configuration presets 8 Measurement type
3 AS7030B/AS7038GB/AS7038RB 9 Application settings
configuration settings 10 Calculated values based on measurement
4 Controller configuration settings type
5 Start/Stop button 11 The currently configured values for PD
6 Recording the data as log file offset and Led input current
12 Connection status and FW version of
connected hardware

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5.2.2 Powering Up and Starting a Measurement
1. Connect the sensor board and the mainboard via the 10-pin flat cable if you already broke the
board; otherwise, you can skip this step.
2. Connect the micro USB to USB cable to the Bluetooth module and plug it into your computer.
3. Afterwards, press the S1 button for 3 seconds to turn on the sensor board.
4. The green LED on the ARGON board will light up as soon as the board is powered.
5. Start the client software.
6. Select the appropriate COM port number from the drop-down menu.
7. Click the connect button
8. Connect button will change its icon to upon successful connection.

9. The two status boxes on the bottom right side will turn green and show the FW number
currently flashed on the board.
Figure 23:
Starting a Measurement

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10. Select one of the built-in configuration presets

11. Optionally check and change AS7030B/AS7038GB/AS7038RB settings. On the first startup
after SW installation no settings are loaded, after that the last used settings will be used.
12. To start a measurement with the current settings click on the Start button.
13. The green AS7030B/AS7038GB/AS7038RB LEDs will turn on, Start button’s caption will
change to “Stop”
14. Hold the ECG INP and reference electrodes with pointer and middle finger of your left hand, put
the pointer finger of your right hand on the ECG INN electrode and the middle finger of your
right hand on the AS7030B/AS7038GB/AS7038RB to measure
15. The raw pulse and ECG data will be displayed in the GUI
16. The output of the algorithm will be displayed on the right hand side of the window. The numbers
in the curly brackets show how many seconds have passed since the last result different than
zero was reported. After five seconds of no new result, the values will time out and the content
of the fields will change to “--“.
5.2.3 AS7030B/AS7038GB/AS7038RB Configuration Settings
The AS7030B/AS7038GB/AS7038RB configuration settings are located on the left of the evaluation
software (see Figure 22). At power-up, the board starts with the following default configuration:
● The two green LEDS - LED1(VD1) and LED2(VD2) are enabled, the LED current set to 1 mA
● Sequencer period set to 2000 µs
● Photodiode Trans-Impedance amplifier (TIA) is on and used
● All filters are on and used
● ADC is set to measure only the optical front end 1 after the gain stage (OFE1)
The individual settings of each of the AS7030B/AS7038GB/AS7038RB blocks can be viewed/changed

in the dedicated configuration sub menu. To enter the submenus press the corresponding button.

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Figure 25:
Figure 24:
AS7030B/AS7038GB/AS7038RB Block Diagram Highlighted
Submenu Selection
Blocks are Configured in the According Submenus
2
4
1
2 3
3
4
5
6 6
7
8
5
9
10 1
AS7030B
11 AS7038GB/RB 1
For further information, please refer to the AS7030B/AS7038GB/AS7038RB Datasheet.
LED Configuration
Attention
LED current, LED mode and LED state can be set in the “LEDs configuration” window. It is
recommended to configure the current only when the output is not active as there is no latch
implemented to keep the 10 bits consistent.
The LED current can be set via sliders in a range of 0.7 -100 mA. Using the Boost option the LED
current can be doubled. The LEDx on option is only active in manual mode. In all other cases the
LEDs will be controlled by the logic.
The textbox LEDs current (mA) shown in Figure 26 allows to enter a numeric value for LED current
which will be set to all LEDs.

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Figure 26: Figure 27:

LED Configuration Submenu LED Driver Block Diagram
For further information, please refer to the following document:
● AS7030B/AS7038GB/AS7038RB Datasheet
Photodiodes Configuration
Select the photodiodes which are to be connected to TIA input. The offset current is optional, this
allows cancellation of constant light sources like sunlight. Default value for the input offset current is 0
for both – LEDs off and any LED on. By default the offset is controlled by the PD offset control
algorithm accessible via menu 11.
For an external photodiode or any other sensor with (low) current output, the pins GPIO0 and GPIO1
can be used as input.
The sequencer controls the diodes – see DIODE_CTRL described in register MAN_SEQ_CFG.

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Photodiode Configuration Submenu Photodiode Block Diagram
TIA (Trans-Impedance Amplifier) Configuration
The TIA has to be configured according to the information in theAS7030B/AS7038GB/AS7038RB

datasheet (table in Figure 28 AS703x Block Diagram).
It is recommended to keep the TIA settings at their default.

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TIA Configuration Submenu TIA Block Diagram
For changing the TIA, stick to the following suggestions:
Figure 32:
TIA Suggestion
pd_ampres pd1234(1) pd_ampcap pd_ampcomp pd_ampvo Gain
1 1…4 13 1 15 1 V/µA
2 1…4 7 1 15 2 V/µA
3 1…4 5 1 15 3 V/µA
1…2 2
4 0 15 5 V/µA
3…4 3
1…2 2
5 0 15 7 V/µA
3…4 3
1 1
6 0 15 10 V/µA
2…4 2
1…2 1
7 0 15 14 V/µA
3…4 2

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pd_ampres pd1234(1) pd_ampcap pd_ampcomp pd_ampvo Gain
Low Bandwidth Mode
5 1…4 31 3 15 7 V/µA
Integrating Mode (pd_ampres=0)
0 1…4 10 3 15 1 V/pQ
0 1…4 20 3 15 1/2 V/pQ
0 1…4 30 3 15 1/3 V/pQ
(1) pd1234 … number of active photodiodes (for example, pd1=1, pd2=0, pd3=1, pd4=0 -> pd1234=2)

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OFE (Optical Frontend) Configuration
In this window, the OFE blocks can be enabled and the filter chain is configured.

OFE Configuration Submenu OFE Block Diagram
Check OFE1 and/or OFE2 check box to enable the corresponding OFE block.
To optimize signal quality adapt the OFE Gain setting to your application. The Bandwidth of HP and
LP can also be changed to suit your needs. The “SD negative initial polarity” switch will invert the
signal.
The “Prefilter” tab is used to configure the input filters of the two synchronous demodulators. For
reference, please see OFE_CFGA, OFE_CFGB, OFE_CFGC and OFE_CFGD register descriptions in
the AS7030B/AS7038GB/AS7038RB datasheet.

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Sequencer Configuration
Figure 35:
Sequencer Configuration Submenu
The “Cycle period” field of the “Sequencer configuration” window (see Figure 35) holds the value of
the SEQ_PER register. The client software will automatically calculate its value from the user input for
Sample frequency/period entered in the fields “Frequency (Hz)” / “Period (µs)” of the “Sequencer
configuration” window (Figure 35). Sample period/frequency is the period/frequency between # of
samples of the same ADC channel and it depends on the number of enabled ADC channels. If the
calculation yields a value for the cycle period that is bigger than 255 - the maximum possible,

UG001014 • v1-00 • 2021-May-06 53 │ 36
subsampling will be enabled1. Please refer to Sampling Rate and Subsampling for details on sampling
rate.
Use this window to enable/disable ADC channels.
Any change in the values of the fields for sample frequency, sample period, cycle period and in the
ADC channel selection will cause a new calculation of the values for the rest of the fields.
● AS7030B/AS7038GB/AS7038RB Datasheet.
ADC Configuration
This window configures the clock divider of the 1 MHz ADC input clock and the ADC settling periods.
ADC channels are enabled in the Sequencer Configuration window. The selection is shown below.

ADC Configuration Submenu ADC Block Diagram
For further information, please refer to the following documents:
1
For example, with one ADC channel enabled and desired sample rate of 200 Hz, the sequencer cycle period needs to be
5000 µs. If (SEQ_DIV+1) is 10, the SEQ_PER register should be 500, but as it is 8 bits, it cannot fit the value 500. It is also not
advisable to increase the clock divider as that will affect all the other timing settings, it is better to keep that small to give finer
granularity of the timing. To achieve the 200 Hz sample rate, the cycle period will be set to 250 and subsampling enabled with
subsampling ratio of 2 – meaning the ADC will be triggered every 2nd sequencer cycle. That will give a sample rate of 200 Hz /
5000 µs period.

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ECG Amplifier Configuration
The ECG (electro cardiogram) amplifier is a high impedance, low noise instrumentation amplifier with
analog circuitry to band pass filter the signal. Gain is distributed between 3 gain stages. The gain in
the first stage determines the tradeoff between achievable noise level and achievable input offset
voltage. With the highest gain of 4 at the first gain stage (G1) about 400 mV of offset can be managed.
This value scales up to a max of 1.6 V of offset at gain 1. An optional 50/60 Hz notch filter can be
enabled to attenuate unwanted noise from mains coupling.
The recommended gain settings are 4-6-8 and 4-6-16.
The ECG signal can be used independently or together with PPG in further computation. (e.g. blood
pressure).
Figure 38:
ECG Amplifier Configuration Submenu

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Figure 39:
ECG Amplifier Block Diagram
ecg_low_leakage_en for diode leakage G_ina=18

reduction on ECG_INP and ECG_INN (programmable 1 .. 48)
Hi gh Pass Filter Stage 2 Di fferential Notch Low Pa s s Anti Al iasing Ga i n Stage

Sta ge1
Ampl i fier Fi l ter Fi l ter Fi l ter
AS7030_ECG_INP G1 G2
1 .. 4 1 .. 12 1 G=1..128 ADC
0.33Hz
50 Hz 40-200 Hz 800Hz
800 Hz
Leads off SIGREF
detect Instrumentational Filter Gain
Amplifier
AS7030_ECG_INN
ecg_ref_en
AS7030_ECG_REF
SIGREF
to electrical
frontend
Electrodes
ECG
ECG_INP
ECG_INN
ECG_REF

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Electrical Analog Frontend Configuration
The electrical analog front end consists of three identical signal paths with independent settings of
bias condition, gain and offset.
Here the EAF_CFG, EAF_GST, EAF_BIAS, EAF_DAC and EAF_DAC_CFG registers are set.
Figure 40:
Figure 41:
Electrical-Analog-Frontend Configuration
Electrical-Analog-Frontend Block Diagram
Submenu

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Light-to-Frequency Configuration
Light-to-frequency feature can be used to measure light input directly. Its main purpose is proximity
detection.
Attention
Do not use diodes that are connected to the TIA (register PD_A, PD_B, PD1...4) at the same time
when itf_en is enabled on the same diode.
For detailed information, please refer to the AS7030B/AS7038GB/AS7038RB datasheet.

Light-to-Frequency Configuration Submenu Light-to-Frequency Block Diagram
The following registers can be shown/configured in the dialog: ITIME, LTF_CONFIG, LTF_SEL and
LTF_GAIN.
GPIOs Configuration
To set a GPIO to analog mode check the check box from the “GPIO mode” group box. If left
unchecked, then the GPIO is a digital output or input, depending on the state of the “GPIOx enable

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output” check boxes - unchecked means the pin is digital input. If the pin is set as digital output, it’s
state can be set via the corresponding check box in the “Output state” group box.

GPIO Configuration Submenu GIPO Block Diagram
5.2.4 Controller Configuration
This section describes the configurations of the firmware running on the microcontroller that
communicates with the AS7030B/AS7038GB/AS7038RB.
PD Offset and LED Current Control Configuration
The PD offset and LED current control is an algorithmic approach to increase signal quality of PPG
signals. The algorithm continuously monitors the TIA and OFE1 outputs and if necessary reconfigures
the AS7030B/AS7038GB/AS7038RB while measuring to ensure ideal conditions.

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Figure 46:
PD Offset & LED Current Control Submenu
Minimum amplitude of the controlled signal in ADC counts – If the amplitude of the ADC signal drops
below that value, LED current will be increased, if LED current control is enabled.
Maximum amplitude of the controlled signal in ADC counts– If the amplitude of the ADC signal grows
above that value, LED current will be decreased, if LED current control is enabled.
Number of samples to average – How many ADC samples are averaged before values go to FIFO.
AGC reset interval – The interval at which the min and max values are calculated over a moving
average are reset in order to keep a recent history and to avoid random spikes.

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Minimum threshold of the controlled signal in ADC counts – If the amplitude of the ADC signal drops
below that value, LED current will be increased, if LED current control is enabled.
Maximum threshold of the controlled signal in ADC counts– If the amplitude of the ADC signal grows
above that value, LED current will be decreased, if LED current control is enabled.
AGC Algorithm selection – Based on the automatic gain control TIA2, TIA3 and OFE1 can be selected
or AGC algorithms can be disabled.
Minimum and maximum LED output current – Sets the range in which the LED current can move if
LED current control is enabled. If LED current control is disabled the LED have constant LED current
set in the LED Configuration window.
5.2.5 Advanced Settings
Application Settings
The “Application Settings” setting is located on the right side of the evaluation software (Figure 22).
This setting is mainly use to select and change the HRM and SpO2 configuration blocks and
parameters.
The “Signal Routing” which is PPG signal source configuration, window is used to select the PPG and
SpO2 blocks as shown in the Figure 47.
Figure 47:
Signal Routing

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For AS7038RB
The “SpO2” is for configuring the SpO2 Parameters. These parameters associated with the specific
settings of the AS7038R must be entered in the SpO2 configuration settings. Because of production
and assembling tolerances, it is recommended that the below-mentioned factors for the photodiode
offset current compensation (𝑃𝐷𝑜𝑓𝑓_𝑓𝑎𝑐𝑡_𝑟𝑒𝑑 and 𝑃𝐷𝑜𝑓𝑓_𝑓𝑎𝑐𝑡_𝑖𝑟 ) are determined for the device under
development, after the sensor (AS7038R) has been integrated and the optical configuration is
finalized.
Figure 48:
SpO2 Configuration
● AS7038RB_SpO2_Calibration_Note
Register Map
The “Register Map” window is used to view/change the contents of the complete set of
AS7030B/AS7038GB/
AS7038RB user register. To open it, click on the “  Register Map” menu.
Changing a register value can be doe either by modifying its value in the relevant “Value” field or by
toggling a bit by clicking on the relevant bit cell. Changing a value in the register map will not update
the current selection in the configuration windows of the GUI. Also, a change in any of the
configuration windows will not trigger an automatic update of the already opened register map window.
To update the values, click on the refresh button marked with the orange rounded rectangle on the
“Register Map” picture on the right.

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Figure 49:
Register Map Dialog
Saving Current Configuration Settings to a File
The current configuration settings can be exported to a file. To do this, click on the “File  Save
Configuration” menu. This will open the “Save Configuration File” dialog box on the second picture on
the right. Enter file name and choose the file location, then click “Save”.
Loading Configuration Settings from File
To load a previously exported configuration settings, click on the “File  Load Configuration” menu.
This will open the “Select Configuration File” dialog box. Select the configuration file from which to
load settings and click “Open” button.
The settings imported from the file can be reviewed in the relevant configuration windows.
If the GUI is connected to the board, the newly imported settings will be applied immediately,
otherwise upon successful connection to the board.

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Figure 50:
Figure 51:
Safe and Load Configuration Menu
Safe Configuration File Dialog
Entries
Raw Data Logging and Exporting
Before starting the measurement by clicking the “Start” button, click the “Record” button to save the raw
data from the AS703x. When a measurement is stopped with the “Stop” button, a pop-up window will
appear to select the file location and save the CSV file.
Figure 52:
Export Raw Data Menu
5.2.6 Signal Optimization
Three settings have a major impact on signal strength and quality:

● LED current
● OFE gain
● Offset compensation
LED current has a direct impact on signal strength with minimal impact on noise. OFE gain will
increase overall signal strength but also increase noise. We recommend the following settings to begin
with and start experimenting from there:

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Figure 53:
Useful Start Settings
Use Case LED Current [mA] OFE Gain

Finger 0.768 4
Light skin wrist 2 8
Dark skin wrist 5 16
5.3 AS703x Firmware Upgrade
5.3.1 Controller Firmware Update over USB
1. Connect the USB cables to the Argon board.

2. Push “mode” and ON (S1) buttons together for 3 seconds, then release.
Figure 54:
Switch ON/OFF & Mode Button
Mode Button
Sensor Board On/Off Button (S1)

ON: Press the button for 1 Sec
OFF: Press the button for 3 sec
3. The red LED on the Argon board will be turned on.

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4. Check the right COM port name from the “Device Manager”
Figure 55:
Device Manager
5. Open the Application Firmware folder
Figure 56:
Firmware Folder
6. Modify batch script 'update_firmware.bat' to set right virtual com port

● Open the batch script 'update_firmware.bat' with the “Notepad++”
● Put the correct COM port as shown in the below

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Figure 57:
Notepad++
● Save the file and close the Notepad++

7. Double click the batch script “update_firmware.bat” to update the firmware.
Figure 58:
Firmware Update
8. The message "Device programmed" and the green LED switching on, means that programming
was successful.

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Figure 59:
Update Successful

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Revision Information
6 Revision Information
Changes from previous version to current revision v1-00 Page
Initial production version
● Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
● Correction of typographical errors is not explicitly mentioned.

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Legal Information
7 Legal Information
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved.
The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
Demo Kits, Evaluation Kits and Reference Designs are provided to recipient on an “as is” basis for demonstration and
evaluation purposes only and are not considered to be finished end-products intended and fit for general consumer use,
commercial applications and applications with special requirements such as but not limited to medical equipment or automotive
applications. Demo Kits, Evaluation Kits and Reference Designs have not been tested for compliance with electromagnetic
compatibility (EMC) standards and directives, unless otherwise specified. Demo Kits, Evaluation Kits and Reference Designs
shall be used by qualified personnel only.
ams AG reserves the right to change functionality and price of Demo Kits, Evaluation Kits and Reference Designs at any time
and without notice.
Any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a
particular purpose are disclaimed. Any claims and demands and any direct, indirect, incidental, special, exemplary or
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1 Introduction ................................... 3 4.5 ADC and FIFO ............................................ 17

Eval Kit Manual• PUBLIC

1.1 Kit Content

Eval Kit Manual • PUBLIC

1.2 Ordering Information

Ordering Code Description

AS703X_EVALKIT_BT Evaluation Kit for AS7030B/AS7038GB/AS7038RB

Eval Kit Manual • PUBLIC

Eval Kit Manual • PUBLIC

3.1 Hardware Architecture

Wireless Module IEC 60601

Test Point for External ECG REF Electrode

Break Out Line

Eval Kit Manual • PUBLIC

Connector for SMOD module

Connector for AS703x

Eval Kit Manual • PUBLIC

3.2 Power Supply

Eval Kit Manual • PUBLIC

The operation of the AS7030B/AS7038GB/AS7038RB is based on photoplethysmography (PPG) and

Additionally, AS7038RB can measure blood oxygen saturation (SpO2).

In addition, the AS7030B/AS7038GB/AS7038RB devices also provide interfaces to external sensors.

● AS7030B has internal LEDs but AS7038GB/RB does not.

4.1 Optical Front End (OFE)

Eval Kit Manual • PUBLIC

The optical front end consists of:

Eval Kit Manual • PUBLIC

For AS7038GB / AS7038RB

The optical front end consists of:

Eval Kit Manual • PUBLIC

Eval Kit Manual • PUBLIC

Trans-Impedance Amplifier (TIA)

● TIA output filter (Prefilter, see Figure 11)

Eval Kit Manual • PUBLIC

Each of the blocks depicted on Figure 11 can be individually enabled or disabled/bypassed.

4.2 ECG Amplifier

The recommended gain settings are 4-6-8 and 4-6-16

Eval Kit Manual • PUBLIC

ecg_low_leakage_en for diode leakage G_ina=18

Hi gh Pass Filter Stage 2 Di fferential Notch Low Pa s s Anti Al iasing Ga i n Stage

Eval Kit Manual • PUBLIC

4.3 Electrical Analog Front End (EAFE)

The analog inputs configuration sets up different non-inverting amplifier topologies:

Eval Kit Manual • PUBLIC

4.4 Light-to-Frequency Converter (LTF)

4.5 ADC and FIFO

Eval Kit Manual • PUBLIC

ADC can trigger an interrupt after conversion has finished.

Eval Kit Manual • PUBLIC

4.6 Digital Interface

4.6.1 GPIO Pins

4.7 Sampling Sequencer

Eval Kit Manual • PUBLIC

𝑆𝐸𝑄_𝑃𝐸𝑅 ∗ (𝑆𝐸𝑄_𝐷𝐼𝑉 + 1) ∗ 1𝜇𝑠

SEQ_DIV holds the value of the 1 µs input clock divider.

Within one sequencer cycle, the sequencer will:

Eval Kit Manual • PUBLIC

4.7.1 Sampling Rate and Subsampling