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574 327
K.V.G COLLEGE OF ENGINEERING, SULLIA, D.K. – 574 327
(AFFILIATED TO VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VLSI LAB MANUAL

COURSE CODE: 21ECL66
VI SEMESTER
Academic Year: 2023-24

Course Material Prepared by Course Material Approved by

Dr. Savitha M Dr. Kusumadhara S

Professor Dept. of E&C Professor & Head, Dept. of E&C

Prepared By Approved by
 VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI
B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication Engineering
NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2021 – 22)
VI Semester

VLSI Laboratory
Course Code 21ECL66 CIE Marks 50
Teaching Hours/Week (L: T: P: S) 0:0:2:0 SEE Marks 50
Credits 1 Exam Hours 3

Course objectives:
This laboratory course enables students to
 Design, model, simulate and verify digital circuits.
 Design layouts and perform physical verification of CMOS digital circuits.
 Perform ASIC design flow and understand the process of synthesis, synthesis constraints and
evaluating the synthesis reports to obtain optimum gate level netlist.
 Perform RTL-GDSII flow and understand the stages in ASIC.
Sl.No. Experiments
ASIC Digital Design
1 4-Bit Adder
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
2 4-Bit Booth Multiplier
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
3 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for ALU
Behavioral Modeling
• Write Verilog Code
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
4 Latch and Flip-Flop
 Synthesize the design and compare the synthesis report (D, SR, JK)

ASIC Analog Design

5 a) Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
Inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology.
Carry out the following:

19.09.2023
 i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
ii. From the simulation result compute tpHL, tpLH and td for all three geometrical settings
of width?
iii. Tabulate the results of delay and find the best geometry for minimum delay for CMOS
inverter?
b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
6 a) Capture the schematic of 2-input CMOS NAND gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NAND gate and also find
out the delay td for all four possible combinations of input vectors. Table the results. Increase
the drive strength to 2X and 4X and tabulate the results.
b) Draw the layout of NAND with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC
and LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
7 a) Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and find its
transient response and AC response? Measure the Unit Gain Bandwidth (UGB), amplification
factor by varying transistor geometries, study the impact of variation in width to UGB.
b) Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC & LVS,
extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.
8 a) Capture schematics of two-stage operational amplifier and measure the following:
i. UGB
ii. dB Bandwidth
iii. Gain Margin and phase margin with and without coupling capacitance
iv. Use the op-amp in the inverting and non-inverting configuration and verify its
functionality.
v. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the
stage wise transistor geometries and record the observations.
b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained
in part a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform
post layout simulations, compare the results with pre-layout simulations. Record the
observations.
Demonstration Experiments ( For CIE )
9 UART
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist, Identify Critical path
10 For synthesized netlist carry out the following:
• Floor planning
• Placement and Routing
• Record the parameters such as no. of metal layers used for routing, flip method for placement
of standard cells
• Physical Verification and record the DRC and LVS reports
• Generate GDSII

19.09.2023
 11 Design and characterize 6T binary SRAM cell and measure the following:
• Read Time, Write Time, SNM, Power
• Draw Layout of 6T SRAM, use optimum layout methods. Verify for DRC & LVS, extract parasitic
and perform post layout simulations, compare the results with pre-layout simulations. Record the
observations.
Course outcomes (Course Skill Set):
On the completion of this laboratory course, the students will be able to:
1. Design and simulate combinational and sequential digital circuits using Verilog HDL.
2. Understand the synthesis process of digital circuits using EDA tool.
3. Perform ASIC design flow and understand the process of synthesis, synthesis constraints and
evaluating the synthesis reports to obtain optimum gate level netlist.
4. Design and simulate basic CMOS circuits like inverter, common source amplifier, differential
amplifier, SRAM.
5. Perform RTL_GDSII flow and understand the stages in ASIC design.

decided jointly by examiners.

udents can pick one question (experiment) from the questions lot prepared by the internal
/external examiners jointly.
Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly
by examiners.
General introductions suggested for SEE are mentioned here, writeup-20%, Conduction
procedure and result in -60%, Viva-voce 20% of maximum marks. SEE for practical shall be
evaluated for 100 marks and scored marks shall be scaled down to 50 marks (however, based
on course type, rubrics shall be decided by the examiners).
Change of experiment is allowed only once and 15% Marks allotted to the procedure part
to be made zero.
The duration of SEE is 03 hours.
Rubrics suggested in Annexure-II of Regulation book
 LIST OF EXPERIMENTS

PART A
SL no Name of experiment
1. 4- Bit Adder Supporting 4-Logical And 4-Arithmetic
Operations
2. 4 Bit Booth Multiplier

3. 32-Bit Alu

4. Latches

5 Flip-Flops

PART B

6 CMOS Inverter

7 2-input Nand Gate

8 Common source amplifier

9 Operational amplifier
 VLSI LAB MANUAL

PART - A
DGITAL DESIGN

STEPS FOR HANDLING THE XILLINX

I). Design Entry and Simulation:

1. Desktop r xillinx ISE 9.5

2. Goto File New project - Give name to project click Next

3. Enter the specification of the Target device as

Sparten 3, XCS 400, TQ144 And Speed grade as 4/5

4. Select Verilog language in same window click next

5. Click on NEW Source click on Verilog module give name of the module

6. Click next 4 times and finally click Finish

7. Enter the program in Verilog Design editor click on SAVE

8. Select ‘ synthesize XST ‘ click on Check syntax, if any error , Clear it

II) To synthesize design :

1. Select ‘ synthesize XST ‘ click on view synthesis report and observe the ‘
Device utilization summary’ ,

2. Click RTL schematic and view the diagram

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III). To enter Testbench Program :

1. Select behavioural and simulation in Source Click on ‘ create new source’ on

process

2. Click on ‘ Verilog test fixture’ give name to test bench program click next

3. Enter the testbench program click on SAVE

4. click on Check syntax, if any error , Clear it

5. click on ‘ Simulate behavioral ‘ in process

6. Waveform will appear on simulation window

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Sample program : INVERTER

AIM: To write Verilog code for inverter and to perform simulation , synthesis and study the area and timing
constraints

Truth Table :
a (i/p) b(o/p)
0 1
1 0

Verilog program for inverter:

module inverter(a,b) ;
input a;
output b;
assign b = ~a;
endmodule

Test Bench program:

module inverter_tb;
reg a;
wire b;
inverter uut (a,b);
initial
begin

a=1'b0;
#100 a =1'b1;
#100 a=1'b0;
#100 a =1'b1;

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#100;
end
initial
begin
$monitor( $time, " a=%b and b=%b”, a , b );
end
endmodule
SIMULATION RESULT OF INVERTER:

Synthesis Report:
Device Utilization for xcs400tq1444
***************************************************************
Resource Used Avail Utilization
---------------------------------------------------------------
IOs 1 232 1.29%
Global Buffers 0 24 0.00%
LUTs 1 9312 0.01%
CLB Slices 1 4656 0.02%
Dffs or Latches 0 9776 0.00%
Block RAMs 0 20 0.00%
Block Multipliers 0 20 0.00%

---------------------------------------------------------------

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Design No . 1:
4 BIT ADDER

4 BIT PARELLEL ADDER:

Block diagram:

Truth Table:
a b c s cout
0 0 11 1100 0 1111 0
0001 0111 1 1000 0
1100 0111 0 0011 1

Verilog Program:

module fulladder (a, b, cin, sum, carry);

input a, b, cin;
output sum, carry;
assign sum=a ^ b^ cin;
assign carry= (a & b)| (b & cin) | (cin & a);
endmodule

module parellel (a, b, cin, sum, carry);

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input [3:0] a,b;
input cin;
output [3:0] sum;
output carry;
wire [3:1] w;

fulladder fa0(.a[0], b[0],. cin,.sum[0],.w[1]);

fulladder fa1(.a[1], b[1],. w[1],.sum[1],.w[2]);

fulladder fa2(.a[2], b[2],. w[2],.sum[2],.w[3]);

fulladder fa3(a[3],.b[3],.w[3],.sum[3],.carry);

endmodule

Test Bench program:

module parellel_tb;
reg [3:0] a,b;
reg cin;
wire [3:0] sum;
wire carry;
parellel uut (a, b, cin, sum, carry);
initial
begin
a=4'b0111; b=4'b0100; cin=1'b0;
#10; a=4'b1011; b=4'b0110; cin=1'b1;
end
initial
$monitor ($time, "a=%b b=%b cin=%b sum=%b carry=%b",a, b, cin, sum, carry);
Endmodule

Simulation result parallel adder:

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Synthesis report :

Device Utilization for 3S500EFG320

***************************************************************
Resource Used Avail Utilization
---------------------------------------------------------------
IOs 5 232 2.16%
Global Buffers 0 24 0.00%
LUTs 2 9312 0.02%
CLB Slices 1 4656 0.02%
Dffs or Latches 0 9776 0.00%
Block RAMs 0 20 0.00%
Block Multipliers 0 20 0.00%

Conclusion :

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Design no: 3

32 bit ALU
Aim: 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for ALUBehavioral
Modeling

Opcode (3:0) ALU Operation Remarks

0000 A+B Addition of twonumbers

0001 A–B Subtraction of twonumbers

0010 A&B // Bitwise AND

0011 A OR B Bitwise OR

0100 A XOR B Bitwise EX OR

0101 ~(A&B) Bitwise NAND

0110 A<<B Left shift operand_A by operand_B[4:0] bits

0111 A>>B Right shift operand_A by operand_B[4:0] bits

0111 A+1 Increment A by 1

1000 A-1 Decrement by 1
1001 ~A Complement A

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Verilog code:
module ALU32( input en,
input [0:3] op_code ,
input [31:0] A,
input [31:0] B,
output reg ack,
output reg [32:0] result
);

always@(en,op_code,A,B)
begin
if(en)
case(op_code)
4'b0000: res= A+B;
4'b0001: res= A-B;
4'b0010: res= A&B;
4'b0011: res= A|B;
4'b0100: res= A^B;
4'b0101: res= A&B;
4'b0110: res= A<<B;
4'b0111: res= A>>B;
4'b1000: res= A+1;
4'b1001: res= A-1;
4'b1010: res= ~A;
default: res=33'hxxxxxxxx;
endcase
else
res= 33’hzzzzzzzz;
ack = 1'b1;
#5 ack =1'b0;
end
endmodule

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Test Bench:
module TB_ALU32;

// Inputs
reg en;
reg [3:0] op;
reg [31:0] A;
reg [31:0] B;

wire [32:0] res;

wire ack;

// Instantiate the Unit Under Test (UUT)

ALU32 uut (
.en(en),
.op(op),
.A(A),
.B(B),
.ack(ack),
.res(res)
);
initial
begin

op = 02;
A = 20;
B = 10;

// Wait 50 ns for global reset to finish #50;

// Add stimulus here

en = 1;
A = 32'hffff_ffff;
B = 32'h2;
op = 0;
#50; op = 1;
#50; op = 2;
#50; op = 3;
#50; op = 4;
#50; op = 5;
#50; op = 6;
#50; op = 7;
#50; op = 3'b1xx;
#50;

end
endmodule

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Result obtained:

Synthesis Result of JK flip flop :

Device Utilization for 3S400tq1444
***************************************************************
Resource Used Avail Utilization
---------------------------------------------------------------
IOs 4 232 1.72%
Global Buffers 1 24 4.17%
LUTs 2 9312 0.02%
CLB Slices 1 4656 0.02%
Dffs or Latches 1 9776 0.01%
Block RAMs 0 20 0.00%
Block Multipliers 0 20 0.00%

Conclusion:

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DESIGN NO 4 : FLIPFLOPS
AIM: To write verilog code for all the types of flipflops and to perform simulation , synthesis and study
the area and timing constraints
D flip flops :

Block diagram Truth Table

CLK RST Data Q

 1 x 0

 0 0 0
 0 1 1

Verilog code Test bench program

module dff_tb;
reg clock, reset, d;
module dff (reset, clock, d, q, qb); wire q, qb;
input reset, clock, d; dff uut (reset, clock, d, q, qb);
output q, qb; initial
reg q; begin
wire qb; clock=1'b1;
always @ (posedge clock) reset=1'b0;
begin end
if (reset) always #5 clock=~clock;
q<=1'b0; always #40 reset=~reset;
else initial
q<=d; begin
end #20 d =1'b1;
assign qb=~q; #20 d =1'b0;
endmodule #30 d =1'b1;
#30 d =1'b0;
end
initial
begin
$monitor ($time, "reset=%b clock=%b d=%b q=%b
qb=%b", reset, clock, d, q, qb);
end
endmodule

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JK Flip Flop:
Block diagram Truth Table

CLK RESET JK Q
 1 XX 0
 0 00 Q
 0 01 0
 0 10 1
 0 11 qbar
.(Toggle)

Verilog code Test bench program :

module JK_FF (JK, clock, q, qb); module JK_ff_tb;
input [1:0] JK; reg [1:0] JK;
input clock; reg clock;
output reg q, qb; wire q, qb;
always @ (posedge clock) JK_FF uut(JK, clock, q, qb);
begin initial
case (JK) clock=1'b1;
2'b00 : q = q; always #5 clock=~clock;
2'b01 : q = 1'b0; initial
2'b10 : q = 1'b1; begin
2'b11 : q =~ q; JK=2'b00; #20;
endcase JK=2'b01; #20;
qb =~ q; JK=2'b10; #20;
end JK=2'b11; #50;
endmodule end
initial
$monitor ($time, "JK=%b q=%b qb=%b ", JK, q, qb);
endmodule

Simulation Result of JK flip flop :

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Synthesis Result of JK flip flop :

Device Utilization for 3S400tq1444
***************************************************************
Resource Used Avail Utilization
---------------------------------------------------------------
IOs 4 232 1.72%
Global Buffers 1 24 4.17%
LUTs 2 9312 0.02%
CLB Slices 1 4656 0.02%
Dffs or Latches 1 9776 0.01%
Block RAMs 0 20 0.00%
Block Multipliers 0 20 0.00%

Conclusion:

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RS flip flops:
Block diagram Truth Table
CLK Reset SR Q
 1 XX 0
 0 00 Q
 0 01 0
 0 10 1
 0 11 Indetermitant

Verilog code Test bench program

module rs_ff_tb;
reg [1:0] sr;
module rs_ff(rs, clock, q, qb); reg clock;
input [1:0] rs; wire q, qb;
input clock; rs_ff uut(rs, clock, q, qb);
output reg q, qb; initial
always @ (posedge clock) clock=1'b1;
begin always #5 clock=~clock;
case (rs) initial
2'b00 : q = q ; begin
2'b01 : q = 1'b1 ; rs=2'b00; #20;
2'b10 : q = 1'b0 ; rs =2'b01; #20;
2'b11 : q = 1'dZ ; rs =2'b10; #20;
endcase rs =2'b11; #50;
qb =~ q; end
end initial
endmodule $monitor ($time, "rs=%b q=%b qb=%b ", rs, q, qb);
endmodule

Simulation Result of SR flip flop:

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Synthesis Result of SR flip flop:

Device Utilization for 3S500EFG320
***************************************************************
Resource Used Avail Utilization
---------------------------------------------------------------
IOs 4 232 1.72%
Global Buffers 1 24 4.17%
LUTs 2 9312 0.02%
CLB Slices 1 4656 0.02%
Dffs or Latches 1 9776 0.01%
Block RAMs 0 20 0.00%
Block Multipliers 0 20 0.00%
---------------------------------------------------------------

Conclusion:

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S R LATCH

AIM: To write verilog code for SR Latch and D type and to perform simulation , synthesis and study the
area and timing constraints

Verilog code:

module SR_latch(Q, Qbar, Sbar, Rbar);

output Q, Qbar;
input Sbar, Rbar;
. nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
endmodule

Stimulation block:

module Top;
wire q, qbar;
reg sbar, rbar;
SR_latch m1(q, qbar, sbar, rbar);
initial
begin
$monitor($time, " sbar = %b, rbar= %b, q= %b\n",sbar,rbar,q,qbar);
sbar = 0; rbar = 0;
#5 rbar = 1;
#5 rbar = 0;
#5 sbar = 1;
end
endmodule

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output obtained:

Synthesis result:

Conclusion

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D Latch

Verilog code:
module d_latch ( input d, // 1-bit input pin for data
input en, // 1-bit input pin for enabling the latch
input rstn, // 1-bit input pin for active-low reset
output reg q); // 1-bit output pin for data output

always @ (en or rstn or d)

if (!rstn)
q <= 0;
else
if (en)
q <= d;
endmodule

Testbench Program:
module tb_latch;
reg d;
reg en;
reg rstn;
wire q;
d_latch uut( .d (d),
.en (en),
.rstn (rstn),
.q (q));
initial begin
$monitor ("[%0t] en=%0b d=%0b q=%0b", $time, en, d, q);

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// 1. Initialize testbench variables

d <= 0;
en <= 0;
rstn <= 0;

// 2. Release reset
#10;
rstn <= 1;
en=1; d=0;
#10;
En=1;d=1;
#10;

end
endmodule

output obtained:

Synthesis result:

Conclusion:

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MICROWIND TOOL
MICROWIND is truly integrated EDA software encompassing IC designs from concept
to completion, enabling chip designers to design beyond their imaginat ion. MICROWIND
integrates traditionally separated front -end and back-end chip design into one flow,
accelerating the design cycle and reduces design complexit ies.

It tightly integrates mixed-signal implementation with digital implementation, circuit

simulation, transistor-level extraction and verification – providing an innovative education
init iative to help individuals to develop the skills needed for design positions in virtually
every domain of IC industry.

The MICROWIND software allows the designer to simulate and d esign an integrated circuit
at physical description level. Born in Toulouse (France), Microwind is an innovative CMOS
design tool for educational market.

Microwind is developed as comprehensive package on windows platform to enable students

to learn smart design methods and techniques with more practice. With inbuilt layout
editing tools, mix-signal simulator, MOS characteristic viewer and more, it allows students
to learn complete design process with ease.

Microwind unifies schematic entry, pattern based s imulator, SPICE extraction of schematic,
Verilog extractor, layout compilation, on layout mix -signal circuit simulation, cross
sectional & 3D viewer, netlist extraction, BSIM4 tutorial on MOS devices and sign -off
correlation to deliver unmatched design per formance and productivit y.

With its approach for CMOS design education, Microwind has gained lot followers
worldwide. Universities across the globe are using Microwind for budding engineers to
teach CMOS concepts with ease. Paving their path for more skilled softwares to be used at
later stage of their course work.

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PART I
ANALOG DESIGN
Procedure for schematic design by using DSCH
1. Open DSCH 3.1.
2. File tab -generate spice file.
3. To set path for spice file, select option for Browse- select the drive.
4. Construct the schematic circuit by dragging the components from the pallet.
5. Save and run.
6. Go to program files.
7. Select Microwind 3.1 folder.
7. Select client folder-select DSCH3.1 folder-select system folder.
8. Select spice library file-close the window-Enable the ADD node list.
9. Check on update spice file.
10. Change to n.
11. Save the spice file and click ok.

Procedure for layout design by using Microwind

1. Open Microwind.
2. Open file tab-Open select foundry-select CMOS 0.12μm technology.
3. Construct layout by picking the layers from the pallet.
4. Save and simulate the layout.
5. Check DC and Transient analysis.
6. Calculate Gain of layout and verify with the practical result.
7. Extract RC values.
8. Note all the results- save and quit.

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Experiment no : 1
CMOS INVERTER
Question:

i). Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology. Carry out the
following:
a. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and time
period of 20ns and plot the input voltage and output voltage of designed inverter?
b. From the simulation results compute tpHL, tpLH and td for all three geometrical settings of
width?
c. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter?

Schematic design:
For NMOS and PMOS Wn=Wp, Wn=2Wp,Wn=Wp/2

Output waveform

Steps to convert the schematic to layout

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1. Go to microwind1 and draw the schematic

2. Save the file with file name
3. Simulate the schematic for correct output
4. Go to file -----Make a verilog file
5. Go to microwind 2
6. Go to compile
7. Compile verilog file created in the microwind 1
8. Layout of the schematic will be generated

II). Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS,extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.

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Transient Chacterstics

DC Characterstics

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For Wn=2Wp

Schematic diagram

Generated layout for the verilog file

Output waveform

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Results

SL No Transistor Tplh Tphl Td

geometry

1 Wn=Wp,

2 Wn=2Wp

3 Wn=Wp/2

Conclusion :

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Experiment no:2

2 -INPUT NAND GATE

Question:

i). Capture the schematic of 2-input CMOS NAND gate having similar delay as that
of CMOS inverter computed in experiment 1. Verify the functionality of NAND gate
and also find out the delay td for all four possible combinations of input vectors.
Table the results. Increase the drive strength to 2X and 4X and tabulate the results .

OUTPUT WAVEFORM:

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Generated layout

ii). Draw layout of NAND withWp/Wn = 40/20, use optimum layout methods. Verify for DRC
and LVS, extract parasitic and perform post layout simulations, compare the results with
pre-layout simulations. Record the observations.

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Voltage versus time characteristics

Conclusion:

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Experiment no:1

COMMON SOURCE AMPLIFIER

I). Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and
find its transient response and AC response? Measures the Unity Gain Bandwidth
(UGB),.

Schematic diagram

II). Draw layout of common source amplifier, use optimum layout methods. Verify for
DRC and LVS,extract parasitic and perform post layout simulations, compare the
results with pre-layout simulations.Record the observations.

Layout diagram

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Output waveform (voltage vs time characteristics)

Output waveform( Voltage vs voltage characteristics)

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Results

Conclusion

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Experiment no 4:
i). Capture schematic of two-stage operational amplifier and measure the following:
a. UGB
b. dB bandwidth

Layout diagram

Output waveform

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4. b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in 180/90/45
nm technology), choose appropriate transistor geometries as per the results obtained in 4.a. Use optimum
layout methods. Verify for DRC and LVS, extract parasitic and perform post layout simulations, compare the
results with pre-layout simulations. Record the observations.

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Output waveform:

Conclusion:

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