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7-MUX, DeMUX, Encoder and Decoder Circuits-07!06!2024

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78 views47 pages

7-MUX, DeMUX, Encoder and Decoder Circuits-07!06!2024

Uploaded by

sedhupathirajendranofficial
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BECE102L – Digital Systems Design

Module 3 – Design of Combinational Logic Circuits

Dr. Rohit Mathur


Assistant Professor Sr. Grade 1
School of Electronics Engineering

Digital System Design 1


Multiplexers
• Combinational Circuit to select a binary information from one of the many input
lines to single output line. The term Multiplexer means many into one.
• Multiplexing is the process of transmitting a large number of information over a
single line.
• A Multiplexer is also called a Data Selector.
➢Multiplexer contains the followings:
❖ data inputs
❖ selection inputs
❖ a single output
• Selection input determines the input that should be connected to the output.
Digital System Design Lab 2
2:1 Multiplexer
4:1 Multiplexer
Implementation of NOT gate using 2 : 1 Mux

Digital System Design Lab 30


Implementation of AND gate using 2 : 1 Mux
Implementation of OR gate using 2 : 1 Mux
Implementing Boolean Functions using Mux
• F(x,y,z) = Ʃ(1,2,6,7)
• x and y are connected to the selection inputs of the multiplexer in the same order.
• x is connected to S1 and y is connected to S0
• z, z’, 0 and 1 are connected to the data inputs of the multiplexer

Digital System Design Lab 11


Digital System Design Lab 12
Exercise
1. Construct a 16x1 Multiplexer with two 8x1 and one 2x1 multiplexers. Write the Verilog HDL.
2. Implement the following Boolean function with a Multiplexer
a) F(A,B,C,D) = Ʃ(0,2,5,8,10,14)
b) F(A,B,C,D) = ∏(2,6,11)
3. Implement a full adder with two 4x1 Multiplexer

Digital System Design Lab 31


De-Multiplexer
• De-Mux is a combinational circuit that receives input from a single line and directs it to one of
the 2n output lines based on the ‘n’ bit selection lines.
• A decoder with enable input can function as a de-multiplexer with the following
considerations.
• The input of decoder can be considered as selection lines of the de-multiplexer
• The enable signal of the decoder can be considered as the data input of the de-multiplexer

Digital System Design Lab 32


Even Parity Generator
• A parity bit is an extra bit included with a binary message to make the number of 1’s either odd
or even.

• A circuit that generates the parity bit in the transmitter is called parity generator.

• It is very useful in systems requiring error detection and correction codes.

Digital System Design Lab 33


Even Parity Checker
• The circuit that checks the parity in the receiver is called a parity checker.

Digital System Design Lab 34


Code Converters
Code converters – take an input code, translate to its equivalent output
code.
Input Code Output
code converter code

Example: BCD to Excess-3 Code Converter.


Input: BCD digit
Output: Excess-3 digit

Digital System Design Lab 35


BCD-to-Excess-3 Code converter
BCD is a code for the decimal digits 0-9
Excess-3 is also a code for the decimal digits

Digital System Design Lab 36


Specification of BCD-to-Excess3

Inputs: a BCD input, A,B,C,D with A as the most significant bit and D
as the least significant bit.

Outputs: an Excess-3 output W,X,Y,Z that corresponds to the BCD


input.

Internal operation – circuit to do the conversion in combinational logic.

Digital System Design Lab 37


Formulation of BCD-to-Excess-3

Excess-3 code is easily formed by adding a binary 3 to the


binary or BCD for the digit.

There are 16 possible inputs for both BCD and Excess-3.

It can be assumed that only valid BCD inputs will appear so


the six combinations not used can be treated as don’t cares.

Digital System Design Lab 38


BCD-to-Excess-3 Code Converter
▪Truth table:
BCD Excess-3
A B C D W X Y Z
0 0 0 0 0 0 0 1 1 W(A,B,C,D) = Σm(5,6,7,8,9)
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1 +d(10,11,12,13,14,15)
3
4
0
0
0 1
1 0
1
0
0 1 1 0
0 1 1 1
X(A,B,C,D) = Σm(1,2,3,4,9)
5 0 1 0 1 1 0 0 0 +d(10,11,12,13,14,15)
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0 Y(A,B,C,D) = Σm(0,3,4,7,8)
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0 +d(10,11,12,13,14,15)
10
11
1
1
0 1
0 1
0
1
X X X X
X X X X
Z(A,B,C,D) = Σm(0,2,4,6,8)
12 1 1 0 0 X X X X +d(10,11,12,13,14,15)
13 1 1 0 1 X X X X
14 1 1 1 0 X X X X
15 1 1 1 1 X X X X Digital System Design Lab 39
W(A,B,C,D) = Σm(5,6,7,8,9) X(A,B,C,D) = Σm(1,2,3,4,9) Y(A,B,C,D) = Σm(0,3,4,7,8) Z(A,B,C,D) = Σm(0,2,4,6,8)
+d(10,11,12,13,14,15) +d(10,11,12,13,14,15) +d(10,11,12,13,14,15) +d(10,11,12,13,14,15)

W = A + BC + BD X = BC’D’+B’C+B’D Y = CD + C’D’ Z = D’
Digital System Design Lab 40
Two level circuit implementation
Have equations
W = A + BC + BD = A + B(C+D)
X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
Y = CD + C’D’
Z = D’
Factoring out (C+D) and call it T
Then T’ = (C+D)’ = C’D’
W = A + BT
X = B’T + BT’
Y = CD + T’
Z = D’
Implementing the second set of equations where T=C+D results in a lower gate
count.
Digital System Design Lab 41
W = A + BT
X = B’T + BT’
Y = CD + T’
Z = D’

Digital System Design Lab 42


BCD-to-Seven-Segment Decoder

Specification
Each digit is created by lighting the appropriate segments. The segments are labeled
a,b,c,d,e,f,g
The decoder takes a BCD input and outputs the correct code for the seven-segment
display.
Input: A 4-bit binary value that is a BCD coded input.
Outputs: 7 bits, a through g for each of the segments of the display.
Operation: Decode the input to activate the correct segments.

Digital System Design Lab 43


BCD Input 7 Segment Decoder

Decimal A B C D a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1
Invalid BCD
6 0 1 1 0 1 0 1 1 1 1 1 codes
=
7 0 1 1 1 1 1 1 0 0 0 0 No Light

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 0 0 1 1

10-15 All Other Inputs 0 0 0 0 0 0 0

Digital System Design Lab 44


a b c
d

e f g
Digital System Design Lab 45
a = A’C + A’BD + AB’C’ + B’C’D’
b = A’B’ + A’C’D’ + A’CD + B’C’
c = A’B + B’C’ + A’C’ + A’D
d = A’CD’ + A’B’C + B’C’D’+AB’C’+A’BC’D
e = A’CD’ + B’C’D’
f = A’BC’ + A’C’D’ + A’BD’ + AB’C’
g = A’CD’ + A’B’C + A’BC’ + AB’C’

Digital System Design Lab 46


Binary-Gray conversions

Digital System Design Lab 47

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