Name: Amna Arif

Sap ID: 49752

Question 1:
Assume a pipeline with four stages: fetch instruction (FI), decode
instruction and calculate addresses (DA), fetch operand (FO), and
execute (EX). Draw a diagram similar to Figure 14.10 for a sequence of
7 instructions, in which the third instruction is a branch that is taken and
in which there are no data dependencies.
Answer :
Instruction 1 2 3 4 5 6 7 8 9 10
11 F1 DA FO EX
12 - F1 DA FO EX
13 - F1 DA FO EX
14 F1 DA FO
15 F1 DA
16 F1
115 F1 DA FO EX

Question 2:
Assume a pipeline with five stages: instruction fetch (IF), instruction
decode (ID), operand fetch (OF), execute (EX), and write-back (WB).
Draw a pipeline diagram for a sequence of 8 instructions where the
fourth instruction is a branch that is taken. Explain how control hazards
are managed in this scenario.

Answer :
Cycle 1 2 3 4 5 6 7 8 9
Instruction I1 I2 I3 I4 I5 I6 I7 I8

Stages:
IF I1 I2 I3 B - - -
ID - I1 I2 I3 B - -
OF - - I1 I2 I3 B -
EX - - - I1 I2 I3 B
WB - - - - I1 I2 I3

In this diagram:
 The pipeline has five stages: Instruction Fetch (IF), Instruction
Decode (ID), Operand Fetch (OF), Execute (EX), and Write-Back
(WB).
 Each instruction moves through the pipeline stages in subsequent
cycles.
 The fourth instruction (I4) is a branch instruction that is taken.
 The '-' symbol indicates that a stage is idle or not yet reached by an
instruction.

Question 3:
Consider a processor with a three-stage pipeline: instruction fetch (IF),
instruction decode (ID), and execute (EX). Draw a pipeline diagram for
a sequence of 6 instructions where the second instruction is a branch that
is taken. Discuss how control hazards are handled, ensuring there are no
data dependencies.

Answer :
Cycle 1 2 3 4 5 6 7 8 9 10

IF I1 I2 I3 I4 I5 I6 - - - -

ID - I1 I2 I3 I4 I5 I6 - - -

EX - - I1 I2 - I3 I4 I5 I6 - -
In this diagram, each row represents a stage of the pipeline (IF, ID, EX)
and each column represents a cycle. The instructions are denoted as I1,
I2, I3, I4, I5, and 16.

Question 4:
Assume a pipeline with four stages: instruction fetch (IF), instruction
decode (ID), operand fetch (OF), and execute (EX). Draw a diagram for
a sequence of 10 instructions, in which the fifth instruction is a branch
that is taken, ensuring there are no data dependencies. Describe any
potential resource hazards that might arise.

Answer:
Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13

IF I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 - - -

ID I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 - -

OF I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 - -

EX I1 I2 I3 - I4 I5 I6 I7 I8 I9 I10

In this diagram:
 IF: Instruction Fetch stage
 ID: Instruction Decode stage
 OF: Operand Fetch stage
 EX: Execute stage the instructions are denoted as I1 to I10.
Question 5:
Given a pipeline with five stages: fetch (F), decode (D), fetch operands
(FO), execute (EX), and write-back (WB), draw a pipeline diagram for a
sequence of 9 instructions, with the seventh instruction being a branch
that is taken. Ensure there are no data dependencies.

Answer :
Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IF I1 I2 I3 I4 I5 I6 I7 I8 I9
ID I1 I2 I3 I4 I5 I6 I7 I8 I9 - - - - -

OF I1 I2 I3 I4 I5 I6 I7 I8 I9 - - - -
EX I1 I2 I3 I4 I5 - I6 I7 I8 I9 - -
WB I1 I2 I3 I4 I5 - I6 I7 I8 I9 -

In this diagram:
 F: Fetch stage
 D: Decode stage
 FO: Fetch Operands stage
 EX: Execute stage
 WB: Write-back stage the instructions are denoted as I1 to I9.

Question 6:
Assume a pipeline with four stages: fetch (F), decode (D), execute (E),
and write-back (W). Create a pipeline diagram for a sequence of 12
instructions where the sixth instruction is a branch that is taken. Include
and discuss potential data dependencies and how they are resolved.
Answer:
Cycle 1 2 3 4 5 6 7 8 9 10 11 12

F I1 I2 I3 I4 I5 I6 I7 I8 I9 I19 I11 I12

D I2 I3 I4 I5 I6 I7 I8 I9I 10 I11 I12

E I3 I4 I5 I6 I7 I8 I9 I10 I11 I12

F I4 I5 I6 I7 I8 I9 I10 I11 I12

In this diagram:
 Each row represents the state of the pipeline at a specific cycle.
 The columns represent the stages of the pipeline: fetch (F), decode
(D), execute (E), and write-back (W).
 Instructions progress through the pipeline stages over consecutive
cycles.