Paging

 Paging is a memory-management scheme that permits the

physical address space of a process to be non contiguous.
 Paging avoids the considerable problem of fitting memory
chunks of varying sizes onto the backing store.
Basic Method
 Breaking physical memory into fixed-sized blocks called
frames and breaking logical memory into blocks of the same
size called pages.
 When a process is to be executed, its pages are loaded into
any available memory frames from the backing store.
 The backing store is divided into fixed-sized blocks that are of
the same size as the memory frames.
Paging
Paging
 Every address generated by the CPU is divided into two parts:
a page number (p) and a page offset (d).
 The page number is used as an index into a page table.
 The page table contains the base address of each page in
physical memory.
 This base address is combined with the page offset to define
the physical memory address that is sent to the memory unit.
Paging
Paging
 The page size (like the frame size) is defined by the hardware.
 The size of a page is typically a power of 2, varying between
512 bytes and 16 MB per page, depending on the computer
architecture.
 If the size of logical address space is 2m and a page size is 2n
addressing units (bytes or words), then the high-order m – n
bits of a logical address designate the page number, and the n
low-order bits designate the page offset.

 where p is an index into the page table and d is the

displacement within the page.
Paging:Example
Paging: Example
 Page size of 4 bytes and a physical memory of 32 bytes (8
pages.
 page 0 is in frame 5.
 Thus, logical address 0 maps to physical address 20 (= (5 x 4)
+ 0).
 Logical address 3 (page 0, offset 3) maps to physical address
23 =( (5x4) + 3).
 Logical address 4 is page 1, offset 0; Thus, logical address 4
maps to physical address 24 (= (6x4) + 0).
 Logical address 13 maps to physical address 9.
Paging-Disadvantage
 When we use a paging scheme, there is no external
fragmentation: Any free frame can be allocated to a process
that needs it.
 Paging have internal fragmentation.
 If the memory requirements of a process do not coincide with
page boundaries, the last frame allocated may not be
completely full.
 For example, if page size is 2,048 bytes, a process of 72,766
bytes would need 35 pages plus 1,086 bytes. It would be
allocated 36 frames, resulting in an internal fragmentation of
2,048-1,086 = 962 bytes.
 In the worst case, a process would need n pages plus 1 byte. It
would be allocated, n + 1 frames, resulting in an internal
fragmentation of almost an entire frame.
Paging
 When a process arrives in the system to be executed, its size,
expressed in pages, is examined.
 Each page of the process needs one frame.
 If the process requires n pages, at least n frames must be
available in memory.
 If n frames are available, they are allocated to this arriving
process.
 The first page of the process is loaded into one of the allocated
frames, and the frame number is put in the page table for this
process. The next page is loaded into another frame, and its
frame number is put into the page table, and so on
Paging
Paging-Hardware Support
 Each operating system has its own methods for storing page
tables.
 Some allocate a page table for each process.
 A pointer to the page table is stored with the other register
values (like the instruction counter) in the process control
block.
 When the dispatcher is told to start a process, it must reload
the user registers and define the correct hardware page-table
values from the stored user page table.
Hardware implementation of page table
1)Using Hardware registers
 A single page table consisting of an array of fast hardware
registers, with one entry for each virtual page, indexed by
virtual page number.
 When a process is started up, the operating system loads the
registers with the process‘ page table, taken from a copy kept
in main memory.
Advantages: It is straightforward and requires no memory
references during mapping.
Disadvantage: Potentially expensive (if the page table is large).
Having to load the full page table at every context switch hurts
performance.
Page Tables-Implementation
2)Page table stored entirely in main memory.
 Page table base register (PTBR) points to the start of the page
table.
 Changing the page table requires changing only this register
thereby reducing context switch time.
Disadvantage
 This scheme, requires two memory accesses to access a byte
(one for the page-table entry, one for the byte).
3) Translation Lookaside Buffer (TLB)
 The TLB is associative, high-speed memory.
 Each entry in the TLB consists of two parts:a key (or tag) and
a value.
 When the associative memory is presented with an item, the
item is compared with all keys simultaneously.
 If the item is found,the corresponding value field is returned.
 The search is fast;
 The TLB contains only a few of the page-table entries.
 When a logical address is generated by the CPU, its page
number is presented to the TLB.
 If the page number is found, its frame number is immediately
available and is used to access memory.
 If the page number is not in the TLB (known as a TLB miss), a
memory reference to the page table must be made.
 Then add the page number and frame number to the TLB.
 If the TLB is already full of entries, an existing entry must be
selected for replacement.
 Replacement policies range from least recently used (LRU)
through round-robin to random.
 Some TLBs allow certain entries to be wired down, meaning
that they cannot be removed from the TLB. Typically, TLB
entries for kernel code are wired down.
 Some TLBs store address-space identifiers (ASIDs) in each
TLB entry.
 An ASID uniquely identifies each process and is used to
provide address-space protection for that process.
 When the TLB attempts to resolve virtual page numbers, it
ensures that the ASID for the currently running process
matches the ASID associated with the virtual page.
 If the ASIDs do not match, the attempt is treated as a TLB
miss.
 ASID allows the TLB to contain entries for several different
processes simultaneously.
 The percentage of times that the page number of interest is
found in the TLB is called the hit ratio.
Eg: An 80-percent hit ratio, means that we find the desired page
number in the TLB 80 percent of the time.
Problem: If it takes 20 nanoseconds to search TLB and 100
nanoseconds to to access memory.Find the effective memory
access time? hit ratio is 80%.
Effective access time=(hit ratio*memory access time) +(miss ratio
*memory access time)
=hit ratio*(time to serach TLB+memory access time for desired
byte)+ miss ratio*(time to serach TLB+memory access time for
the page table and frame number+memory access time for desired
byte)
=0.8*120+0.20*220
=140 nanoseconds