TMS320TCI6618

Doubling performance for

4G wireless base stations

Product bulletin Key features

The race towards 4G is on! As wireless data rates increase with high-speed 3G now, • Newest multistandard wireless base station
system-on-chip (SoC) that delivers double
and move toward the future with even faster 4G services, the ability to efficiently handle
the LTE performance over existing solutions
the large number of bits flowing through base stations becomes critically important. while reducing SoC power consumption
Without the right silicon technology and design, base stations cannot handle the immense to the industry’s lowest levels at 0.075
amount of network traffic that 4G demands. Operators are being forced to move to mW/GMAC of power
• Highest performing multicore base station
heterogeneous networks that combine macro and small cell solutions to deliver affordable
SoC on the market today, delivering 2X the
bandwidth. Multiple input, multiple output (MIMO) antenna arrays and advanced receivers wireless system performance of any other
are key elements of the new wireless standards that increase the bandwidth capabilities base station SoC for 4G, with unmatched
of the network. throughput and lowest latency
• Bit rate coprocessor increases the SoC
system performance and enables advanced
The TMS320TCI6618 is a new multistandard tion for new base station designs. Multicore
receiver algorithms to achieve improved
wireless base station system-on-chip (SoC) that Navigator, a queue-based packet structure, spectral efficiency by up to 40 percent over
delivers double the LTE performance over exist- coupled with TI’s Open Navigator programming conventional decoding techniques
ing 40-nm solutions while reducing the SoC interface, gives designers the ability to add • TI’s new C66x DSP combines fixed
power consumption for macro and compact differentiating, value-added features easily. and floating point on the same core,
base stations to the industry’s lowest With both fixed- and floating-point process- delivering floating-point performance at
levels – 0.075 mW/GMAC of power. The ing on each DSP core, the TCI6618 enables fixed-point speeds for the first time
TCI6618 is ideally suited to the data-centric base station designers to take advantage of • Only solution to feature coprocessors for
every standard, including WCDMA chip
performance that wireless network opera- rapid algorithm prototyping and quick software rate – no FPGA/ASIC required
tors are demanding today for 4G macro base redesigns, reducing costs and development • Network coprocessor and Multicore
stations. Its multiple TMS320C66x DSP cores time. Because the C66x cores are so powerful, Navigator combine to provide Layer 2 and
provide programmable performance, while significantly fewer cores are needed to provide transport acceleration for all wireless base
new hardware accelerators focus on bit rate four times the processing power of previ- station standards
processing to allow base station manufacturers ous generations of TI processors. Designers • Based on TI’s new KeyStone architecture,
to deliver up to 40 percent more spectral ef- will enjoy simplified programming with fewer enabling scalability and portability from
macro to small cells reducing product
ficiency over conventional decoding techniques. cores, along with increased performance. It
development expense
TI’s TCI6618 is a scalable SoC based on TI’s also delivers 5.5 times cycle reduction over
• Multicore Navigator brings single core
KeyStone architecture and C66x DSP core. It previous generations in MIMO decoding, and simplicity to multicore SoCs
features the highest performance fixed- and enables a software defined MIMO decoder. • Best power/performance ratio, coupled with
floating-point operation, allowing base station In addition, designers can benefit from the unique power-saving hibernation modes,
designers to deliver the capacity and perfor- TCI6618’s pin and software compatibility with delivers the lowest power for base stations
mance to meet tomorrow’s demands today. the previously announced TCI6616 wireless • Leverages high-performance 40-nm
The TCI6618 enables manufacturers to reduce base station SoC, to design multistandard process technology
the cost per bit on the operator’s expensive air base stations that support all 2G, 3G, and 4G
interface, as well as lower power consump- standards. OEMs can simplify the migration
 fixed-point implementation alone. In addition,
Multicore Navigator the development and debugging cycle time
for complex algorithms is significantly reduced
CorePac Network coprocessor from a multiple-month cycle to just a few days.
IPY 4/Y 6 GTP/SCTP The TCI6618 integrates large on-chip
CorePac fast path
memory organized as a two-level memory
CorePac RSA IPsec/SRTP IEEE 1588 system that minimizes latency and increases
CorePac RSA
1 MB L2cache system performance. The level-1 (L1) program
Layer 2 coprocessor and data memories on the TCI6618 device
1 MB L2cache
C66x DSP RoHC Air ciphering are 32 KB each per core. The level-2 (L2)
1 MB L2cache QoS RLC/MAC memory is shared between program and data
1 MB L2 cache space for a total of 4,096 KB (1,024 KB per
Scheduler Fast path
core). The TCI6618 contains 2,048 KB of

TeraNet Layer 1 acceleration multicore shared memory (MSM) that is used

Memory system Turbo Turbo as a shared L2 SRAM or shared L3 SRAM. A
encoder decoder dedicated Multicore Shared Memory Controller
Multicore shared memory
64-bit controller (MSMC) Viterbi (MSMC) prevents memory contention between
DDR3 decoder FFT/DFT
the cores and arbitrates access to the shared
EMIF 2MB shared memory Interference TFCI CQI memory between the cores and other IP
cancellation decoder
blocks.
Uplink Downlink The TCI6618 has a high-performance pe-
System elements chip rate chip rate
Power ripheral set with everything needed to develop
management System monitor Modulator De-modulator robust base stations of varying coverage and
Debug EDMA capacity, including:
Rate Rate
matching de-matching
• I2C, SPI, and UART
Peripherals and I/O Scrambler Convolution • PCI Express port with two lanes supporting
de-scrambler encode
HyperLink

SRIO PCIe SGMII Gig E GEN1 and GEN2

4x 2x 2x switch Interleaver
de-interleaver CRC • Sixteen 64-bit general-purpose timers (also
CPRI/ UART SPI configurable as thirty-two 32-bit timers)
OBSAI I2C HARQ
PUCCH combining • 16-pin general-purpose input/output (GPIO)
port with programmable interrupt/event
generation mode
TCI6618 block diagram • Multicore Navigator for hardware-
accelerated dispatch
to 4G with this flexibility, and it allows them leverages the KeyStone architecture for scal-
• Four lanes of serial RapidIO® (SRIO),
to develop a wider portfolio of solutions at ability to meet the need of all base stations,
compliant with RapidIO 2.1 spec for up to
a lower cost and in a shorter time than with from single-sector small cells to multi-sector
5-Gbps operation per lane
competing solutions. macro cells. With one software base driving
• 64-bit DDR3 SDRAM interface
a variety of base station products, developers
TCI6618 high-performance • 16-bit external memory interface (EMIF) for
will realize the highest R&D efficiency possible
solution for 4G base stations connecting to flash memory (NAND and
as well as optimized product costs
Designed specifically for 4G wireless infra- NOR) and asynchronous SRAM
The TMS320TCI6618 is based on 40-nm
• Second-generation SERDES-based antenna
structure baseband applications, the TCI6618 process technology and delivers 4.8 GHz
interface (AIF2) capable of up to 6.25 Gbps
is an ideal solution for heterogeneous network of raw DSP processing power, as well as operation per link with six high-speed
base stations. The TCI6618’s coprocessor performance of up to 153.6 16-bit GMACs serial links, compliant to OBSAI RP3 and
performs 95 percent of the LTE Layer 1 per second, making it a cost-effective solu- CPRI standards
processing and substantially increases system tion for high-performance DSP programming
capacity and performance with the lowest challenges. Due to its floating-point capability, For efficient communications between
latency. The TCI6618 also enables SoC the TCI6618 offers performance of up to 76.8 the device and the network (as well as other
baseband solutions for GSM/EDGE, UMTS, billion floating-point operations per second devices), the TCI6618 includes a network
TD-SCDMA, WiMAX, and LTE applications. To (GFLOPs), making it the industry’s most pow- coprocessor that consists of:
make the transition from C6000™ DSPs easier, erful floating- and fixed-point SoC. Because • Two 10/100/1000 Ethernet media access
the TCI6618 is backward code-compatible, al- the TCI6618 incorporates both fixed- and controllers (EMACs), which provide an
lowing software reuse and maintaining value- floating-point capabilities on the same core, efficient interface between the TCI6618
added designs and IP. In addition, TI’s TCI6618 it can perform up to five times faster than a DSP core processor and the core network

2
• Management data input/output (MDIO) Total performance
module (also part of the EMAC) that Coprocessor
(@1.2-GHz core frequency)
continuously polls all 32 MDIO addresses
1,908 MSPS @ 256-FFT
in order to enumerate all PHY devices in FFT/DFT
1,683 MSPS @ 192-DFT
the system LTE – 582 Mbps @ 6144 block size, 6 iterations
Turbo decode
• Packet coprocessor that provides L2 to L4 WCDMA – 371 Mbps @ 5114 block size
classification functionalities and the Turbo encode
LTE – 2572 Mbps @ 6144 block size
processing power of up to 1.5 Gbps WCDMA – 2556 Mbps @ 5114 block size, 6 iterations
• Security accelerator block capable of Viterbi decoder >38 Mbps (K = 9) Mbps = 9)
wire-speed processing on 1-Gbps Ethernet Rake Search Accelerator 32-bit multiplication per cycle
traffic on IPSec, SRTP, and 3GPP air inter WCDMA despreading 256 AMR users supported @ eight fingers
face security protocols WCDMA spreading 256 users supported with two radio links and diversity
• Embedded Ethernet switch that allows Encryption/decryption IPSec 2.8 Gbps
multiple devices to be connected through LTE – DL 2.2Gbps, UL 1.1Gbps
BCP
SGMII, eliminating the need for a board level WCDMA – DL: 800 Mbps, UL 400 Mbps
Ethernet switch TCI6618’s coprocessors
The TCI6618 has twelve high-performance
embedded coprocessors to perform intensive As wireless radio standards evolve and decoder coprocessors (VCP2_A, VCP2_B,
signal processing functions common to wire- related implementations become standardized, VCP2_C, and VCP2_D), three third-generation
less base station applications. The result is each evolution of TI’s wireless SoC devices turbo decoder coprocessors (TCP3d_A,
increased overall system performance, yielding has included more and more radio accelera- TCP3d_B, and TCP3d_C), turbo encoder
40 percent spectral efficiency over conven- tion/coprocessing, and as such provides a coprocessor (TCP3e), three fast Fourier trans-
tional decoding techniques. compelling roadmap to lower power and costs form coprocessors (FFTC_A, FFTC_B, and
while delivering higher performing base station FFTC_C) and a bit rate coprocessor. Together,
Bit rate coprocessor for solutions for our customers. TI’s SoC strategy they significantly accelerate channel encod-
increased spectral efficiency of integrating DSP cores with coprocessors is ing/decoding operations. Also included in the
The bit rate coprocessor (BCP) is a multi- the simplest and most economical approach to TCI6618 are four tightly coupled rake/search
standard acceleration engine that offloads all wireless base station solutions and continues accelerators (RSAs) for code division multiple
bit rate processing in the wireless signal chain. to be the market-leading solution today. TI’s access (CDMA) assistance with chip-rate
The BCP contains the modulator, demodulator, coprocessors eliminate external FPGAs and processing.
interleaver/de-interleaver, turbo and convolu- ASICs that were previously needed to deliver the
tion encoding, rate matcher/rate de-matcher, performance needed for base stations, lowering Delivering full multicore
correlator for block code decoding, and CRC the system cost and design complexity. entitlement
engine. The BCP enables turbo interfer- The TCI6618 has multiple, dedicated TI’s TCI6618 is based on the KeyStone
ence cancellation for MIMO equalization and high-performance embedded coprocessors to multicore SoC architecture, the first of its
enables high-performance PUCCH format 2 perform intensive signal processing functions kind to provide full multicore entitlement. This
decoding. It offloads approximately 15 GHz common to wireless base station applications. provides non-blocking access to all process-
of CPU MIPS with a maximum LTE downlink The coprocessors are four enhanced Viterbi ing cores, peripherals, coprocessors, and I/
throughput of 2.2 Gbps and uplink through-
put of 1.1 Gbps. For WCDMA, the maximum
downlink throughput is 800 Mbps and uplink
Traffic manager

Navigator interface
throughput is 400 Mbps. These techniques,
coupled with the powerful MIMO processing DIO interface
128 bit packet streaming switch

capabilities of TI’s new DSP C66x cores, yield CRC

an SoC that delivers on the promise of 4G for
operators and users alike. Turbo encoder Correlator
Faster coprocessors for Rate dematching
optimized base station designs Rate-matcher DIO
HARQ combiner
Since 2001, TI has delivered radio coprocess-
ing functions that consist of configurable IP Interleaver De-interleaver
blocks to offload processing demands as well
as increase overall system performance. TI’s Modulator De-modulator
coprocessors also reduce base station power
requirements and dissipation as well as board
complexity, making new products easier to
design, build, and debug. BCP architecture

3
Os. Innovations that unleash full multicore and other IP blocks, eliminating memory management, segmentations and reassembly,
entitlement are: Multicore Navigator, TeraNet, contention. Shared memory access for code is and delivery across multiple cores and devices
Multicore Shared Memory Controller (MSMC), nearly identical in latency to local L2 access, are all supported by Multicore Navigator. Layer
and HyperLink. with highly effective prefetch mechanisms for 2 data-plane and transport-plane overhead
Multicore Navigator – TI’s Multicore Naviga- code and data. can be reduced by 10-15 times due to the
TI’s TCI6618’s DDR3 external memory inter- fast-path and zero-copy processing enabled
tor is an innovative packet-based manager
face (EMIF) is a 1,600-MHz, 64-bit bus with 8 by the Multicore Navigator.
that controls 8,192 queues and abstracts the
connections between the various subsystems GB of addressable memory space. Tied directly
to the MSMC, the DDR3 EMIF reduces latency Lowest power consumption
on the TCI6618. With a unified interface for
associated with external memory fetches for performance
communication, data transfer, and job man-
and provides the speed increase and support TI has a history of providing the lowest power
agement, Multicore Navigator enables higher
needed for larger applications that operate on wireless base station SoCs on the market. TI is
system performance with fewer interrupts and
large amounts of data, which is essential for able to achieve its ultimate low power through
reduced software complexity with a “fire and
advanced 3G and 4G base stations. the combination of its process technology,
forget” paradigm.
SmartReflex™ technology, and the proactive
Multicore Navigator instructs the next
HyperLink – HyperLink, with four lanes at up use of power management techniques (such
free DSP core to read the job and process it.
to 12.5 Gbps/lane, is a proprietary high-speed as adaptive voltage scaling) in every wireless
Multicore Navigator simplifies the software
interconnect that allows low protocol and base station semiconductor device to keep ac-
architecture and improves performance of
high-speed communication and connectivity tive power at a minimum. TI’s latest technology
base stations with: in the TCI6618 has brought the SoC power
to other KeyStone devices providing OEMs
• Dynamic resource/load sharing a seamless path to scalable solutions. The consumption for macro and compact base
• Offloading CPU overhead/delay related to HyperLink on the TCI6618 works in conjunc- stations down to the industry’s lowest levels at
inter-subsystem communications tion with the Multicore Navigator to dispatch 0.075 mW/GMAC of power.
• Hardware-based task prioritization tasks to multiple devices transparently, so
• Dynamic load balancing they execute as if they are running on local Complete tools and support
• Common communication methodology for resources. TI provides a full suite of best-in-class Eclipse-
all IP blocks (software, I/O, and accelerators) based development and debugging tools with
the TCI6618; these include a new C compiler,
TeraNet – TeraNet provides a hierarchal TCI6618 as Layer 2 and an assembly optimizer to simplify program-
switch fabric that combines to deliver more transport processing engine ming and scheduling, and a Windows debug-
than two terabits of bandwidth for data TCI6618 combines the unmatched PHY ger interface for visibility into source-code
transfer within the SoC. This virtually guaran- processing capabilities with dedicated copro- execution. TI’s compiler generates highly effi-
tees that the cores or coprocessors are never cessors for the Layer 2 and transport layer cient code that is “first-pass efficient” so there
starved for data and can deliver the entitled processing. This enables designers to create is less need to optimize it. TI’s debugging tools
processing horsepower. Because the switch base stations without a separate network pro- help developers visualize problems and resolve
fabric is hierarchical instead of flat crossbar, cessor, thereby reducing board complexity and them quickly, so designers can get products
overall power consumption is much lower cost without compromising performance. to the field faster while saving development
in idle states and also delivers systems with The network coprocessor enables fast-path resources. In addition, TI will offer a TCI6618
minimal latency, which is a key requirement in processing in the transport network layer and evaluation module (EVM) to help customers
next-generation base stations. deep into the Layer 2 of the radio network. prototype quickly with the TCI6618.
Multicore Shared Memory Controller Within the network coprocessor inside the
(MSMC) – TI’s TCI6618 includes a unique TCI6618, the Packet Accelerator and the For more information
memory architecture for enhanced per- Security Accelerator perform fully-accelerated To learn more about the TCI6618 SoC
formance. TI’s Multicore Shared Memory autonomous packet-to-packet processing. visit www.ti.com/tci6618. Discover how the
Controller (MSMC) allows the cores to directly They leverage the Multicore Navigator, which TCI6618 can add performance to your next
access shared memory without having to use uses a zero-copy approach to optimize data wireless base station design.
any TeraNet bandwidth. The MSMC arbitrates processing at all layers. Classification and or-
access to shared memory between the cores dering, multicore-accessible storage, memory

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