UNIT - III

SEQUENTIAL CIRCUITS

Sequential
Circuits

In sequential circuits, the output depends not only on the present input conditions but
also on the previous output conditions i.e. the past history of the inputs. The past history is
provided by the feedback from the output back to the input.

Flip-flops

The basic building block for sequential logic circuits is the flip-flop(FF). Flip-flop is a
bi-stable logic element with one or more inputs and two outputs. The outputs are complement
to each other. A flip-flop can store one bit of binary data „0‟ or „1‟. Flip-flops are used in
counters, shift registers and memory devices. There are six types of flip-flops:

1. SR Flip-flop
2. JK flip-flop
3. JK Master Slave flip-flop
4. D flip-flop and
5. T flip-flop

Flip-flop is a one bit memory cell. It can store one bit of information.

SR (or RS) flip-flop

It is also called Set/Reset flip-flop. The logic symbol of SR flip-flop is shown in

figure:

Figure : Symbol of SR flip-flop

The SR flip-flop has two inputs and two outputs. The inputs are S (Set) and R (Reset).
The outputs Q and 𝑄 are complements to each other. i.e. when Q = 0, 𝑄 will be 1 and when Q
= 1, 𝑄 will be 0. The logic diagram of SR flip-flop using NAND gates and the truth table are
shown in figure.

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 Figure : Logic diagram of SR flip-flop
Inputs Outputs
Condition
S R Q 𝑄
Previous Previous
0 0 No change
value value
0 1 0 1 Reset
1 0 1 0 Set
1 1 Forbidden Not used

Figure : Truth table of SR flip-flop

NAND gates 3 and 4 form the basic flip-flop circuit. The output of gate 3 (Q) is
connected as one of the input to gate 4. Similarly, the output of gate 4 (𝑄) is connected as one
of the input to gate 3. This feedback type of connection is called cross coupled connection.
NAND gates 1 and 2 are used as NOT gates for complementing S and R.

When S=1 and R=1, the outputs Q and 𝑄 will not change and the previous values are
retained. When S=0 and R=1, the output Q will become 0 and 𝑄 will become 1. This
condition is called RESET condition. i.e. the output Q is reset to zero. When S=1 and R=0,
the output Q will become 1 and 𝑄 will become 0. This condition is called SET condition. i.e.
the output Q is set to ONE.

But, when S=1 and R=1, both the outputs Q and 𝑄 will become 1. This is not allowed
in digital circuits because the outputs Q and 𝑄 are complement to each other. Hence, this
state is called forbidden state and we should not use the SR flip-flop with S=R=1.

JK Flip-flop

The NOT USED condition of SRFF i.e. S=1, R=1 condition is eliminated in the JK
flip-flop. The condition J=1, K=1 is used to toggle the flip-flop. Toggling means, when the
previous output is „0‟, the present output will be „1‟. Similarly, when the previous output is
„1‟, the present output will be‟0‟.

JK FF has three inputs J, K and CLK and two outputs Q and 𝑄. Preset (Pr) and Clear
(Cr) inputs are also provided in the JK FF. The logic symbol, logic circuit diagram and truth
table of JK FF are shown in figure.

Figure : Logic symbol of JK FF

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 Figure : Logic circuit diagram of JK FF

Inputs Outputs
Condition
CLK J K Q 𝑄
Previous Previous
0 0 No change
value value
0 1 0 1 Reset
1 0 1 0 Set
Complement Complement
1 1 of Previous of Previous Toggle
value value

Figure : Truth table of JK FF

When J=0 and K=0, there will be no change in the output. Q and 𝑄 will retain the
previous state. When J=0 & K = 1 and CLK = 1, Q will become „0‟ and 𝑄 will become „1‟,
This condition is called RESET condition. When J = 1 & K = 0 and CLK = 1, Q will become
„1‟ and 𝑄will become „0‟. This condition is called SET condition. When J =1 and K =1, the
output will toggle repeatedly on the arrival of the successive clock signal.

The PRESET and CLEAR inputs are used to set and clear the FF irrespective of the
application of clock pulse. The bubbles shown in Pr and Cr inputs represent the active low
inputs. That means the signal is active when it is „0‟. The FF will SET when Pr = 0 and
CLEAR when Cr = 0.

Racing problem

In JK flip-flop, when J = 1, K = 1 and when the clock pulse duration is more, the FF
will toggle many times (more than one time). Hence, we cannot estimate the final output.

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 This problem in JK FF is called racing problem and this condition is called race-
around condition. The racing problem can be avoided by using JK Master Slave (JK MS)
flip-flop or by using edge triggering techniques.

JK Master Slave (JKMS) flip-flop

The racing problem in JK FF can be avoided by using JKMS FF. The logic symbol of
JKMS FF is show in figure.

Figure : Logic symbol of JKMS FF

In JKMS FF there are two JKFFs, one Master JKFF and one Slave JKFF. The CLK
pulse of the master section is inverted and then given to the CLK input of the slave section.

Figure : JKMS FF using two JK FF

The logic circuit diagram and truth table of JKMS FF are shown in figure.

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 Figure : Logic circuit diagram of JKMS FF

Inputs Outputs
Condition
CLK J K Q 𝑄
Previous Previous
0 0 No change
value value
0 1 0 1 Reset

1 0 1 0 Set
Complement Complement
1 1 of Previous of Previous Toggle
value value

Figure : Truth table of JKMS FF

NAND gates 1, 2, 3 and 4 form the Master section and NAND gates 5, 6, 7 and 8
form the slave section. NOT gate is used to generate the inverted clock for the slave section.

When CLK = 1, the Master section in enabled and the outputs Q M and 𝑄M respond to
the inputs J and K. At this time, the Slave section is inhibited (not enabled) because the CLK
to the slave section is 0. When CLK goes LOW, the Master section is inhibited and the Slave
section is enabled, because its CLK input is HIGH. Therefore, the outputs Q and 𝑄 follow QM
and 𝑄M respectively. Hence, the slave section follows the master section.

The input to the gates 3 and 4 do not change during the clock pulse, therefore the
race-around condition does not exist. The state of the JKMS FF changes at the negative
transition (trailing edge) of the clock pulse. The Pr and Cr inputs are used to SET and
CLEAR the FF irrespective of the clock input.

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T Flip-flop

The T (Toggle) Flip-flop is formed by connecting the J and K inputs of JKMS FF

together. (or) In a JKMS FF, when we make J = K, we will get a T FF. This is shown in
figure.

Figure : Logic diagram of T FF

The truth table of T FF is shown in figure.

Inputs Outputs
Condition
CLK T Q 𝑄
Previous Previous
0 No change
value value
Complement Complement
1 of Previous of Previous Toggle
value value

Figure : Truth table of T FF

The T FF has only one input, called T input. When T = 1 (J =1 and K = 1), the output
Q toggles i.e. the complement of the previous output. When T = 0 (J = 0 and K = 0), the
output will remain unchanged. Pr and Cr inputs are used to SET and CLEAR the FF
irrespective of the clock signal.

T FF is also called „divide by 2‟ counter because the output signal frequency is half
of the clock signal frequency.

D Flip-flop

In a JK FF, when K is the complement of J by connecting a NOT gate between them

(K = 𝐽), we will get the D flip-flop. D FF has only one input D and two outputs Q and 𝑄. The
logic circuit and truth table of D FF are shown the figure.

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 Figure : Logic diagram of D FF

Inputs Outputs
Condition
CLK D Q 𝑄
0 0 1 Reset

1 1 0 Set
Figure : Truth table of D FF

When D = 0, J will become 0 and K will become 1, and after the clock pulse is
arrived, the output will be in RESET condition i.e. Q = 0 and 𝑄 = 1. When D = 1, J will
become 1 and K will become 0, and after the clock pulse is arrived, the output will be in SET
condition i.e. Q = 1 and 𝑄 = 0. It is clear that the FF stores the input value D.

D FF is called Data FF because this flip-flop can be used to store one bit. D FF is also
called Delay FF because the input is transferred to the output only after the arrival of the
clock pulse. . Pr and Cr inputs are used to SET and CLEAR the FF irrespective of the clock
signal.

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 Counters

The most important sequential circuits used in digital systems are

1) Counters and
2) Registers

A sequential logic circuit used for counting the number of pulses is known as a
counter. Counters are also used for measuring time and frequency.Flip-flops are the basic
elements used for designing the counter circuits. Basically there are two types of counters.
They are,

1. Asynchronous counter
2. Synchronous counter

Asynchronous counter

The asynchronous counter (ripple counter) is simple and straightforward in operation

and construction and requires minimum hardware. These counters are slow in operation. Each
flip-flop is triggered by the previous flip-flop and hence the counter has a cumulative settling
time. i.e. the flip-flops are connected in serial and hence these counters are also called serial
counters. In this type of counters, the triggers move through the flip-flop like a ripple in
water. Hence, these counters are also known as ripple counters.

Four bit binary asynchronous (ripple)UP counter

The logic diagram of 4-bit binary asynchronous UP counter is shown in figure. The
UP counter counts from 0000 to 1111.

Figure :Four bit binary asynchronous (ripple) UP counter

Four negative edge triggered JKMS flip-flops are used in this counter. J and K inputs
of all the FFs are connected to +5v (J =1, K = 1). This makes the FFs to operate as T (Toggle)
flip-flop. The T FF changes its state (i.e. from 0 to 1 or 1 to 0) for every input clock pulse.
The clock input is applied to the first flip-flop A. The Q output of the FF A is given as clock
input to the second flip-flop B. The Q output of FF B is given as clock input to the third flip-
flop C. The Q output of flip-flop C is given as clock input to the forth flip-flop D. The Q
output of all the flip-flops are taken as the counter outputs DCBA. The output A is called the

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Least Significant Bit (LSB) and the output D is called the Most Significant Bit (MSB). The
CLEAR (Cr) input of all the FFs are connected to ground through the Master Reset switch.

When the Master Reset switch is pressed, all the FFs are cleared and the counter
output DCBA is 0000. During the negative edge of the first clock pulse, FF A will be toggled
i.e. the output A changes from 0 to 1. At this time, the outputs of all other flip-flops will not
change.Hence, the counter output DCBA is 0001.

Input Output
Clock D C B A
Reset 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0

During the application of the second clock pulse, FF A will be toggled once again
from 1 to 0. This will give a negative edge triggering pulse to FF B and hence FF B also
toggles from 0 to 1. The counter output DCBA will become 0010.

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 Similarly, FF C will toggle when the output of FF B toggles from 1 to 0 and FF D will
toggle when the output of FF C toggles from 1 to 0. It should be noted that FF A toggles for
every clock pulse, FF B toggles for every two clock pulses, FF C toggles for every 4 clock
pulses and FF D toggles for every eight clock pulses. The frequency of output A is ½ of the
clock frequency, output B is ¼ of clock, output C is 1/8 of clock and output D is 1/16 of
clock frequency. Hence, the four bit counter acts as a „divided by 16‟ counter.

For the 15th clock pulse, the output is 1111. When the next (16 th) clock pulse is
applied, all the flip-flops will toggle from 1 to 0 at the same time and hence the output is
0000.The outputs of the counter during the application of each clock pulse are shown in the
truth table and also in the waveforms.

Four bit binary asynchronous (ripple) DOWN counter

The logic diagram of 4-bit binary asynchronous DOWN counter is shown in figure.
The DOWN counter counts from 1111 to 0000.

Figure :Four bit binary asynchronous (ripple) DOWN counter

Four negative edge triggered JKMS flip-flops are used in this counter. J and K inputs
of all the FFs are connected to +5v (J =1, K = 1). This makes the FFs to operate as T (Toggle)
flip-flop. The T FF changes its state (i.e. from 0 to 1 or 1 to 0) for every input clock pulse.
The clock input is applied to the first flip-flop A. The 𝑄 output of the FF A is given as clock
input to the second flip-flop B. The 𝑄 output of FF B is given as clock input to the third flip-
flop C. The 𝑄 output of flip-flop C is given as clock input to the fourth flip-flop D. The Q
output of all the flip-flops are taken as the counter outputs DCBA. The output A is called the
Least Significant Bit LSB) and the output D is called the Most Significant Bit (MSB). The
CLEAR (Cr) input of all the FFs are connected to ground through the Master Reset switch.

When the Master Reset switch is pressed, all the FFs are cleared and the counter
output DCBA is 0000. During the negative edge of the first clock pulse, FF A will be toggled
i.e. the Q output of A changes from 0 to 1 and 𝑄 output of A changes from 1 to 0. Hence,
flip-flop B also toggles. Similarly flip-flops C and D also toggle. Hence, the counter output
DCBA is 1111.

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 Input Output
Clock D C B A
Reset 0 0 0 0
1 1 1 1 1
2 1 1 1 0
3 1 1 0 1
4 1 1 0 0
5 1 0 1 1
6 1 0 1 0
7 1 0 0 1
8 1 0 0 0
9 0 1 1 1
10 0 1 1 0
11 0 1 0 1
12 0 1 0 0
13 0 0 1 1
14 0 0 1 0
15 0 0 0 1
16 0 0 0 0

During the application of the second clock pulse, the Q output of FF A will toggled
once again from 1 to 0 and 𝑄 from 0 to 1. Hence, FF B will not toggle this time. The counter
output DCBA will become 1110.

During the third clock pulse, the Q output of FF A will toggle once again from 0 to 1
and 𝑄 from 1 to 0. Hence, FF B will toggle this time. The counter output DCBA will become
1101. Similarly, FF C will toggle when the 𝑄 output of FF B toggles from 1 to 0 and FF D
will toggle when the 𝑄 output of FF C toggles from 1 to 0. It should be noted that FF A
toggles for every clock pulse, FF B toggles for every two clock pulses, FF C toggles for every
4 clock pulses and FF D toggles for every eight clock pulses. The frequency of output A is ½
of the clock frequency, output B is ¼ of clock, output C is 1/8 of clock and output D is 1/16
of clock frequency. Hence, the four bit counter acts as a „divided by 16‟ counter.The outputs
of the counter during the application of each clock pulse are shown in the truth tableand also
in the waveforms.

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Four bit binary asynchronous (ripple) UP / DOWN counter

The logic circuit diagram of 4-bit binary asynchronous UP / DOWN counter is shown
in figure.

Figure :Four bit binary asynchronous (ripple) UP / DOWN counter

We know that in UP counter, the Q output of each flip-flop is given as clock input for
the next FF. For the DOWN counter, the 𝑄 output each flip-flop is given as clock input for
the next FF. A combinational circuit using AND and OR gates is used to select the Q or 𝑄
output. When the COUNT UP line is made 1, the upper AND gate is enabled and Q will go
as clock input to the next FF. When the COUNT DOWN line is made 1, the lower AND gate
is enabled and 𝑄 will go as clock input to the next flip-flops.
Four bit binary synchronous UP counter

The logic diagram of 4-bit binary synchronous UP counter is shown in figure. The UP
counter counts from 0000 to 1111. The synchronous counters are fast in operation but require
more hardware.

Figure : Four bit binary synchronous UP counter

Four JKMS flip-flops are used in this counter. J and K inputs of all the FFs are
connected to +5v (J =1, K = 1). This makes the FFs to operate as T (Toggle) flip-flop. The T
FF changes its state (i.e. from 0 to 1 or 1 to 0) for every input clock pulse. The clock input is
applied to all the flip-flops. The gate circuits are arranged in such a way that FF A toggles for
every clock pulse, FF B toggles for every two clock pulses, FF C toggles for every four clock
pulses and FF D toggles for every eight clock pulses. The Q output of all the flip-flops are
taken as the counter outputs ABCD.The output A is called the Least Significant Bit (LSB)
and the output D is called the Most Significant Bit (MSB). The truth table of the counter is
shown in figure.
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Input Output
Clock D C B A
Reset 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0

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 From the truth table we may observe that the output A toggles in every clock pulse,
output B toggles when output A is 1, output C toggles when both A and B are 1, output C
toggles when A, B and C are 1. This can be achieved by using AND gates as shown in the
figure. Toggle input of FF A is directly connected to +5v, hence, FF A toggles for every
clock pulse. The Q output of the FF A is connected to the Toggle input of FF B, hence, FF B
toggles only when A is 0. The output of AND gate 1, whose inputs are A and B, is connected
to the Toggle input of FF C, hence, FF C toggles only when Aand B are 1. Similarly, the
output of AND gate 2, whose inputs are the output of AND gate 1 and C, is connected to the
Toggle input of FF D, hence, FF D toggles only when A, B and C are 1.

The frequency of output A is ½ of the clock frequency, output B is ¼ of clock, output

C is 1/8 of clock and output D is 1/16 of clock frequency. Hence, the four bit counter acts as a
„divided by 16‟ counter.For the 15th clock pulse, the output is 1111. When the next (16 th)
clock pulse is applied, all the flip-flops will toggle from 1 to 0 at the same time and hence the
output is 0000. The outputs of the counter during the application of each clock pulse are
shown in the waveforms.

Four bit binary synchronous DOWN counter

The logic diagram of 4-bit binary synchronous UP counter is shown in figure. The
DOWN counter counts from 1111 to 0000. The synchronous counters are fast in operation
but require more hardware.

Figure : Four bit binary synchronous DOWN counter

Four JKMS flip-flops are used in this counter. J and K inputs of all the FFs are
connected to +5v (J =1, K = 1). This makes the FFs to operate as T (Toggle) flip-flop. The T
FF changes its state (i.e. from 0 to 1 or 1 to 0) for every input clock pulse. The clock input is
applied to all the flip-flops. The gate circuits are arranged in such a way that FF A toggles for

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every clock pulse, FF B toggles for every two clock pulses, FF C toggles for every four clock
pulses and FF D toggles for every eight clock pulses. The Q output of all the flip-flops are
taken as the counter outputs ABCD. The output A is called the Least Significant Bit (LSB)
and the output D is called the Most Significant Bit (MSB). The truth table of the counter is
shown in figure.

Input Output
Clock D C B A
Reset 0 0 0 0
1 1 1 1 1
2 1 1 1 0
3 1 1 0 1
4 1 1 0 0
5 1 0 1 1
6 1 0 1 0
7 1 0 0 1
8 1 0 0 0
9 0 1 1 1
10 0 1 1 0
11 0 1 0 1
12 0 1 0 0
13 0 0 1 1
14 0 0 1 0
15 0 0 0 1
16 0 0 0 0

From the truth table we may observe that the output A toggles in every clock pulse,
output B toggles when output A is 0, output C toggles when both A and B are 0, output C
toggles when A, B and C are 0. This can be achieved by using AND gates as shown in the
figure. Toggle input of FF A is directly connected to +5v, hence, FF A toggles for every
clock pulse. The 𝑄A output of the FF A is connected to the Toggle input of FF B, hence, FF B
toggles only when A is 0. The output of AND gate 1, whose inputs are 𝑄A and𝑄B, is
connected to the Toggle input of FF C, hence, FF C toggles only when A and B are 0.
Similarly, the output of AND gate 2, whose inputs are the output of AND gate 1 and 𝑄C, is
connected to the Toggle input of FF D, hence, FF D toggles only when A, B and C are 0.

The frequency of output A is ½ of the clock frequency, output B is ¼ of clock, output

C is 1/8 of clock and output D is 1/16 of clock frequency. Hence, the four bit counter acts as
a
„divided by 16‟ counter.For the 15th clock pulse, the output is 0000. When the next (16 th)
clock pulse is applied, all the flip-flops will toggle from 0 to 1 at the same time and hence the

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 output is 1111. The outputs of the counter during the application of each clock pulse are
shown in the waveforms.

Four bit binary synchronous UP/DOWN counter

The logic diagram of 4-bit binary synchronous UP/DOWN counter is shown in figure.
The UP counter counts from 0000 to 1111. The DOWN counter counts from 1111 to 0000.
The synchronous counters are fast in operation but require more hardware.

Figure : Four bit binary synchronous UP/DOWN counter

Four JKMS flip-flops are used in this counter. J and K inputs of all the FFs are
connected to +5v (J =1, K = 1). This makes the FFs to operate as T (Toggle) flip-flop. The T
FF changes its state (i.e. from 0 to 1 or 1 to 0) for every input clock pulse. The clock input is
applied to all the flip-flops. The gate circuits are arranged in such a way that FF A toggles for
every clock pulse, FF B toggles for every two clock pulses, FF C toggles for every four clock
pulses and FF D toggles for every eight clock pulses.

UP function :

For UP function, the Q output of previous FF must be connected to the Toggle input
of next FF. This is achieved by the AND gates 1, 2 and 3 and the OR gates. The UP function
is enabled by connecting Up/𝐷𝑜𝑤𝑛 input to +5V (logic 1). Now, the counter functions as UP
counter.

DOWN function :

For DOWN function, the 𝑄 output of the previous FF must be connected to the
Toggle input of next FF using the AND gates 4, 5 and 6 and the OR gates. The DOWN
function is selected by connecting the Up/𝐷𝑜𝑤𝑛 input to GND (logic 0). Now, the counter
functions as DOWN counter.

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