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K L Deemed to be University
Department of Electronics and Communication Engineering -- KLVZA
Course Handout
2023-2024, Even Sem
Course Title :DIGITAL DESIGN AND COMPUTER ARCHITECTURE
Course Code :23EC1202
L-T-P-S Structure : 3-0-2-0
Pre-requisite :
Credits :4
Course Coordinator :TAMMINENI SREELATHA
Team of Instructors :
Teaching Associates :
Syllabus :CO 1: Combinational Digital Logic Circuits: Boolean Algebra, Digital Logic SOP/POS representation and
optimization techniques. Adders, Subtractors, Multiplexers, De-Multiplexers, Decoder, Encoder, Concept of Reversible
Gates. Programmable Logic Devices: PROM, PAL, and PLA design. Implementation of CPLD (Macrocells) and FPGA
(CLB/LUT) based digital logic modules and their applications. CO-2: Design of Sequential and Memory Circuits:
Latches and Flip-Flops, Modeling of memory ,registers and Shift registers, Timing and sequence control modules using
Asynchronous/Synchronous counters, Ring and Johnson counter as timing and control units. Random Access Memory
(RAM) and Memory decoding. CO-3: Basic Computer Architecture and Instructions: Features of Micro Computer,
Operands, Addressing modes, Instruction formats, Machine cycle, Instruction sets, subroutine call and return
mechanisms. Instruction set architectures - CISC and RISC architectures. Hardwired realization vs micro-programmed
realization, multi-cycle implementation, Instruction level parallelism, instruction pipelining and pipeline hazards. CO-4:
Memory Architecture and I/O Organization Storage systems, introduction to memory hierarchy: importance of temporal
and spatial locality; main memory organization, cache memory: address mapping, block size, replacement, and store
policies. Virtual Memory System: page table and TLB. External storage; IO fundamentals: handshaking, buffering,
programmed IO, interrupt driven IO.
Text Books :1. Computer System Architecture by M. Moris Mano, 3rd edition published by Pearson/PHI 2.
Fundamentals of Digital Logic with Verilog HDL by Stephen Brown and ZvonkoVranesic, 3rd edition, Published by Mc
Graw Hill
Reference Books :1. Computer Organization and Design by DA Patterson and JL Hennessy,4th edition published by
Morgan Kaufmann Publisher 2. Computer Organization and Architecture, by W. Stalling published by PHI.
Web Links :[1]. https://nptel.ac.in/courses/117106086 [2]. https://archive.nptel.ac.in/courses/106/105/106105163/
MOOCS :[1]. https://www.edx.org/learn/design/harvey-mudd-college-digital-design [2]. https://ocw.mit.edu/courses/6-
823-computer-system-architecture-fall-2005/ [3]. https://www.coursera.org/learn/digital-systems

COURSE OUTCOMES (COs):

Blooms
CO Taxonomy
Course Outcome (CO) PO/PSO
NO Level
(BTL)
Build the combinational and programmable digital logic circuits using
CO1 PSO1,PO1,PO2 3
logic gates and optimization methods
CO2 Construct the sequential and memory circuits using flip-flops PSO1,PO1,PO2 3
CO3 Able to organize computer architecture and instructions sequence PSO1,PO1,PO2 3
CO4 Model the Memory Architecture and I/O Organization modules PO2,PSO1,PO1 3
Develop and analyze of computer architecture modules using basic
CO5 PSO1,PO1,PO3,PO5 4
combinational, sequential and memory logics

COURSE OUTCOME INDICATORS (COIs)::

Outcome Highest
COI-1 COI-2
No. BTL

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Btl-2
Btl-3
This course provides a comprehensive
Understanding this course delves into the realm
introduction to digital logic design and Boolean
of Programmable Read-Only Memory (PROM),
algebra, covering fundamental concepts,
Programmable Array Logic (PAL), and
CO1 3 representation techniques, and optimization
Programmable Logic Array (PLA), exploring
strategies. Students will gain a deep
their design principles and applications. Students
understanding of the building blocks of digital
will gain a comprehensive understanding of these
systems and learn how to design and optimize
devices and their role in modern digital systems.
circuits for various applications.
Btl-2 Btl-3
This course empowers the knowledge by Studying The study of Ring and Johnson counters provides
latches, flip-flops, memory modeling, and register insights into advanced sequential control
design provides essential knowledge for creating mechanisms, improving students' understanding
CO2 3 digital circuits with effective data storage. of precise timing in digital systems. Exploring
Exploring timing controls using Random Access Memory (RAM) and Memory
asynchronous/synchronous counters ensures decoding enhances their knowledge of efficient
accurate sequencing, while understanding shift data storage and retrieval, contributing to the
registers enables serial data manipulation. optimization of digital circuits.
Btl-2
Btl-3
Understanding an in-depth exploration of
This course explores Instruction Set Architectures
microcomputer architecture and programming,
(ISAs), covering Complex Instruction Set
covering essential features, addressing modes,
Computing (CISC) and Reduced Instruction Set
instruction formats, machine cycles, and
CO3 3 Computing (RISC). Topics include hardwired
subroutine call and return mechanisms. Students
versus micro-programmed realization, multi-
will gain a comprehensive understanding of the
cycle implementations, and advanced concepts
fundamental components that constitute a
like instruction-level parallelism, instruction
microcomputer system and the intricacies of
pipelining, and pipeline hazard mitigation.
programming at the machine level.
Btl-3
The study of virtual memory system,
Btl-2
emphasizing page tables and TLBs for
Understanding the storage systems and memory
streamlined virtual-to-physical memory mapping.
hierarchy, students delve into the hierarchical
The course further covers external storage and IO
organization of computer memory. Emphasizing
CO4 3 fundamentals, including handshaking, buffering,
the significance of temporal and spatial locality,
programmed IO, and interrupt-driven IO. This
this provides students with a thorough
provides a comprehensive grasp of organizational
understanding of the principles governing
elements in virtual memory systems and
efficient data retrieval in computer architecture.
principles governing Input/Output operations in
computer architecture.
Btl-4
Students analyze practical applications in digital
electronics, including tasks like LED control, car
security system design, and participant selection
using multiplexers. They also analyze projects
CO5 4 involving digital displays, random number
generators, and computational processing
systems. These hands-on activities offer a
valuable opportunity for students to analyze and
understand the diverse applications of digital
electronics in real-world scenarios.

PROGRAM OUTCOMES & PROGRAM SPECIFIC OUTCOMES (POs/PSOs)

Po
Program Outcome
No.
Engineering Knowledge:Apply the knowledge of mathematics, science, engineering fundamentals, and an
PO1
engineering specialization to the solution of complex engineering problems.
Problem Analysis: Identify, formulate, review research literature, and analyse complex engineering problems
PO2
reaching substantiated conclusions using first principles of mathematics, natural sciences and engineering sciences
Design/Development of Solutions: Design solutions for complex engineering problems and design system
PO3 components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations
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Conduct Investigations of Complex Problems:Use research-based knowledge and research methods including
design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid
PO4
conclusions for complex problems that cannot be solved by straightforward application of knowledge, theories and
techniques applicable to the engineering discipline.
Modern Tool Usage:Create, select, and apply appropriate techniques, resources, and modern engineering and IT
PO5 tools including prediction and modelling to complex engineering activities with an understanding of the
limitations.
The Engineer and Society:Apply reasoning informed by the contextual knowledge to assess societal, health,
PO6 safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.
Environment and Sustainability:Understand the impact of the professional engineering solutions in societal and
PO7
environmental contexts, and demonstrate the knowledge of, and need for sustainable development
Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
PO8
engineering practice
Individual and Team Work: Function effectively as an individual, and as a member or leader in diverse teams, and
PO9
in multidisciplinary settings.
Communication:Communicate effectively on complex engineering activities with the engineering community and
PO10 with society at large, such as, being able to comprehend and write effective reports and design documentation,
make effective presentations, and give and receive clear instructions
Project Management and Finance: Demonstrate knowledge and understanding of the engineering and management
PO11 principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.
Life-long Learning: Recognize the need for, and have the preparation and ability to engage in independent and
PO12
lifelong learning in the broadest context of technological change.
An ability to solve Electronics engineering problems, using latest hardware and software tools, to obtain
PSO1
appropriate solutions in the domain of embedded systems and Internet of things.
PSO2 Ability to design web applications by applying the knowledge of cyber security.

Lecture Course DELIVERY Plan:

Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods

COI- End Semester Exam,SEM-

1 CO1 Course Handout NA Chalk,PPT,Talk
1 EXAM1,SEM-EXAM2

T BOOK [1],
COI- End Semester Exam,SEM-
2 CO1 Introduction, Boolean Algebra CH 2, Page no Chalk,PPT,Talk
1 EXAM1
1-24

Digital Logic SOP/POS T BOOK [1],

COI- ALM,End Semester
3 CO1 representation and optimization CH 2, Page no Chalk,PPT,Talk
1 Exam,SEM-EXAM1
techniques 25-37

T BOOK [1],
COI- End Semester Exam,SEM-
4 CO1 Adders, Subtractors CH 2, Page no Chalk,PPT,Talk
1 EXAM1
38-42

T BOOK [1],
COI- End Semester Exam,Home
5 CO1 Multiplexers, De-Multiplexers CH 6, Page no Chalk,PPT,Talk
1 Assignment,SEM-EXAM1
303-314

T BOOK [1],
COI- End Semester Exam,SEM-
6 CO1 Decoder, Encoder CH 2, Page no Chalk,PPT,Talk
1 EXAM1
314-317

T BOOK [1],
COI- End Semester Exam,SEM-
7 CO1 Introduction to PLD's, PROM CH 2, Page no Chalk,PPT,Talk
2 EXAM1
87-92

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Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods

T BOOK [1],
COI- End Semester Exam,Home
8 CO1 PAL and PLA design CH 2, Page no Chalk,PPT,Talk
2 Assignment,SEM-EXAM1
47-49

Implementation of CPLD T BOOK [1],

COI- ALM,End Semester
9 CO1 (Macrocells) based digital logic CH 2, Page no Chalk,PPT,Talk
2 Exam,SEM-EXAM1
modules and their applications 92-101

T BOOK [1],
COI- FPGA (CLB/LUT) based digital ALM,End Semester
10 CO1 CH 2, Page no Chalk,PPT,Talk
2 logic modules and their applications Exam,SEM-EXAM1
102-108

T BOOK [1],
COI- End Semester Exam,SEM-
11 CO1 Concept of Reversible Gates CH 2, Page no Chalk,PPT,Talk
2 EXAM1
62-63

T BOOK [1],
COI- Introduction to sequential circuits, End Semester Exam,SEM-
12 CO2 CH 2, Page no Chalk,PPT,Talk
1 Latches EXAM1
497-499

T BOOK [1],
COI- End Semester Exam,SEM-
13 CO2 Flip-Flops CH 2, Page no Chalk,PPT,Talk
1 EXAM1
499-502

T BOOK [1],
COI- End Semester Exam,SEM-
14 CO2 Modeling of memory and registers CH 2, Page no Chalk,PPT,Talk
1 EXAM1
68-71

T BOOK [1],
COI- ALM,End Semester
15 CO2 Shift registers CH 5, Page no Chalk,PPT,Talk
1 Exam,SEM-EXAM1
160 - 165

Timing and sequence control T BOOK [1],

COI- End Semester Exam,SEM-
16 CO2 modules using Asynchronous CH 5, Page no Chalk,PPT,Talk
2 EXAM1
counters 155

Timing and sequence control T BOOK [1],

COI- End Semester Exam,SEM-
17 CO2 modules using Synchronous CH 5, Page no Chalk,PPT,Talk
2 EXAM1
counters 156

T BOOK [1],
COI- Ring counter as timing and control End Semester Exam,Home
18 CO2 CH 5, Page no Chalk,PPT,Talk
2 units Assignment,SEM-EXAM1
157-158

T BOOK [1],
COI- Johnson counter as timing and ALM,End Semester
19 CO2 CH 5, Page no Chalk,PPT,Talk
2 control units Exam,SEM-EXAM1
159-161

T BOOK [1],
COI- End Semester Exam,Home
20 CO2 Random Access Memory (RAM) CH 5, Page no Chalk,PPT,Talk
2 Assignment,SEM-EXAM1
609 - 610

T BOOK [1],
COI- End Semester Exam,SEM-
21 CO2 Memory decoding CH 5, Page no Chalk,PPT,Talk
2 EXAM1
611

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Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods

T BOOK [1],
COI- Introduction, Features of Micro End Semester Exam,SEM-
22 CO3 CH 5, Page no Chalk,PPT,Talk
1 Computer EXAM2
123 - 126

T BOOK [1],
COI- Operands, Addressing modes, End Semester Exam,Home
23 CO3 CH 5, Page no Chalk,PPT,Talk
1 Instruction formats Assignment,SEM-EXAM2
186 - 190

T BOOK [1],
COI- ALM,End Semester
24 CO3 Machine cycle, Instruction sets CH 7, Page no Chalk,PPT,Talk
1 Exam,SEM-EXAM2
174-179

T BOOK [1],
COI- subroutine call and return End Semester Exam,SEM-
25 CO3 CH 7, Page no Chalk,PPT,Talk
1 mechanisms EXAM2
213-220

T BOOK [1],
COI- Instruction set architectures - CISC ALM,End Semester
26 CO3 CH 7, Page no Chalk,PPT,Talk
2 and RISC architectures Exam,SEM-EXAM2
262

T BOOK [1],
COI- Hardwired realization vs micro- End Semester Exam,SEM-
27 CO3 CH 7, Page no Chalk,PPT,Talk
2 programmed realization EXAM2
282-285

T BOOK [1],
COI- End Semester Exam,SEM-
28 CO3 Multi-cycle implementation CH 7, Page no Chalk,PPT,Talk
2 EXAM2
286-288

T BOOK [1],
COI- End Semester Exam,SEM-
29 CO3 Instruction level parallelism CH 9, Page no Chalk,PPT,Talk
2 EXAM2
310-315

T BOOK [1],
COI- Instruction pipelining and pipeline End Semester Exam,Home
30 CO3 CH 9, Page no Chalk,PPT,Talk
2 Hazards Assignment,SEM-EXAM2
316-320

T BOOK [1],
COI- End Semester Exam,SEM-
31 CO4 Introduction, Storage systems CH 12, Page no Chalk,PPT,Talk
1 EXAM2
445

Introduction to memory hierarchy: T BOOK [1],

COI- End Semester Exam,Home
32 CO4 Importance of temporal and spatial CH 12, Page no Chalk,PPT,Talk
1 Assignment,SEM-EXAM2
locality 446-448

T BOOK [2],
COI- ALM,End Semester
33 CO4 Main memory organization CH 12, Page no Chalk,PPT,Talk
1 Exam,SEM-EXAM2
448-452

T BOOK [2],
COI- Cache memory: address mapping, End Semester Exam,SEM-
34 CO4 CH 12, Page no Chalk,PPT,Talk
1 Block size EXAM2
462-465

T BOOK [2],
COI- End Semester Exam,SEM-
35 CO4 Replacement, and Store policies CH 12, Page no Chalk,PPT,Talk
1 EXAM2
466-469

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Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods

T BOOK [2],
COI- Virtual memory system: page table End Semester Exam,Home
36 CO4 CH 12, Page no Chalk,PPT,Talk
1 and TLB Assignment,SEM-EXAM2
469-476

T BOOK [2],
COI- End Semester Exam,SEM-
37 CO4 External storage CH 12, Page no Chalk,PPT,Talk
1 EXAM2
478

T BOOK [2],
COI- IO fundamentals: handshaking, ALM,End Semester
38 CO4 CH 11, Page no Chalk,PPT,Talk
2 buffering Exam,SEM-EXAM2
392-396

T BOOK [2],
COI- End Semester Exam,SEM-
39 CO4 Programmed IO, Interrupt driven IO CH 11, Page no Chalk,PPT,Talk
2 EXAM2
402-407

Lecture Session wise Teaching – Learning Plan

SESSION NUMBER : 1

Session Outcome: 1 Course Introduction Session

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
--- NOT
Discussion on Course Objectives, Course Outcomes and Course
20 2 PPT APPLICABLE -
outcome Indicators.
--
--- NOT
20 Discussion on Evaluation Plan 2 PPT APPLICABLE -
--
--- NOT
5 Summary & Conclusion 2 Talk APPLICABLE -
--

SESSION NUMBER : 2

Session Outcome: 1 Student gains foundational knowledge in computer science, digital logic, and mathematical
principles essential for understanding the inner workings of computers.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 1 Talk APPLICABLE -
--
Sketching &
20 Introduction 2 PPT
Drawing
Sketching &
20 Boolean Algebra 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

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SESSION NUMBER : 3

Session Outcome: 1 Student gets knowledge and skills in representing Boolean expressions, optimizing digital circuits for
efficiency

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Sketching &
20 Digital Logic SOP/POS representation 2 PPT
Drawing
Sketching &
20 Optimization techniques 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 4

Session Outcome: 1 Students explore building blocks like half and full adders,subtractors, and grasp the application of
these circuits in Arithmetic Logic Units (ALUs) and digital signal processing.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE -
--
Sketching &
20 Half Adder, Full adder 2 PPT
Drawing
Sketching &
20 Half subtractor, Full subtractor 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 5

Session Outcome: 1 Student gains the knowledge of versatile components used in digital systems for data routing, signal
selection, and circuit expansion.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Sketching &
20 Multiplexers 2 PPT
Drawing
Sketching &
20 De-Multiplexers 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 6

Session Outcome: 1 Student understands the elements of essential components used for encoding and decoding
information in various digital systems.

Time(min) Topic BTL Teaching- Active

Learning Learning

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Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Sketching &
20 Decoder 2 PPT
Drawing
Sketching &
20 Encoder 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 7

Session Outcome: 1 Student gets the foundational understanding of programmable logic devices and programmable
memory components.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
Sketching &
20 Introduction to PLD's 3 PPT
Drawing
Sketching &
20 PROM 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 8

Session Outcome: 1 Student gains deep understanding of two important types of programmable logic devices.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
Sketching &
20 Programmable Array Logic (PAL) 3 PPT
Drawing
Sketching &
20 programmable logic array (PLA) 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 9

Session Outcome: 1 Students gain experience in designing and implementing digital logic circuits using CPLD
macrocells.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
Sketching &
20 CPLD Structure 3 PPT
Drawing

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Sketching &
20 Implementation of CPLD (Macrocells) 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 10

Session Outcome: 1 Students acquire skills in designing and implementing digital logic circuits using FPGA CLBs/LUTs.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
Sketching &
20 FPGA Structure 3 PPT
Drawing
Sketching &
20 Implementation of FPGA based digital logic modules 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 11

Session Outcome: 1 Students gets a unique perspective on information conservation and reversibility in computation.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
Sketching &
20 Types of Reversible Gates 3 PPT
Drawing
Sketching &
20 Operation of Reversible Gates 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 12

Session Outcome: 1 Students gain a foundational understanding of sequential circuits and latches, essential components
in digital systems.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE -
--
Problem-Based
20 Sequential circuits - Introduction 2 PPT
Learning
Problem-Based
20 Concept of latches 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 13

Session Outcome: 1 Students develop a comprehensive understanding of flip-flops and its types, a crucial element in
sequential circuit design.
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Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
Problem-Based
5 Attendance 2 PPT
Learning
Problem-Based
20 Concept of flip-flops 2 PPT
Learning
Problem-Based
20 Types of flip-flops 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 14

Session Outcome: 1 Students will gain practical knowledge applicable to digital system design and embedded systems.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Problem-Based
20 Modeling of memory 2 PPT
Learning
Problem-Based
20 Registers 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 15

Session Outcome: 1 Students gains practical skills applicable to various fields such as digital electronics, communication
systems, and embedded systems.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Problem-Based
20 Types of Shift registers 2 PPT
Learning
Problem-Based
20 Operation of shift Registers 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 16

Session Outcome: 1 Students able to understand Timing and sequence control modules using Asynchronous counters.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
20 Asynchronous counters 3 PPT Design Thinking
20 Asynchronous counters - Timing and sequence control modules 3 PPT Design Thinking
5 Summary & Conclusion 3 PPT Design Thinking

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SESSION NUMBER : 17

Session Outcome: 1 Students able to understand Timing and sequence control modules using synchronous counters.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
20 Synchronous counters 3 PPT Design Thinking
20 Synchronous counters - Timing and sequence control modules 3 PPT Design Thinking
5 Summary & Conclusion 3 PPT Design Thinking

SESSION NUMBER : 18

Session Outcome: 1 Students able to understand Ring counter as timing and control units

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
20 Description - Ring counter 3 PPT Design Thinking
20 Operation of Ring counter 3 PPT Design Thinking
5 Summary & Conclusion 3 PPT Design Thinking

SESSION NUMBER : 19

Session Outcome: 1 students can gain insights into the practical application of Johnson counters in digital systems,
particularly in the critical areas of timing and control.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
20 Introduction - Johnson counter 3 PPT Design Thinking
20 Operation - Johnson counter 3 PPT Design Thinking
5 Summary & Conclusion 3 PPT Design Thinking

SESSION NUMBER : 20

Session Outcome: 1 Students acquire knowledge of Random Access Memory (RAM), a fundamental component in
computer systems, enhancing their understanding of memory hierarchies and computer architecture principles.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
20 Random Access Memory (RAM) - Introduction 3 PPT Design Thinking
Application of Random Access Memory (RAM) in computer
20 3 PPT Design Thinking
architecture
5 Summary & Conclusion 3 PPT Design Thinking

SESSION NUMBER : 21

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Session Outcome: 1 Students master memory decoding, a critical skill in digital systems, enabling efficient utilization of
memory resources.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE -
--
20 Memory decoding introduction 2 PPT Design Thinking
20 Application of Memory decoding in computer architecture 2 PPT Design Thinking
5 Summary & Conclusion 2 PPT Design Thinking

SESSION NUMBER : 22

Session Outcome: 1 Students will acquire a comprehensive understanding of microcomputers, enabling them to work
effectively with these ubiquitous computing devices.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
One minute
20 Introduction of computer architecture 2 PPT
paper
One minute
20 Features of Micro Computer 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 23

Session Outcome: 1 Students can understand how instructions are structured and executed in a computer system.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 1 Talk APPLICABLE -
--
One minute
10 Operands 2 PPT
paper
One minute
20 Addressing modes 2 PPT
paper
One minute
10 Instruction formats 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 24

Session Outcome: 1 Students will develop a strong foundation in the principles of machine cycles and instruction sets.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--

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One minute
20 Machine cycle 2 PPT
paper
One minute
20 Instruction sets 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 25

Session Outcome: 1 students gain a deep understanding of how modular programming is achieved, enabling them to write
efficient, organized, and maintainable code.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
One minute
20 Types of subroutines 2 PPT
paper
One minute
20 subroutine call and return mechanisms 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 26

Session Outcome: 1 Students gain insights into the design principles that shape modern processors.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
One minute
5 Attendance 3 PPT
paper
One-Minute
20 CISC architecture 3 PPT
Paper
One-Minute
20 RISC architecture 3 PPT
Paper
One-Minute
5 Summary & Conclusion 3 PPT
Paper

SESSION NUMBER : 27

Session Outcome: 1 Students comprehend the trade-offs between hardwired realization and micro-programmed
realization, gaining insights into the design choices

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
One-Minute
20 Hardwired realization 3 PPT
Paper
One-Minute
20 micro-programmed realization 3 PPT
Paper
One-Minute
5 Summary & Conclusion 3 PPT
Paper

SESSION NUMBER : 28

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Session Outcome: 1 Students grasp multi-cycle implementation, enhancing their ability to design efficient and optimized
digital circuits.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE -
--
One-Minute
20 Concept of Multi-cycle implementation 3 PPT
Paper
One-Minute
20 Application of Multi-cycle implementation 3 PPT
Paper
One-Minute
5 Summary & Conclusion 3 PPT
Paper

SESSION NUMBER : 29

Session Outcome: 1 Students studying ILP gain insights into the challenges, methods, and trade-offs involved in
achieving efficient instruction-level parallelism in modern computing systems.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
One minute
20 Instruction level Pipelining 3 PPT
paper
One minute
20 Instruction level parallelism 3 PPT
paper
One minute
5 Summary & Conclusion 3 PPT
paper

SESSION NUMBER : 30

Session Outcome: 1 Students gain insights into the trade-offs, challenges, and strategies involved in achieving efficient
and effective pipeline execution in modern computing systems.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
One minute
20 Instruction pipelining 3 PPT
paper
One minute
20 pipeline Hazards 3 PPT
paper
One minute
5 Summary & Conclusion 3 PPT
paper

SESSION NUMBER : 31

Session Outcome: 1 Students can understand the role of storage in data-centric computing.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
5 Attendance 2 Talk --- NOT
APPLICABLE -
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--
Think / Pair /
20 Introduction 2 PPT
Share
Think / Pair /
20 Storage systems 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 32

Session Outcome: 1 Students empowers make informed decisions in memory management, cache design, and overall
system optimization.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE -
--
Think / Pair /
20 Introduction to memory hierarchy 2 PPT
Share
Think / Pair /
20 Importance of temporal and spatial locality 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 33

Session Outcome: 1 Students gains the intricacies of data storage, retrieval, and the role of main memory within the
broader context of a computer's memory hierarchy.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Think / Pair /
20 Introduction of Main memory organization 2 PPT
Share
Think / Pair /
20 Description - Main memory organization 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 34

Session Outcome: 1 students can develop a deeper insight into the intricacies of memory management and the
optimization of computer systems for better performance.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Think / Pair /
20 Cache memory: address mapping 2 PPT
Share
Think / Pair /
20 Concept of Block size 2 PPT
Share

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Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 35

Session Outcome: 1 students gains a deeper insight into the practical aspects of cache memory management

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Think / Pair /
20 Concept of Replacement in Memory 2 PPT
Share
Think / Pair /
20 Concept of Store policies 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 36

Session Outcome: 1 Students can grasp the step-by-step process of translating a virtual address to a physical address
through the page table, including the role of page table entries.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Think / Pair /
20 Virtual memory system: page table 2 PPT
Share
Think / Pair /
20 Virtual memory system: TLB 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 37

Session Outcome: 1 students gain a comprehensive understanding of the role these devices play in data management,
backup strategies, and the overall storage architecture of modern computer systems.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE -
--
Think / Pair /
20 External storage types 2 PPT
Share
Think / Pair /
20 External storage description 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 38

Session Outcome: 1 Students will gain insights into the complexities of managing data flow and ensuring reliable
communication between components in a computing environment.

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Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
Think / Pair /
20 IO fundamentals: Handshaking 3 PPT
Share
Think / Pair /
20 IO fundamentals: Buffering 3 PPT
Share
Think / Pair /
5 Summary & Conclusion 3 PPT
Share

SESSION NUMBER : 39

Session Outcome: 1 Students will grasp the impact of these I/O methods on operating system design.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE -
--
Think / Pair /
20 Programmed IO 3 PPT
Share
Think / Pair /
20 Interrupt driven IO 3 PPT
Share
Think / Pair /
5 Summary & Conclusion 3 PPT
Share

Tutorial Course DELIVERY Plan: NO Delivery Plan Exists

Tutorial Session wise Teaching – Learning Plan

No Session Plans Exists

Practical Course DELIVERY Plan:

Tutorial
Session Topics CO-Mapping
no

1 Introduction session to laboratory CO5

2 Controlling LEDs with Universal Logic Gates CO5

3 Combinational Circuit Based Car Security System CO5

4 Participant selection in Competitions Using Multiplexer CO5

5 Digital Display of the Department Name using 7-segment decoder CO5

6 Random Number Generator for Gaming Using D-Flip- flop CO5

7 Digital Unlocking System using Shift Register CO5

8 Design of Computational Processing System for Arithmetic and Logical Operations CO5

9 Implementation of Information Transmission System CO5

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Tutorial
Session Topics CO-Mapping
no

10 Development of Instruction Processing System from Fetching to Execution CO5

11 Implementation of Cache Memory CO5

12 Choice Based Control of Vending Machine CO5

13 Implementation of 3-Stage Pipelining CO5

Practical Session wise Teaching – Learning Plan

SESSION NUMBER : 1

Session Outcome: 1 Student able to developing practical skills in digital design and computer architecture through hands-
on laboratory experiences.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
40 Introduction to logisim 4 PPT APPLICABLE -
--
--- NOT
40 Introduction to hardware components 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 2

Session Outcome: 1 Student able to Implement a LED control using universal logic gates to demonstrate fundamental
digital circuit design principles.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
20 Description - Controlling LEDs with Universal Logic Gates 4 PPT APPLICABLE -
--
--- NOT
30 Implementation - Controlling LEDs with Universal Logic Gates 4 PPT APPLICABLE -
--
--- NOT
30 Results & Discussion 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 3
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Session Outcome: 1 Student able to design and testing a combinational circuit for a car security system to enhance vehicle
protection through digital logic implementation.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
20 Description - Combinational Circuit Based Car Security System 4 PPT APPLICABLE -
--
--- NOT
Implementation - Combinational Circuit Based Car Security
30 4 PPT APPLICABLE -
System
--
--- NOT
30 Results & Discussion 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 4

Session Outcome: 1 Student able to Utilize multiplexers for efficient participant selection in competitions, showcasing the
application of digital circuitry in event management systems.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
Description - Participant selection in Competitions Using
20 4 PPT APPLICABLE -
Multiplexer
--
--- NOT
Implementation - Participant selection in Competitions Using
30 4 PPT APPLICABLE -
Multiplexer
--
--- NOT
30 Results & Discussion 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 5

Session Outcome: 1 Student able to create a digital display of the department name through a 7-segment decoder

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
Description - Digital Display of the Department Name using 7-
20 4 PPT APPLICABLE -
segment decoder
--
30 Implementation - Digital Display of the Department Name using 4 PPT --- NOT
7-segment decoder APPLICABLE -
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--
--- NOT
30 Results & Discussion 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 6

Session Outcome: 1 Student able to develope a gaming-oriented random number generator using D-flip-flops

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
Description - Random Number Generator for Gaming Using D-
20 4 PPT APPLICABLE -
Flip- flop
--
--- NOT
Implementation - Random Number Generator for Gaming Using
30 4 PPT APPLICABLE -
D-Flip- flop
--
--- NOT
30 Results & Discussion 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 7

Session Outcome: 1 Student able to implement a secure digital unlocking system utilizing a shift register, showcasing the
application of sequential logic for controlled access scenarios.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
20 Description - Digital Unlocking System using Shift Register 4 PPT APPLICABLE -
--
--- NOT
30 Implementation - Digital Unlocking System using Shift Register 4 PPT APPLICABLE -
--
--- NOT
30 Results & Discussion 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 8

Session Outcome: 1 Student able to develop a Computational Processing System for Arithmetic and Logical Operations

Time(min) Topic BTL Teaching- Active

Learning Learning

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Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
Description of Computational Processing System for Arithmetic
20 4 PPT APPLICABLE -
and LogicalOperations
--
--- NOT
Implementation of Computational Processing System for
30 4 PPT APPLICABLE -
Arithmetic andLogical Operations
--
--- NOT
30 Results & Evaluation 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 9

Session Outcome: 1 Student able to Implement Information Transmission System

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
20 Description of Information Transmission System 4 PPT APPLICABLE -
--
--- NOT
30 Implementation of Information Transmission System 4 PPT APPLICABLE -
--
--- NOT
30 Results & Evaluation 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

SESSION NUMBER : 10

Session Outcome: 1 Student able to Optimiz the instruction processing system achieved by seamlessly integrating stages
from instruction fetching to execution for enhanced performance.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 3 PPT APPLICABLE -
--
--- NOT
Description of Instruction Processing System from Fetching to
20 3 PPT APPLICABLE -
Execution
--
--- NOT
Description of Instruction Processing System from Fetching to
30 3 PPT APPLICABLE -
Execution
--
--- NOT
30 Results & Evaluation 3 PPT APPLICABLE -
--

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--- NOT
10 Summary & Conclusion 3 PPT APPLICABLE -
--

SESSION NUMBER : 11

Session Outcome: 1 Student able to understanding a cache memory for efficient storage and retrieval of frequently
accessed data.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 3 PPT APPLICABLE -
--
--- NOT
20 Description of Cache Memory 3 PPT APPLICABLE -
--
--- NOT
30 Implementation of Cache Memory 3 PPT APPLICABLE -
--
--- NOT
30 Results & Evaluation 3 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 3 PPT APPLICABLE -
--

SESSION NUMBER : 12

Session Outcome: 1 Student able to understand a vending machine functionality with a choice-based control system for
user-selectable product options.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE -
--
--- NOT
20 Description of Choice Based Control of Vending Machine 4 PPT APPLICABLE -
--
--- NOT
30 Implementation of Choice Based Control of Vending Machine 4 PPT APPLICABLE -
--
--- NOT
30 Results & Evaluation 4 PPT APPLICABLE -
--
--- NOT
10 Choice Based Control of Vending Machine 4 PPT APPLICABLE -
--

SESSION NUMBER : 13

Session Outcome: 1 Student able to Improved a instruction throughput through the implementation of a three-stage
pipelining architecture.

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods

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--- NOT
10 ATTENDANCE 4 PPT APPLICABLE -
--
--- NOT
30 Demonstration of 3-Stage Pipelining 4 PPT APPLICABLE -
--
--- NOT
50 Implementation of 3-Stage Pipelining, Results & Evaluation 4 PPT APPLICABLE -
--
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE -
--

Skilling Course DELIVERY Plan: NO Delivery Plan Exists

Skilling Session wise Teaching – Learning Plan

No Session Plans Exists

WEEKLY HOMEWORK ASSIGNMENTS/ PROBLEM SETS/OPEN ENDEDED PROBLEM-SOLVING EXERCISES etc:

Assignment Assignment
Week Topic Details co
Type No
Weekly 2. Design a random number
5 Homework 2 D - Flip flops generator for gaming using D- CO2
Assignments flipflops
Weekly
1. Design a Digital Unlocking
6 Homework 2 Shift Registers CO2
System using Shift Register
Assignments
1. Define operands in the context
of computer instructions. What
are the different types of
operands commonly used in
assembly language
Weekly
programming? 2. Explain the
7 Homework 3 ALP, Hazards CO3
concept of pipeline hazards.
Assignments
What are data hazards, control
hazards, and structural hazards,
and how do they impact the
smooth execution of instructions
in a pipeline?
1. Define a machine cycle and
break down the components,
Weekly including fetch, decode, execute,
9 Homework 3 Instruction cycle & CISC, RISC and store. 2. Explore and CO3
Assignments contrast the architectural features
and design philosophies of RISC
and CISC architectures.
1. Provide examples of real-
world scenarios where temporal
locality is exhibited. How does
the repeated use of certain data
within a short time frame benefit
Weekly from the concept of temporal
10 Homework 4 Page Table locality? 2. Describe the typical CO4
Assignments structure of a page table. What
information is stored in the page
table entries, and how does the
operating system use this
information during address
translation?
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1. Draw and explain the

operation of 4:1 Mux and 1:4
Weekly demux. 2. How do AND gates
2 Homework 1 Multiplexer and Demultiplexer PLD's and OR gates contribute to the CO1
Assignments implementation of combinational
logic functions in PAL and PLA
devices?
1. Compare and contrast the
characteristics and
Weekly functionalities of main memory
11 Homework 4 Main memory & Handshaking in a computer system. 2. How CO4
Assignments does handshaking facilitate
communication between devices
in a computer system?
1. Optimize the following 3-
variable Boolean function:
Weekly
F(A,B,C)=Σ(1,2,4,6) using
3 Homework 1 K-Maps & FPGA, CPLD's CO1
Karnaugh Maps. 2. Sketch the
Assignments
digital logic modules of FPGA
and CPLD
1. Explore the applications of
Ring Counters in digital systems.
How are they utilized in various
scenarios, and what advantages
Weekly do they offer over other types of
4 Homework 2 Counters and Memories counters? 2. Differentiate CO2
Assignments between volatile and non-volatile
memory. Why is RAM
considered volatile, and how
does this characteristic influence
its usage in a computer system?

COURSE TIME TABLE:

Hour 1 2 3 4 5 6 7 8 9
Day Component
V-S13,V-
S14,V-
V-S25,V- V-S25,V- V-S13,V- V-S9,V- V-S33,V- V-S33,V- V-S43,V-
Theory S21,V- V-S9,V-S10
S26 S26 S14 S10 S34 S34 S44
S22,V-
S23,V-S24
Mon Tutorial -- -- -- -- -- -- -- -- --
V-S15,V- V-S11,V- V-S35,V- V-S35,V- V-S41,V-
V-S27,V- V-S27,V- V-S15,V- V-S11,V-
S15,V- S11,V- S35,V- S35,V- S41,V-
Lab S27,V- S27,V- S15,V- S11,V-
S16,V- S12,V- S36,V- S36,V- S42,V-
S28,V-S28 S28,V-S28 S16,V-S16 S12,V-S12
S16 S12 S36 S36 S42
Skilling -- -- -- -- -- -- -- -- --
V-S27,V-
S28,V-
V-S27,V- V-S15,V- V-S15,V- V-S11,V- V-S11,V- V-S35,V- V-S35,V-
Theory S41,V- ---
S28 S16 S16 S12 S12 S36 S36
S42,V-
S43,V-S44
Tue Tutorial -- -- -- -- -- -- -- -- ---
V-S13,V- V-S9,V- V-S33,V- V-S33,V-
V-S25,V- V-S25,V- V-S13,V- V-S9,V-
S13,V- S9,V- S33,V- S33,V-
Lab S25,V- S25,V- S13,V- S9,V-S10,V- ---
S14,V- S10,V- S34,V- S34,V-
S26,V-S26 S26,V-S26 S14,V-S14 S10
S14 S10 S34 S34
Skilling -- -- -- -- -- -- -- -- ---

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V-S21,V-
V-S5,V-
S22,V- V-S33,V-
V-S21,V- S6,V-S7,V- V-S17,V- V-S37,V- V-S37,V- V-S45,V-
Theory S37,V- S34,V- ---
S22 S8,V-S17,V- S18 S38 S38 S46
S38,V- S35,V-S36
S18
S39,V-S40
Wed Tutorial -- -- -- --- -- -- -- -- --
V-S19,V- V-S39,V- V-S39,V- V-S47,V-
V-S23,V- V-S23,V- V-S19,V-
S19,V- S39,V- S39,V- S47,V-
Lab S23,V- S23,V- -- --- S19,V-
S20,V- S40,V- S40,V- S48,V-
S24,V-S24 S24,V-S24 S20,V-S20
S20 S40 S40 S48
Skilling -- -- -- --- -- -- -- -- --
V-S23,V- V-S9,V-
S24,V- V-S1,V- S10,V-
V-S23,V- V-S19,V- V-S39,V- V-S39,V- V-S47,V-
Theory S49,V- S2,V- --- S11,V-
S24 S20 S40 S40 S48
S50,V- S3,V-S4 S12,V-
S51,V-S52 S19,V-S20
Thu Tutorial -- -- -- --- -- -- -- -- --
V-S17,V- V-S37,V- V-S37,V- V-S45,V-
V-S21,V- V-S21,V- V-S17,V-
S17,V- S37,V- S37,V- S45,V-
Lab S21,V- S21,V- -- --- S17,V-
S18,V- S38,V- S38,V- S46,V-
S22,V-S22 S22,V-S22 S18,V-S18
S18 S38 S38 S46
Skilling -- -- -- --- -- -- -- -- --
V-S7,V-
S8,V-
V-S7,V- V-S41,V- V-S41,V- V-S49,V-
Theory V-S3,V-S4 V-S3,V-S4 S45,V- --- ---
S8 S42 S42 S50
S46,V-
S47,V-S48
Fri Tutorial -- -- -- -- --- --- -- -- --
V-S43,V- V-S43,V- V-S51,V-
V-S1,V- V-S1,V- V-S5,V- V-S5,V-
S43,V- S43,V- S51,V-
Lab S1,V- S1,V- S5,V- S5,V- --- ---
S44,V- S44,V- S52,V-
S2,V-S2 S2,V-S2 S6,V-S6 S6,V-S6
S44 S44 S52
Skilling -- -- -- ----- --- -- -- --
V-S13,V-
V-S1,V- S14,V-
S2,V- S15,V-
V-S5,V- V-S51,V-
Theory S25,V- V-S1,V-S2 V-S5,V-S6 S16,V- --- --- ---
S6 S52
S26,V- S17,V-
S27,V-S28 S18,V-
Sat S19,V-S20
Tutorial -- -- -- -- -- --- --- --- --
V-S49,V-
V-S3,V- V-S3,V- V-S7,V- V-S7,V-
S49,V-
Lab S3,V- S3,V- S7,V- S7,V- -- --- --- ---
S50,V-
S4,V-S4 S4,V-S4 S8,V-S8 S8,V-S8
S50
Skilling -- -- -- -- -- --- --- --- --
Theory -- -- -- -- -- -- -- -- --
Tutorial -- -- -- -- -- -- -- -- --
Sun
Lab -- -- -- -- -- -- -- -- --
Skilling -- -- -- -- -- -- -- -- --

REMEDIAL CLASSES:

Supplement course handout, which may perhaps include special lectures and discussions that would be planned, and
schedule notified according

SELF-LEARNING:

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Assignments to promote self-learning, survey of contents from multiple sources.
S.no Topics CO ALM References/MOOCS

DELIVERY DETAILS OF CONTENT BEYOND SYLLABUS:

Content beyond syllabus covered (if any) should be delivered to all students that would be planned, and schedule notified
accordingly.
Advanced Topics, Additional Reading, Research papers
S.no CO ALM References/MOOCS
and any

EVALUATION PLAN:

Evaluation Evaluation Duration

Weightage/Marks Assessment Dates CO1 CO2 CO3 CO4 CO5
Type Component (Hours)
End End Weightage 24 6 6 6 6
Semester Semester 07.05.2024 180
Summative Exam Max Marks 100 25 25 25 25
Evaluation Lab End Weightage 16 16
Total= 40 Semester 07.05.2024 120
% Exam Max Marks 50 50
Semester in Weightage 15 7.5 7.5
In 11.03.2024,12.03.2024,13.03.2024 90
Exam-I Max Marks 50 25 25
Semester
Weightage 15 7.5 7.5
Summative Semester in 29.04.2024,30.04.2024,01.05.2024 90
Evaluation Exam-II Max Marks 50 25 25
Total= 38 Lab In Weightage 8 8
% Semester 01.04.2024 100
Exam Max Marks 50 50
Weightage 8 2 2 2 2
ALM 22.01.2024,01.05.2024 50
Max Marks 20 5 5 5 5
In
Semester Lab Weightage 7 7
Formative Weekly 22.01.2024,01.05.2024 100
Max Marks 75 75
Evaluation exercise
Total= 22 Home Weightage 7 1.75 1.75 1.75 1.75
% Assignment
22.01.2024,01.05.2024 50
and
Textbook Max Marks 28 7 7 7 7

ATTENDANCE POLICY:

Every student is expected to be responsible for regularity of his/her attendance in class rooms and laboratories, to appear
in scheduled tests and examinations and fulfill all other tasks assigned to him/her in every course
In every course, student has to maintain a minimum of 85% attendance to be eligible for appearing in Semester end
examination of the course, for cases of medical issues and other unavoidable circumstances the students will be condoned
if their attendance is between 75% to 85% in every course, subjected to submission of medical certificates, medical case
file and other needful documental proof to the concerned departments

DETENTION POLICY :

In any course, a student has to maintain a minimum of 85% attendance and In-Semester Examinations to be eligible for
appearing to the Semester End Examination, failing to fulfill these conditions will deem such student to have been
detained in that course.

PLAGIARISM POLICY :

Supplement course handout, which may perhaps include special lectures and discussions

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COURSE TEAM MEMBERS, CHAMBER CONSULTATION HOURS AND CHAMBER VENUE DETAILS:

Supplement course handout, which may perhaps include special lectures and discussions
Chamber
Delivery Chamber Chamber Signature of
Sections Consultation
Name of Faculty Component of Consultation Consultation Course
of Faculty Timings for each
Faculty Day (s) Room No: faculty:
day
Siva Ganga Prasad 5-MA,34-
L - - - -
Mutchakayala MA
Madhav B.T.P L 33-MA - - - -
Madhav B.T.P P 33-A - - - -
Venkata Ganesh
P 17-B - - - -
Gorla
42-B,45-
Suresh Namgiri P - - - -
B,47-B
1-MA,14-
Kali prasad L - - - -
MA
1-A,14-
Kali prasad P A,18-B,24- - - - -
B
Venkata Durga
L 46-MA - - - -
Mareedu
Venkata Durga
P 46-A - - - -
Mareedu
Subba Reddy 9-MA,41-
L - - - -
Vasipalli MA
8-B,9-
Subba Reddy
P A,23-B,41- - - - -
Vasipalli
A,50-B
7-MA,22-
Siddaiah Nalluri L - - - -
MA
7-A,22-
Siddaiah Nalluri P - - - -
A,34-A
Banda Sandeep L 48-MA - - - -
Banda Sandeep P 48-A,52-B - - - -
Vipul Agarwal L 37-MA - - - -
Vipul Agarwal P 25-B,37-A - - - -
36-MA,47-
Agilesh R L - - - -
MA
16-B,20-
Agilesh R P B,36-A,47- - - - -
A
Muzammil Parvez P 7-B,15-B - - - -
Syam Sundar
P 12-B - - - -
Pillalamarri
Atul Kumar P 46-B - - - -
Abhishek Pahuja P 2-B - - - -
Abhishek Kumar P 21-B - - - -
19-MA,27-
Lokendra Singh L - - - -
MA
Lokendra Singh P 19-A,27-A - - - -
Yesudasu Vasimalla P 9-B,23-A - - - -
2-MA,13-
Gopi Chatragadda L - - - -
MA
2-A,13-
Gopi Chatragadda P - - - -
A,48-B

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Nishant Kumar P 3-B - - - -

4-MA,16-
Sameer Yadav L - - - -
MA
4-A,16-
Sameer Yadav P A,27-B,34- - - - -
B,37-B
NAGESH 10-MA,42-
L - - - -
MANTRAVADI MA
NAGESH
P 10-A,42-A - - - -
MANTRAVADI
SHABBIR ALI L 52-MA - - - -
SHABBIR ALI P 52-A - - - -
VENKATA SAI
L 39-MA - - - -
BOKKISAM
1-B,11-
VENKATA SAI
P B,28-B,39- - - - -
BOKKISAM
A
SIVANI
L 51-MA - - - -
PINNABOINA
SIVANI 5-B,39-
P - - - -
PINNABOINA B,51-A
Siva Prasad Sripathi P 22-B - - - -
NAGAMALLI 6-MA,21-
L - - - -
ARASAVALLI MA
NAGAMALLI
P 6-A,21-A - - - -
ARASAVALLI
CHINTA
L 40-MA - - - -
MANJUSHA
6-B,26-
CHINTA
P B,40-A,51- - - - -
MANJUSHA
B
Suneetha Emmela L 24-MA - - - -
Suneetha Emmela P 40-B,44-B - - - -
Lakshmi Kuruguntla L 50-MA - - - -
5-A,13-
Lakshmi Kuruguntla P - - - -
B,50-A
20-MA,28-
Shailendra Tripathi L - - - -
MA
14-B,20-
Shailendra Tripathi P - - - -
A,28-A
SIVAPRASAD 17-MA,25-
L - - - -
LEBAKA MA
SIVAPRASAD
P 17-A,25-A - - - -
LEBAKA
TAMMINENI 12-MA,44-
L - - - -
SREELATHA MA
4-B,12-
TAMMINENI
P A,38-B,44- - - - -
SREELATHA
A
APPIKATLA PHANI
L 38-MA - - - -
KUMAR
33-B,36-
APPIKATLA PHANI
P B,38-A,43- - - - -
KUMAR
B
BANDARU 11-MA,43-
L - - - -
MAMATHA MA

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BANDARU 11-A,43-
P - - - -
MAMATHA A,49-B
SRINIVASARAO
L 49-MA - - - -
ALLURI
SRINIVASARAO
P 19-B,49-A - - - -
ALLURI
35-MA,45-
Neppalli Ramesh L - - - -
MA
Neppalli Ramesh P 35-A,45-A - - - -
RAJANIDEVI 8-MA,23-
L - - - -
MERIGALA MA
RAJANIDEVI 8-A,10-
P - - - -
MERIGALA B,35-B
LAKSHMUNAIDU 18-MA,26-
L - - - -
M MA
LAKSHMUNAIDU
P 18-A,26-A - - - -
M
RANJAN 3-MA,15-
L - - - -
MAHAPATRA MA
3-A,15-
RANJAN
P A,24- - - - -
MAHAPATRA
A,41-B

GENERAL INSTRUCTIONS

Students should come prepared for classes and carry the text book(s) or material(s) as prescribed by the Course Faculty to
the class.

NOTICES

Most of the notices are available on the LMS platform.

All notices will be communicated through the institution email.

All notices concerning the course will be displayed on the respective Notice Boards.

Signature of COURSE COORDINATOR

(TAMMINENI SREELATHA)

Signature of Department Prof. Incharge Academics & Vetting Team Member

Department Of DBES-2

HEAD OF DEPARTMENT:

Approval from: DEAN-ACADEMICS

(Sign with Office Seal) [object HTMLDivElement]

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