IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO.

8, AUGUST 2020 6195

Power Electronic Converter Based Flexible

Transmission Line Emulation
Soham Dutta , Sushmit Mazumdar, and Kaushik Basu , Senior Member, IEEE

Abstract—A power electronic converter based transmis- tcomp,PS Required observer computation time in PS.
sion line emulator (TLE) is presented in this paper. The TLE tcomp,PL Required observer computation time in PL.
can emulate medium and long lines in steady-state and sym- tclk,PS Instruction clock period in PS.
metrical faults occurring at any point in the line. A traveling
wave based numerical scheme for the emulation of the line tclk,PL Instruction clock period in PL.
is identified and then implemented on a novel digital archi- tf Time required by a processor to perform tasks other
tecture in the field-programmable gate array part of a system than observer computation.
on chip platform. The proposed architecture meets the real- Flimit Maximum operating switching frequency of a
time computation constraints through parallel processing power converter.
and optimal use of hardware resources (DSP slices, block
RAMs, etc.). A comprehensive analysis to determine the δP Power angle between two ends of transmission
two important parameters of the TLE—the power converter line.
switching frequency and observer update period while sat-
isfying a number of constraints coming from the numer-
ical scheme, power, and embedded hardware—has been I. INTRODUCTION
presented. Finally, relevant simulation and experimental re-
EAL-TIME simulation of power systems, electromechan-
sults on a developed 400-V 15-kVA TLE prototype have been
presented for validation.
Index Terms—Current control, hardware emulation, long
R ical energy conversion systems, various power sources,
and loads in steady and transient conditions plays a vital role
transmission line, three-phase voltage source inverter (VSI), in the testing of industry manufactured control, protection and
real-time simulation, system on chip (SoC). power equipment [1]–[8]. A digital platform emulating a test
environment in real time can be connected to a control or pro-
NOMENCLATURE tection device under test (DUT) through digital to analog and
analog to digital conversion interfaces. This is called hardware
Δtobs Transmission line observer solution update period. in loop (HIL) testing [3]–[8]. Here, the digital platform is called
Fsw Power electronic converter switching frequency. the observer (OBS) [see Fig. 1(a)]. For example, the controller
Tsw Power electronic converter switching period. of a grid-tied solar inverter can be tested in an HIL platform.
l Length of emulated transmission line. Where the observer has to emulate solar PV, grid, and the in-
n No. of line subdivisions. verter. Note in HIL simulation, the DUT does not exchange
Δx Length of each line subdivision. real power with the observer. Now, to test the solar inverter
Δxdes Desired minimum length resolution on the line. along with the controller, the emulated test environment (the
R, L, G, C Per-unit length line resistance, inductance, conduc- utility grid and solar PV) needs to exchange electric power with
tance, and capacitance, respectively. DUT. This is achieved by adding a power amplifier (PA) in the
Z0 Characteristic impedance of line. real-time emulator. This PA is implemented with a power elec-
c Wave propagation velocity along line. tronic converter. So, here, we need a power electronic converter
fi,max Maximum frequency component in an emulated based PV and grid emulators. This test setup is known as PHIL
line current signal. [see Fig. 1(b)] [9]–[15]. Hardware emulators, in PHIL testing,
are used to replace any costly or physically unavailable com-
Manuscript received September 13, 2018; revised January 28, 2019 ponent and produce a diverse set of test conditions through a
and April 5, 2019; accepted May 12, 2019. Date of publication June 28, user-friendly interface.
2019; date of current version March 31, 2020. This work was supported Applying the abovementioned concept in developing a rep-
by the Department of Science and Technology, Government of India
through the “Fund for Improvement of S&T Infrastructure” Program at resentative power grid system for laboratory-based testing of
Indian Institute of Science, Bengaluru and by the project titled “Develop- control, protection and power equipment, and communication
ment of an advanced system on chip (SoC) based embedded controller interfaces, autonomous emulators of every component in the
for power electronic converters.” (Corresponding author: Soham Dutta.)
The authors are with the Electrical Engineering Department, Indian system are developed, which are electrically interconnected fol-
Institute of Science, Bengaluru 560012, India (e-mail:, soham.g6992@ lowing the intended network [14]–[17]. Following a similar
gmail.com; [email protected]; [email protected]). idea, a field-programmable gate array (FPGA) based genera-
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. tor, power converter, and transmission line models have been
Digital Object Identifier 10.1109/TIE.2019.2922940 developed in [18]–[20]. But these platforms are incapable of
0278-0046 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 6196 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 8, AUGUST 2020

as three-phase faults occurring at any intermediate point on the

line. Following are the contributions of this paper.
1) We have investigated the applicability of different trans-
mission line models for the stated purpose and identified
a traveling wave based numerical solution suitable to be
solved by the observer in real time.
2) Two key parameters in the design of a programmable TLE
are the power converter switching frequency (Fsw ) and
observer solution update period (Δtobs ). Once selected,
these parameters are not changed for varying cases of line
Fig. 1. Conceptual diagram of (a) HIL and (b) power PHIL (PHIL) length, line parameters, and emulated transient dynamics.
simulation.
The desired space resolution on the emulated line, accu-
racy of the numerical scheme, and frequency content of
the line current signal directly influence the choice of
Δtobs . The choice of Fsw depends on the maximum pos-
sible switching frequency of the power electronic con-
verter and the minimum controller bandwidth required to
track the current references. Furthermore, the constraint
of real-time computation based on the chosen embedded
platform also influence the selection of these parameters.
In this paper, we have provided a comprehensive anal-
ysis of all these determining factors and laid out simple
guidelines to choose the correct values of Fsw and Δtobs
to make the TLE platform independent of emulated line
length and parameters.
3) Due to the complexity of the chosen traveling wave based
transmission line model that captures the distributed
nature of the line, the real-time computation needed in
Fig. 2. General architecture of a TLE. the observer is significantly high when compared with
the previous works [21]–[24]. We show, how to compute
the observer computation time if implemented in a se-
exchanging power with any external hardware. On the contrary, quential processor. The ARM Cortex A9 of Zynq 7000
in a test bed built using power converter based emulators, every system on chip (SoC) is used as an example.
node inside the emulated network is physically accessible to 4) A novel digital architecture for real-time implementation
a power hardware under test and insertion of custom designed of the observer in the FPGA part of SoC has been pro-
PAs are is longer required. Power converter based emulation of vided, which uses parallel computation and optimal num-
synchronous generators has been reported in [17]. In this paper, ber of digital resources (DSP slices, block RAMs, etc.)
we address similar emulation of transmission lines. and thereby drastically reduces the computation time.
The general architecture of a transmission line emulator 5) An experimental test bed for a TLE with grid or bus
(TLE), as shown in Fig. 2, has two main components—the emulators is presented that draws only the losses in the
observer and the power hardware. Sending end (S.E.) and re- power converters.
ceiving end (R.E.) bus voltages (vSE (t), vRE (t)) are physically This paper is organized as follows. Section II provides the
fed to the observer, which solves the emulated line model in modeling and solution of ac transmission lines suitable for long
real-time and estimates the S.E. and R.E. currents of the line line emulation. Section III describes the design and embedded
(i∗SE (t), i∗RE (t)). The estimated currents work as references and implementation details of the observer. Section IV describes
the power hardware output currents (iSE (t), iRE (t)) are con- the power hardware topology and associated controls. Relevant
trolled to track them. Leveraging high switching frequencies simulation and experimental results are given in Section V.
and flexible control of power electronic converters, the power Section VI concludes this paper.
hardware is comprised of three-phase voltage source converters.
The works in [21]–[24] have extensively dealt with the design
and development of a TLE based on a similar architecture. The II. MODELING AND SOLUTION OF TRANSMISSION LINES
works in [21] and [22] have addressed line emulation in case The complexity of the mathematical model of the line to be
of steady state and the works in [23] and [24] have emulated solved in the observer depends on the nature of the emulated
three-phase short-circuit faults on a transmission line. However, event (frequency content, location) as well as the characteristics
the scope in all these works is limited to short lines only, where a of the emulated line (line length (l), arrangement). A very de-
simple lumped R–L model of the line is sufficient for emulation. tailed model can give accurate results in any case while incurring
In this paper, we address the problem of hardware emulation a large computational overhead in real time, whereas a simpli-
of medium and long transmission lines in steady state as well fied model may fail to generate the desired output. Thus, this
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 DUTTA et al.: POWER ELECTRONIC CONVERTER BASED FLEXIBLE TRANSMISSION LINE EMULATION 6197

Fig. 4. Problem addressed by the observer.

where v(x, t) and i(x, t) are, respectively, the voltage and cur-
rent at a distance x from the S.E. of the line at time t. To ensure
modular and autonomous operations of the line emulators, our
goal here is to develop a solution of (1)–(2) that solves the ter-
minal currents only based on the information of individual line
parameters and local bus voltages. Another important objective
is that the solution must be capable of estimating fault currents
for faults occurring anywhere along the line, which also inspires
us to preserve the distributedness of the line unlike it is lumped
approximations. In addition, the solution time should be small
enough to aid real-time emulation. Based on Fig. 4 and discus-
Fig. 3. Comparison of S.E. currents during steady state and fault
transient of a 500-km-long line. (a) Comparison of PSCAD frequency-
sion mentioned above, the problem statement for the observer
dependent model (FDM), lumped R–L model, and nominal Pi model. can be formulated as follows.
(b) Comparison of PSCAD FDM and PSCAD Bergeron. Given initial condition of voltage and current along the line:
v(x, 0) and i(x, 0) and boundary condition of terminal volt-
section is dedicated toward finding out the applicability of dif- ages: vSE (t) = v(0, t) and vRE (t) = v(l, t), solve the terminal
ferent transmission line models and their solutions for real-time currents: iSE (t) = i(0, t) and iRE (t) = i(l, t).
emulation of steady-state and symmetrical faults in medium and A potential candidate for the solution of the abovementioned
long lines. For simplicity of understanding, it is assumed that problem is the Bergeron model [25] as it considers uniform dis-
the lines are a three-phase single circuit, fully transposed in na- tribution of the line inductance and capacitance while lumping
ture and the conductors are symmetrically spaced, maintaining the total line resistance at three places. The solution is much
a uniform height over the ground. faster and accurate and better suited for digital implementation
A simple series model of total line resistance and inductance than cascaded Pi circuits. However, to get accurate results, the
(R–L model) is fairly accurate for short lines (l < 80 km), as wave travel time (τ ) has to be an integral multiple (m1 ) of
emulated in [21]–[24], but not sufficient for long lines as the the time interval Δtobs at which the observer solves the model
shunt admittance of the line becomes significant. For medium and updates the solution or τ = m1 × Δtobs . This essentially
(80 km < l < 250 km) and long (l > 250 km) lines, a nominal Pi avoids the need for using complex interpolation algorithms to
lumped parameter model can be used for the sinusoidal steady- compensate the timing mismatch [25]. Furthermore, as will be
state analysis. However, this model is not accurate for faults and seen later, for discrete-time implementation, Δtobs must be an
other high-frequency transients due to the inherent lumpedness integral multiple (m2 ) of the power converter switching period
of the line parameters [25]. Fig. 3(a) shows the mismatch in (Tsw ). Therefore,
one phase of the S.E. currents during steady state as well as a τ = m1 × m2 × Tsw , (∵ Δtobs = m2 × Tsw ). (3)
three-phase fault at R.E. of a 132-kV 500-km-long line for three
different models—a lumped R–L model, a nominal Pi model, As τ varies with line parameters, (3) implies that if Berg-
and the PSCAD FDM [26]. Fig. 3(b) compares the same result eron model is used, the power converter switching frequency
between PSCAD Bergeron model and PSCAD FDM model. The (Fsw = 1/Tsw ) needs to be changed every time a new line is
transient performance can be improved by cascading several Pi emulated, which will impede flexibility of implementation. This
sections to better represent the distributed nature of the line also presents difficulty to emulate a fault at an intermediate point
parameters, but that increases computation time and complexity on the line, as the line needs to be divided into two segments
so greatly that it becomes very difficult to implement on a digital that have different values of τ parameter, requiring two differ-
platform. Moreover, for longer lines, nominal Pi model need to ent time steps in observer computation. Furthermore, the pre-
be replaced with long line corrected equivalent Pi model for fault voltage and current information at the intermediate point
better results [25]. needs to be known to calculate the fault currents, which are also
The abovementioned observations inspire us to consider the not available with the Bergeron model since it solves only the
general distributed model of a transmission line for emulation terminal quantities of a line.
purpose, as dictated by the following governing equations: To overcome the abovementioned difficulties in digital im-
plementation and fault emulation, in this paper, a numerical
∂v(x, t) ∂i(x, t)
+L + Ri(x, t) = 0 (1) method known as the “method of characteristics” (MOC) [27],
∂x ∂t used for solving hyperbolic partial differential equations such
∂i(x, t) ∂v(x, t) as (1)–(2), is adopted. Unlike the Bergeron model, MOC uni-
+C + Gv(x, t) = 0 (2)
∂x ∂t formly distributes the line resistance and also considers the shunt
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 6198 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 8, AUGUST 2020

with the observer update interval (Δtobs ) in order to make the

TLE platform independent of the emulated line length and pa-
rameters for a range of transients, keeping practical limitations
of the digital hardware and power hardware into consideration.
We will be answering this question first.
A power electronic converter through closed-loop feedback
control ensures that the emulator currents track the S.E. and R.E.
currents computed by the observer. As in this case, the actuator
or power converter is updated only at every switching period
Tsw , there is no need to update the observer computation faster
than that. So, Δtobs ≥ Tsw . Also for digital implementation, it
is convenient to set Δtobs as an integral multiple of Tsw or
Fig. 5. Numerical scheme implemented in the observer P ∈ {V, I}.

Δtobs = m2 × Tsw , m2 ∈ {1, 2, 3, . . .} . (9)

conductance of the line. The MOC converts (1) and (2) into or-
dinary differential equations that can be integrated only along a
√1
So, determination of Δtobs and Tsw is same as finding m2
family of straight lines (see Fig. 5) with slopes dxdt = ± L C = and Tsw . In the following analysis, we consider a case in
±c in the x − t plane [27]. c is the wave propagation velocity.
which the line parameters of the chosen set of emulated trans-
The intersection of these lines on the x − t plane forms the
mission lines vary within ±10% of a nominal value (Xnom )
solution points for v(x, t) and i(x, t) at a regular space interval
as 0.9Xnom ≤ X ≤ 1.1Xnom where X ∈ {L, C, R, G} and the
of Δx and time interval of Δt such that | Δ Δ t | = c. Hence, we
x
maximum length of any emulated line (lmax ) is 1000 km. The
discretize a continuous quantity p ∈ {v, i} in space and time as
considered range of variation of the line parameters and lmax are
p(x, t) = p(jΔx, kΔt) = Pj [k], P ∈ {V, I} . (4) however design parameters that are specific to a TLE platform.
The nominal values of the line parameters in our case are given
In our case, Δt = Δtobs , Δx = cΔtobs , and j = 0, 1, . . . , n in Table III. 
From there, we obtain, minimum surge impedance
where l = nΔx. Also, for S.E., VSE [k] = V0 [k] and ISE [k] = is Z0,min = Lmin /Cmax = 485 Ω and likewise the minimum
I0 [k], and for R.E., VRE [k] = Vn [k] and IRE [k] = In [k]. At ev- and maximum wave velocities are cmin = 2.26 × 105 km/s and
ery kth time step, to solve Pj [k] at any internal point on the line, cmax = 2.76 × 105 km/s, respectively.
the observer solves (5)–(6) using the previous step information Δtobs determines the number of line subdivisions (n) by n =
at two adjacent points Pj −1 [k − 1] and Pj +1 [k − 1], whereas to l/Δx = l/(cΔtobs ) and thereby the computational load on the
find out current at a boundary point, it solves either (7) or (8) digital platform. The choice of Δtobs depends on several factors,
using the previous step data at one adjacent point and sampled which are given as follows.
value of the terminal voltage VSE [k] or VRE [k]. The solved kth 1) Since the transmission line is considered uniform and
step data are stored and used to solve the (k + 1)th step in the continuous, the incremental resistance RΔx in MOC
next computation cycle and in this way the numerical scheme should be small enough compared to the surge impedance
advances in real time. For 1 ≤ j ≤ n − 1, Z0 , not to cause discontinuity in wave propagation.
Vj [k] = C4 (Vj −1 [k − 1] + Vj +1 [k − 1]) Therefore, to get accurate results, RΔx << Z0 . To sat-
isfy for any line, it is recommended to keep
+ C5 (Ij −1 [k − 1] − Ij +1 [k − 1]) (5)
Ij [k] = C6 (Vj −1 [k − 1] − Vj +1 [k − 1]) Z0,min Z0,min
(RΔx)max ≤ or Δtobs ≤ (10)
+ C7 (Ij −1 [k − 1] + Ij +1 [k − 1]) (6) 10 10(Rc)max

ISE [k] = C1 VSE [k] − C2 V1 [k − 1] + C3 I1 [k − 1] (7)

since (RΔx)max = (Rc)max Δtobs .
IRE [k] = − C1 VRE [k] + C2 Vn −1 [k − 1] + C3 In −1 [k − 1] 2) For proper reconstruction of the estimated line current
(8) signal, we ensure that the observer samples the signal
at least at ten times the maximum frequency component
where C1 , . . . , C7 are constants for a particular line whose for-
(fi,max ) present in it. Hence, fobs = 1/Δtobs ≥ 10fi,max .
mulae in terms of line parameters are given in the Appendix.
As this paper addresses the emulation of steady-state
For the steady-state and symmetrical fault analysis, only two
and symmetrical fault dynamics, it is sufficient to take
phases of a three-phase line needs to be solved using (5)–(8) as
fi,max = 100 Hz.
the line is in balanced conditions.
3) Value of Δx should be chosen lesser than the desired
minimum space resolution Δxdes , so that fault points
III. EMBEDDED IMPLEMENTATION OF THE TLE
can be located more precisely. Therefore, Δx ≤ Δxdes
One important question that needs to be answered is how to or Δtobs ≤ Δxdes /cmax . As a choice we take Δxdes =
choose the power converter switching frequency (Fsw ) along 15 km.

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 DUTTA et al.: POWER ELECTRONIC CONVERTER BASED FLEXIBLE TRANSMISSION LINE EMULATION 6199

Abovementioned three factors constitute the upper limit (α) Using (9) and (14), (16) forms a quadratic inequality of Δtobs
of Δtobs as
Δtobs 2 − m2 tf Δtobs − kz ≥ 0. (17)
 
Z0,min 1 Δxdes Solving (17), we get βz (z ∈ {PS, PL}), a function of m2 as the
Δtobs ≤ α = min , , (11)
10(Rc)max 10fi,max cmax lower limit of Δtobs

which satisfies the requirements of numerical solution related m2 tf + (m2 tf )2 + 4kz
constraint, signal reconstruction, and space resolution for emu- Δtobs ≥ βz (m2 ) = . (18)
2
lation of any line within the considered range of parameters and
Note that βz (m2 ) is influenced by the maximum line length and
length. Putting the values in (11) for the present case, we obtain
the computation speed of the digital platform. From (11) and
α = 54 μs.
(18), we conclude that Δtobs should be chosen so that
Next, from (5)–(8) we can infer that to solve two phases  
of a three-phase line with n subdivisions, at each computation βz (m2 ) ≤ Δtobs ≤ α, z ∈ PS, PL . (19)
step, the observer performs φ(n) = 12 + 8(n − 1) multiplica-
As βz (m2 ) increases with m2 , its minimum value is ob-
tions and ψ(n) = 9 + 12(n − 1) additions along with move and
tained for m2 = 1. However, for the TLE platform being
shift operations. Xilinx make Zynq SoC has been selected as the
designed, (18) gives βPS (1) = 59 μs and βPL (1) = 31 μs.
embedded platform that has an ARM Cortex-A9 based process-
Therefore, the observer cannot be implemented in the Zynq
ing system (PS) and Xilinx programmable logic (PL) on a single
PS as βPS (m2 ) > α(= 54 μs) for all m2 , violating (19). Hence,
chip [see Fig. 7(a)]. The required numbers of instruction cycles
for further analysis, we will consider only βPL (m2 ).
for multiplication (ICM) and addition (ICA) are five and four,
respectively, for floating point operation in Zynq PS that has an
A. Determination of Power Converter
instruction clock period tclk,PS = 6 ns. Therefore, the required
Switching Period (Tsw )
computation time of the observer (tcomp ) in PS can be roughly
estimated as Putting Δtobs = m2 Tsw in (19), we get for PL that
βPL (m2 ) α
tcomp,PS ≈ [φ(n) × ICM + ψ(n) × ICA] tclk,PS β  (m2 ) = ≤ Tsw ≤ = α (m2 ). (20)
m2 m2
≈ (88n + 8)tclk,PS ≈ (88n)tclk,PS . (12)
The choice of Tsw = 1/Fsw depends on the maximum switch-
To achieve a much faster rate of computation using parallel ing frequency at which the designed power converter can be
multiplier and adder blocks, a Zynq PL-based implementation operated, denoted as Flimit (30 kHz, in our case). Furthermore,
of the observer has been proposed later by which it takes fixed to ensure proper switching frequency noise attenuation, Fsw is
eight PL clock cycles (1 tclk,PL = 10 ns) to compute each line kept at least ten times higher than the control bandwidth, which
subdivision. Thus, for n subdivisions is again kept at ten times the maximum frequency of current
signal to be tracked (fi,max ). Therefore,
tcomp,PL ≈ (8n)tclk,PL . (13)
100fi,max ≤ Fsw ≤ Flimit (21)
For both PS and PL, tcomp is an increasing function of n(= or δ = 1/Flimit ≤ Tsw ≤ γ = 1/100fi,max . (22)
cΔ t obs ), which is maximum when l = lmax and c = cmin . There-
l

fore, we can write Combining inequalities (20) and (22) we conclude

tcomp,max = kz /Δtobs , z ∈ {PS, PL} (14) max {β  (m2 ), δ} ≤ Tsw ≤ min {α (m2 ), γ} . (23)
 
where kz = (88 lmax tclk,PS ) /cmin , for PS α (m2 ), β (m2 ), γ (= 100 μs), and δ(= 33.33 μs) are plotted
in Fig. 7(b) with respect to m2 for the TLE under design and
= (8 lmax tclk,PL ) /cmin , for PL. (15) the line segment(s) corresponding to Tsw and m2 choices that
satisfy (23) is shown. In the present case, we get the following
In power converter control, one switching period is divided to range: 33.33 μs ≤ Tsw ≤ 56 μs and m2 = 1. Hence, Δtobs =
perform four main tasks as follows: Tsw = 50 μs and corresponding Fsw = 20 kHz is chosen for the
a) sensing and signal filtering; TLE platform designed in this paper. Thus, using inequality (23),
b) observer computation; one can determine correct values of Δtobs and Fsw to be used
c) control and modulation; in order to make the emulator independent of the emulated line
d) communication. length and parameter variation while satisfying all the digital
Let the total time required to perform tasks a), c), and d) be and power hardware constraints.
denoted as tf , which is around 20 μs in our case for Zynq PS.
Since Δtobs can span over m2 number of switching periods, at B. Implementation of Observer in Zynq PL
least (1/m2 )th fraction of the observer computation task must
be completed in one Tsw . Hence, Tsw should be chosen so that Referring to Fig. 8, to find terminal currents (j ∈ {0, n}) of
one phase of the line, we solve (7) and (8) using Op-1a, Op-2,
tcomp,max Op-3, and Op-6. For other values of j (intermediate points),
Tsw ≥ + tf . (16)
m2 (5) and (6) are solved using Op-1b, Op-4, Op-5, and Op-6.

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 6200 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 8, AUGUST 2020

Fig. 6. Resource utilization and timing diagram of the observer operation in Zynq PL for solving a three-phase transmission line with n subdivisions.

TABLE I
FPGA RESOURCE UTILIZATION

(a)

(b)

Fig. 7. (a) PS and PL in a Zynq SoC architecture. (b) Determination of TABLE II

T sw for the designed TLE platform. COMPARISON OF COMPUTATION LOAD AND MEMORY REQUIREMENT
(*SPECIFIC TO ZYNQ PS)

memory buffers that store previous time step data. To solve two
phases of the line simultaneously, six DSP48E1 slices and four
logic fabric adders in the Zynq PL are used to perform Op-2
and Op-3, whereas for Op-4 and Op-5, four preadder DSP48E1
multipliers, four presubtractor DSP48E1 multipliers, and four
logic fabric adders are used. The detailed timing diagram of the
operation is shown in Fig. 6 and PL resource utilization is given
in Table I.

C. Comparison of Model Computation Tasks and

Memory Utilization
In comparison to the proposed MOC-based method, the Berg-
Fig. 8. Observer algorithm to solve one phase of a line in Zynq PL. eron model results in much less computation only when the
line is emulated in steady state. However, for fault emulation,
the Bergeron model results in more computation and requires
These four operations for each j takes eight PL clocks (see larger memory. The computation details and memory required
Fig. 6). Thus, sequential evaluation of Vj [k] and Ij [k] at an for a processor-based implementation of the Bergeron method
observer time step k from j = 0 to j = n − 1 requires 8n PL for line emulation purpose are outlined in Appendix. A com-
clock cycles. For Op-2 to Op-5, operands are fetched using parison of MOC with Bergeron for solving a long line with n
multiplexers M1 –M5 based on the value of j, from 32-b wide subdivisions is presented in Table II.
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 DUTTA et al.: POWER ELECTRONIC CONVERTER BASED FLEXIBLE TRANSMISSION LINE EMULATION 6201

Fig. 10. Control block diagram of the line emulators (x ∈ {SE, RE}).

Fig. 9. Power hardware topology inside the TLE.

TABLE III Fig. 11. Control block diagram of the grid emulators (x ∈ {SE, RE}).
ACTUAL AND SCALED DATA OF EMULATED LINE

IV. TLE POWER HARDWARE TOPOLOGY AND CONTROL

One three-phase voltage source inverter (VSI) emulates the
S.E. and simultaneously another VSI is used to emulate the R.E.
of the line. These VSIs are connected in a back-to-back fashion
through a common dc link (P–N) as shown in Fig. 9 [21]. Fig. 12. Validation of a developed observer for the steady state and
three-phase fault emulation. (a) Comparison with PSCAD FDM. (b) Com-
parison of the proposed method with the existing method and the PSCAD
A. Scaling of the Actual System Bergeron model.
In order to emulate any transmission line using laboratory-
scale power electronic hardware, the actual power and voltage
level of the line need to be scaled down to the power and voltage support the actual losses (switching and conduction loss in the
level of the three-phase VSIs in the emulator. For example, for switching devices and losses in the filter inductor). An active
the TLE designed in this paper, the VSIs are rated for 15 kVA and front-end rectifier (AFE) is used to support the bidirectional
400 V (L–L). To preserve system equivalence, the scaling should power flow requirement while maintaining constant output dc
be done keeping the per unit (p.u.) values of power, voltage, and voltage using the conventional inner current and outer voltage
line parameters (R, L, C, G) unchanged. The nominal values of loop control method [28].
the line parameters are given in Table III. If the nominal voltage The scaled down S.E. and R.E. bus can be emulated with VSIs,
and current of the actual line are scaled down by factors Kv and also known as grid emulators. If connected through isolation
Ki , respectively, to keep the p.u. values unaltered, parameters transformers, these bus emulator VSIs can be connected to the
R, L, C, and G scale as kR, kL, C/k, and G/k, respectively, same dc link (P–N). This will result in circulation of active
where k = Kv /Ki . However, the wave propagation velocity power at both ends of the emulated line. In this way, the AFE
and travel time remain unaltered even after scaling for a given only need to support the converter losses and hence can be of low
length of the line. During fault in the actual system, the current power rating. The proposed test bed with grid or bus emulator
becomes almost five times its rated value (218.7 A). For fault and line emulator VSIs along with the AFE are shown in Fig. 9.
emulation, in order to limit the current in the TLE to its rated
value of 21.65 A, Ki is reduced by a factor of five. C. Control Implementation
The two VSIs used for emulating the transmission line are
B. Emulation of Transmission Line Losses
controlled in current control mode in order to track the observer
The source controlling the dc bus (P-N) needs to sink the generated current references. The system-level control block di-
power loss in the emulated transmission line. It also needs to agram is shown in Fig. 10. The controllers have been designed
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 6202 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 8, AUGUST 2020

Fig. 13. Steady-state emulation. (a) TLE using the proposed method. (b) TLE using the Bergeron method. (c) TLE using the existing method
(R–L line). (d) PSCAD simulation of the steady state at actual power level. (e) PSCAD simulation at TLE power level. (f) Harmonic analysis of the
steady-state current.

TABLE IV
DESIGN DETAILS OF THE TLE POWER AND EMBEDDED HARDWARE

Fig. 14. Experimental setup of the TLE system.

transmission line model available in PSCAD—the frequency-

in the rotating dq0 frame so that the reference currents appears dependent phase model (PSCAD FDM). Current error in the
as dc in steady state and can be tracked using simple PI con- existing R–L model based approach in Fig. 12 confirms the va-
trollers. The VSIs are synchronized with the grid voltages using lidity of the proposed method in steady state (δP kept at 0◦ ) and
a synchronous reference frame PLL [28]. The open-loop control during fault transients (at 210 km of a 500-km line).
bandwidth is kept at 500 Hz and the achieved phase margin is For experimental validation, the experiments were performed
around 80◦ . The converters in the grid bus emulator have been keeping the grid voltages at 1 p.u. in the emulator base as
controlled in voltage–frequency control mode using the conven- per Table III and dc bus voltage regulated at 800 V. In each
tional inner current and outer voltage loop control method. In experiment, the emulated event is also simulated in PSCAD
this way, the filter capacitor voltage is controlled to act as the using the frequency-dependent phase model of the line for val-
grid for the subsequent line emulator (see Fig. 11). idating the obtained experimental result. The events observed
have been divided into the following three cases.
V. SIMULATION AND EXPERIMENTAL RESULTS
A. Steady State
To verify the proposed emulation scheme, a TLE prototype
is designed and fabricated as shown in Fig. 14. The details of Fig. 13(a) shows PSCAD simulation of three-phase S.E. cur-
the power and embedded hardware of the designed TLE are rents of the actual transmission line when the power angle δP
listed in Table IV. As a case study, a 500-km-long transmission between the S.E. voltage (VSE ) and R.E. voltage (VRE ) is fixed
line having R, L, G, and C parameters as listed in Table III is at +15◦ . Fig. 13(b) shows the PSCAD simulation of the line
considered for emulation. when scaled down to the emulator level following conversion
Based on the abovementioned data and chosen Δtobs , the ob- in Table III. Fig. 13(c) shows the experimental result from the
server based on the chosen numerical scheme (MOC) was coded developed emulator. Active power flow = 4 kW and reactive
in MATLAB/Simulink and compared against the most accurate power flow = +3.3 kVAR.
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 DUTTA et al.: POWER ELECTRONIC CONVERTER BASED FLEXIBLE TRANSMISSION LINE EMULATION 6203

Fig. 15. (a) PSCAD simulation of step change in δP (Bergeron). (b) TLE result using the proposed method. (c) TLE result using the existing
method (R–L).

Fig. 16. (a) PSCAD simulation of step change in V RE (Bergeron). (b) TLE result using the proposed method. (c) Harmonic analysis in line currents.

Fig. 17. Phase-a current and voltage during three-phase fault at R.E. triggered at positive zero crossing of V SE . (a) PSCAD simulation (Bergeron).
(b) TLE emulation using the proposed method. (c) TLE emulation using the existing method.

B. Step Change in Power Angle and Bus Voltage

Fig. 15 shows the PSCAD simulation [see Fig. 15(a) and (b)]
and the hardware emulation result [see Fig. 15(c)] of the three-
phase S.E. currents of the line when δP is changed from 0◦ to −
15◦ . Note the 90◦ phase difference between the a-phase voltage
and current as the line draws only reactive power in steady
state when δP = 0◦ . Similarly, Fig. 16 shows the simulation
[see Fig. 16(a) and (b)] and the hardware emulation result [see
Fig. 16(c)] of the S.E. currents when the R.E. voltage (VRE ) is
stepped up from 0.8 to 1 p.u. keeping δP fixed at +15◦ . It can be
observed that the developed TLE-based emulation very closely
matches the PSCAD line simulation in all cases.

C. Symmetrical Faults
Fig. 17(a) and (b), respectively, shows the PSCAD simulated
and TLE emulated phase-a S.E. current response when the line
is subjected to a three-phase symmetrical fault at the R.E. bus
for 10 line cycles. In this case, the fault is triggered when the Fig. 18. Phase-a S.E. and R.E. currents during a three-phase fault
S.E. voltage (VSE ) is passing through its positive zero crossing. at 174 km from S.E. of the 500 km line. (a) PSCAD simulation. (b) TLE
Fig. 18 demonstrates the emulator’s ability to emulate faults emulation.

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 6204 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 8, AUGUST 2020

occurring at any intermediate point on the line with a max. error

of ± Δ2x = ± cΔ2t obs = ±6.2 km. Fig. 18(a) and (b), respectively,
shows the PSCAD simulated and TLE emulated transient S.E.
and R.E. currents when a three-phase fault occurs at 174 km
from S.E. of the 500-km line. In all the cases, the captured fault
dynamics in the TLE exhibit a high degree of matching with the
PSCAD simulations.

VI. CONCLUSION
The problem of medium and long transmission line emula-
tion in steady-state and symmetrical faults using power elec-
tronic converters was addressed in this paper. Applicability of Fig. 19. (a) Bergeron model of a long transmission line. (b) Original
various line models for long line emulation in real-time was in- line segmented into two parts at the fault point.
vestigated and a travelling wave-based numerical solution was
adopted, which considers the uniform distribution of all line
parameters as opposed to simple lumped models adopted in all The constants K1−5 depend on the line parameters. For two
previous attempts of line emulation. The developed emulator phases, the number of multiplications and additions involved
can also emulate faults occurring at an intermediate point on the are 20 and 16, respectively. In addition, we need eight FIFO
line. Furthermore, comprehensive analysis was presented that buffers. The size of each buffer is N = ( Δ τt obs ). As Δx = cΔtobs ,
helped the user to decide the correct power converter switching l = nΔx, and l = cτ , we have N = n. Now, say the fault has
frequency and line model solution interval to be used to em- occurred at x = jΔx. Hence, the line will be segmented into
ulate a large set of lines with varying parameters and length two sections, which will be solved using two separate Bergeron’s
while paying consideration to the power and digital hardware model [see Fig. 19(b)]. To do this, the information of the voltage
constraints of the emulator. Moreover, a novel digital architec- and current at the fault location prior to fault instant must be
ture to implement the adopted numerical scheme in real-time on available. Since the fault location can be chosen arbitrarily by
Zynq SoC-based digital platform was outlined. The proposed the user, we need to solve and store prefault values of vj and
emulation scheme along with the analysis provided made the ij , ∀ j ∈ {1, n − 1} to facilitate the fault computations. This is
developed platform (400 V, 15 kVA) an advanced and versatile done using the following equation:
TLE.   
vj [k] cosh γ(jΔx) Zc sinh γ(jΔx) vse [k]
= 1
.
APPENDIX ij [k] Zc sinh γ(jΔx) cosh γ(jΔx) ise [k]
A. Line Constants (26)

Therefore, for each location, we need to maintain two FIFO

   buffers with size n. So, total 4(n + 1) buffers (each of size n)
C1 = A/B, C2 = A /B, C3 = B /B, C4 = A /(2A)
need to be used and each buffer requires n move operations to
C5 = B  /(2A), C6 = 0.5C2 , C7 = 0.5C3 , where update its contents. Furthermore, using the Cordic algorithm,
 evaluation of each complex cosh and sinh function requires
√ G L RΔtobs two multiplications, 94 additions, and 48 data shift operations.
A= LC + Δtobs , B = L +
2 C 2 Hence, approximately 20(n − 1) numbers of multiplications
 and 192(n − 1) numbers of additions are required.

√ G L RΔtobs
A = LC − Δtobs , B  = L − .
2 C 2
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