Chapter 4:

Basic Computer Organization and Design

Topics to be covered:
• Instruction Codes
• Addressing modes
• Computer Registers
• Instruction Set
• Timing and Control
• Instruction Cycle
• Memory Reference Instructions
• Input –output devices
• Design of Basic Computer
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 3-1 Instruction Codes
• An instruction is a binary code that specifies a sequence of
micro-operations.
• Instructions are encoded as binary instruction codes.
• Instruction codes and data are stored in memory
• An instruction code is a group of bits that tells the computer to
perform a specific operation part.
• The computer reads each instruction from memory and places it
in a control register
• The control unit interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of micro-operations
• An instruction is divided into parts (basic part is the operation
part)
– The operation code (op code) of an instruction is a group of
bits that define operations such as add, subtract, multiply,
shift and compliment.
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 4-1 Instruction Codes cont.
• Instruction codes and data are stored in memory
• The computer reads each instruction from memory and places
it in a control register
• The control unit interprets the binary code of the instruction
and proceeds to execute it by issuing a sequence of micro-
operations
• An Instruction code is a group of bits that instructs the
computer to perform a specific operation (sequence of
microoperations such as add, subtract, shift, and
complement).
• Instruction code is divided into parts (basic part is the
operation part)

3
 4-1 Instruction Codes cont.
• The number of bits required for the operation code depends on
the total number of operations available in the computer
• n bit operation code -> 2n (or little less) distinct operations
• It must consist of at least n bits for a given 2n distinct
operations
It’s an
Op code ADD
Control operation
110010?????????? Unit

Read instruction
from memory
Memory
• Suppose we are having 64 operation then the length of OpCode will be 6. (since 26=64)
• The control unit decode the OpCode and determines the operations
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 4-1 Instruction Codes cont.
• An operation must be performed on some data stored in
processor registers or in memory
• An instruction code must therefore specify not only the
operation, but also the location of the operands (in registers
or in the memory), and where the result will be stored
(registers/memory)
• Memory words can be specified
in instruction codes by their address

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 4-1 Instruction Codes cont.
• Every Computer has its own particular instruction code
format.
– Instruction code formats are conceived by computer
designers who specify the architecture of the computer
• The simplest way to organize a computer is to have Processor
Register and instruction code with two parts.
• The first part specifies the operation to be performed and
the second specifies an address
15 12 11 0 What to do: Opcode
Opcode Address Where: memory address

Instruction Format
• The first part specifies the operation to be performed and second specifies an
address.
• The memory address tells where the operand in memory will be found.
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 4-1 Instruction Codes
• 212=4096 word of RAM , 12 bits are required for addressing
• 16 bit RAM (word length)

15 12 11 0 Memory
Opcode Address 15
4096x16
0
Instruction Format
Instructions
15 0
(program)
Binary Operand

Operands
(data)

15 0

Processor register
(Accumulator AC)

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 4-2 Addressing modes
• The operation field of an instruction specifies the operation to be
performed.
• This operation will be executed on some data which is stored in
computer registers or the main memory.
• The way any operand is selected during the program execution is
dependent on the addressing mode of the instruction.
– Addressing mode refers to the way in which the operand of an
instruction is specified.

• There are different Addressing Modes used for address portion of

the instruction code. Some of these addressing modes are
– Immediate addressing mode
– Direct addressing mode
– Indirect addressing mode

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 4-2 Addressing modes
• Immediate: the operand is given in the address portion
(constant)
– For example: ADD 7
• which says Add 7 to contents of accumulator. 7 is the operand here.
• Direct: the address points to the operand stored in the
memory
– effective address of operand is present in instruction itself.
– Single memory reference to access data.
– No additional calculations to find the effective address of the
operand.

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 4-2 Addressing modes
• Indirect: the address points to the pointer (another address)
stored in the memory that references the operand in memory
– This slows down the execution, as this includes multiple
memory lookups to find the operand.
• One bit of the instruction code can be used to distinguish
between direct & indirect addresses

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 4-2 Addressing modes
• The addressing mod (I) is 0 for direct addressing and 1 for
indirect mode in the following instruction format.
Instruction Format Effective
15 14 12 11 0 address
I Opcode Address

Direct Address Indirect address

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

Effective address: the address of the operand

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In order to cover the basic concepts behind
designing a computer, a model (an imaginary
system) will be presented to you throughout
this chapter. This model will be called the
“Basic Computer”
• The basic computer has 8 registers, a memory unit
and a control unit.
• A Common Bus System is used for transferring
data in a system.
• The basic computer has three instruction code
formats.

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 4-3 Computer Registers
• Computer instructions are normally stored in consecutive
memory locations and executed sequentially one at a time
• The control reads an instruction from a specific address in
memory and executes it, and so on
• This type of sequencing needs a counter to calculate the
address of the next instruction after execution of the current
instruction is completed
• It is also necessary to provide a register in the control unit for
storing the instruction code after it is read from memory
• The computer needs processor registers for manipulating data
and a register for holding a memory address

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Registers in the Basic Computer
11 0
PC
11 0
AR Memory

15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

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 S2
S1 Bus
S0
Memory unit
4096 x 16
7 Computer Registers
Address
Write Read Common Bus System
AR 1

LD INR CLR Bus is a set of wires in

PC 2 a computer along
LD INR CLR which information can
DR 3 be sent to and from
LD INR CLR other parts of the computer
Adder E
and AC 4
logic
LD INR CLR Register  Memory: Write operation
INPR M[AR]  DR
IR 5 Memory  Register: Read operation
LD
TR 6 DR  M[AR]
LD INR CLR IR←M[AR]
OUTR
Clock (note that AC cannot directly read
LD
16-bit common bus
from memory!!)

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 4-3 Computer Registers
Common Bus System cont.
• S2S1S0: Selects the register/memory that would use the bus
• LD (load): When enabled, the particular register receives the data
from the bus during the next clock pulse transition
• E (extended AC bit): flip-flop holds the carry
• DR, AC, IR, and TR: have 16 bits each
• AR and PC: have 12 bits each since they hold a memory address
• When the contents of AR or PC are applied to the 16-bit common
bus, the four most significant bits are set to zeros
• When AR or PC receives information from the bus, only the 12
least significant bits are transferred into the register
• INPR and OUTR: communicate with the eight least significant
bits in the bus
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 4-3 Computer Registers
Common Bus System cont.
• INPR: Receives a character from the input device
(keyboard,…etc) which is then transferred to AC
• OUTR: Receives a character from AC and delivers it to an output
device (say a Monitor)
• Five registers have three control inputs: LD (load), INR
(increment), and CLR (clear)
• The input data and output data of the memory are connected to the
common bus
• But the memory address is connected to AR
• Therefore, AR must always be used to specify a memory address

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 4-3 Computer Registers cont.

• The transition at the end of the cycle transfers the

content of the bus into the destination register, and the
output of the adder and logic circuit into the AC
• For example, the two microoperations
DR←AC and AC←DR (Exchange)
can be executed at the same time
• This is done by:

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 4-3 Computer Registers cont.

• 1- place the contents of AC on the bus (S2S1S0=100)

• 2- enabling the LD (load) input of DR
• 3- Transferring the contents of the DR through the adder
and logic circuit into AC
• 4- enabling the LD (load) input of AC
• All during the same clock cycle
• The two transfers occur upon the arrival of the clock
pulse transition at the end of the clock cycle

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 4-4 Instruction Set
• Computer instructions are a set of machine language instructions
that a particular processor understands and executes.
• A computer performs tasks on the basis of the instruction
provided.
• What is instruction set?
– An instruction set is a list of commands ready to be executed
directly by CPU.
– The entire group of instructions that a microprocessor supports
is called Instruction Set.
– It is the complete set of all the instructions in machine
code that can be recognized and executed by a central
processing unit.
• NB: Each computer has its unique instruction set
– Eg., Intel Microprocessor 8085 has 246 instructions
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 4-4 Instruction Set
Instruction Set Completeness
• The set of instructions are said to be complete if the
computer includes a sufficient number of instructions in
each of the following categories:
– Arithmetic, logical, and shift instructions
– Instructions for moving information to and from memory
and processor registers
– Program control instructions together with instructions that
check status conditions
– Input & output instructions

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 4.4 Instruction Classification
• Computer provides an extensive set of instructions to give the
user the flexibility to carryout various computational task.
• Most computer instruction can be classified into three categories.
1. Data transfer instruction
2. Data manipulation instruction
3. Program control instruction
1. Data Transfer Instruction
• used to move data from one place in the computer to another
without changing the data content.
• The most common transfers are: between memory and processes
registers, between processes register & input or output, and
between processes register themselves

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 4.4. Instruction Classification
Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

2. Data Manipulation Instruction

 It performs operations on data and provides the computational
capabilities for the computer.
 The data manipulation instructions in a typical computer are
usually divided into three basic types.
 Arithmetic Instruction
 Logical bit manipulation Instruction
 Shift Instruction. 23
 3.6 Instruction Classification
Arithmetic Instructions

Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions

Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI 24
 3.6 Instruction Classification
3. Program Control Instructions

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN
Compare(by - ) CMP
Test (by AND) TST

Examples of Program Control Instructions

• Program control instructions specify conditions for altering the
content of the program counter, while data transfer and
manipulation instructions specify conditions for data
processing operations.
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 4-4 Computer Instructions
• Thebasic computer has three Instruction code formats
• Each format has 16 bits

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

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 BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
Memory-Reference ADD 1xxx 9xxx Add memory word to AC
Instructions LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
Register -Reference CIR 7080 Circulate right AC and E
Instructions CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

I/O OUT F400 Output character from AC
Instructions SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off 27
 4-4 Computer Instructions
Instruction Set Completeness
• The set of instructions are said to be complete if the
computer includes a sufficient number of instructions
in each of the following categories:
– Arithmetic, logical, and shift instructions
– Instructions for moving information to and from
memory and processor registers
– Program control instructions together with instructions
that check status conditions
– Input & output instructions

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 4-5 Timing & Control
• The timing for all registers in the basic computer is
controlled by a master clock generator
• The clock pulses are applied to all flip-flops and
registers in the system, including the flip-flops and
registers in the control unit
• The clock pulses do not change the state of a
register unless the register is enabled by a control
signal (i.e., Load)

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 4-5 Timing & Control cont.
• The control signals are generated in the control unit
and provide control inputs for the multiplexers in the
common bus, control inputs in processor registers,
and microoperations for the accumulator
• There are two major types of control organization:
– Hardwired control
– Microprogrammed control

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 4-5 Timing & Control cont.
• In the hardwired organization, the control logic is
implemented with gates, flip-flops, decoders, and other
digital circuits.
• In the microprogrammed organization, the control
information is stored in a control memory (if the design
is modified, the microprogram in control memory has
to be updated)
• Microprogrammed control unit
– Is less complex and simpler to implement than
hardwired control unit
– Hence, it is cheaper and less error prone than hardwired
control unit
– But it is slower than hardwired control unit
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The Control Unit for the basic computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I
D7 Control Control
logic outputs
gates
T15
T0

15 14 . . . . 2 1 0
4 x 16
Sequence decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Hardwired Control Organization

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- Timing signals Generated by 4-bit sequence counter and 4x16 decoder
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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 4-5 Timing & Control cont.
• T0: AR←PC
– Transfers the content of PC into AR if timing signal T0
is active
– T0 is active during an entire clock cycle interval
– During this time, the content of PC is placed onto the
bus (with S2S1S0=010) and the LD (load) input of AR
is enabled
– The actual transfer does not occur until the end of the
clock cycle when the clock goes through a positive
transition
– This same positive clock transition increments the
sequence counter SC from 0000 to 0001
– The next clock cycle has T1 active and T0 inactive

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 4-6 Instruction Cycle
• A program is a sequence of instructions stored
in memory
• The program is executed in the computer by
going through a cycle for each instruction (in
most cases)
• Each instruction in turn is subdivided into a
sequence of sub-cycles or phases

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 4-6 Instruction Cycle cont.
• Instruction Cycle Phases:
– 1- Fetch an instruction from memory
– 2- Decode the instruction
– 3- Read the effective address from memory if
the instruction has an indirect address
– 4- Execute the instruction
• This cycle repeats indefinitely unless a HALT
instruction is encountered

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 4-6 Instruction Cycle
Fetch and Decode
• Initially, the Program Counter (PC) is loaded with
the address of the first instruction in the program
• The sequence counter SC is cleared to 0,
providing a decoded timing signal T0
• After each clock pulse, SC is incremented by
one, so that the timing signals go through a
sequence T0, T1, T2, and so on

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 4-6 Instruction Cycle
Fetch and Decode cont.
– T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR.

– T1: IR←M[AR], PC←PC+1

The instruction is fetched from the memory to IR
,and the PC is incremented.

– T2: D0,…, D7←Decode IR(12-14), AR←IR(0-

11), I←IR(15)

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 Start DETERMINE THE TYPE OF INSTRUCTION
SC  0

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.

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 MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- The execution of MR Instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E

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 4-7 Input-Output Devices
• Instructions and data stored in memory must
come from some input devices
• Computational results must be transmitted to the
user through some output device
• For the system to communicate with an input
device, serial information is shifted into the input
register INPR
• To output information, it is stored in the output
register OUTR

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4-7 Input-Output Devices

Input-output Serial registers and

terminal communication Computer
interface flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI

Serial Communications Path

Parallel Communications Path

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 4-7 Input-Output Devices cont.
• INPR and OUTR communicate with a
communication interface serially and with the AC in
parallel. They hold an 8-bit alphanumeric information
• I/O devices are slower than a computer system 
we need to synchronize the timing rate difference
between the input/output device and the computer.
• FGI: 1-bit input flag (Flip-Flop) aimed to control the
input operation

43
 4-7 Input-Output Devicescont.
• FGI is set to 1 when a new information is available
in the input device and is cleared to 0 when the
information is accepted by the computer
• FGO: 1-bit output flag used as a control flip-flop to
control the output operation
• If FGO is set to 1, then this means that the computer
can send out the information from AC. If it is 0, then
the output device is busy and the computer has to
wait!

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 4-8 Design of Basic Computer
1. A memory unit: 4096 x 16.
2. Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR,
and SC
3. Flip-Flops (Status): I, E, FGI, and FGO
4. Decoders:
1. a 3x8 Opcode decoder
2. a 4x16 timing decoder
5. Common bus: 16 bits
6. Control logic gates
7. Adder and Logic circuit: Connected to AC

45
 4-8 Design of Basic Computercont.
• The control logic gates are used to control:
– Inputs of the nine registers
– Read and Write inputs of memory
– Set, Clear, or Complement inputs of the flip-
flops
– S2, S1, S0 that select a register for the bus
– AC Adder and Logic circuit

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