Scribd
Upload
12 views

Lect8 RTL Design

Uploaded by

mlp
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
12 views

Lect8 RTL Design

Uploaded by

mlp
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 33

VLSI Design

Prof. Tassadaq Hussain Cheema

Register Transfer Level


Modeling
Outline
Verilog
Modelsim

2
Difference between Combination Logic and
Sequential Logic

In combinational circuits the output is a


function of the current inputs.
In sequential circuits the output depends on
previous as well as current inputs; such
circuits are said to have state.
Finite state machines and pipelines are two
important examples of sequential circuits.
Latch and Flipflop
Latch and FlipFlops

always @( posedge Clock or reset)


begin
Sig1 = A & B;
Y1 = Sig1 &C: //single flip-flop inferred
end
Contamination Delay
Contamination delay is the minimum
amount of time from when an input
changes until any output starts to change
its value.
It represents the time it takes for a change
in an input to propagate through the circuit
and affect the output.
Propagation Delay
The propagation delay, or gate delay, is the
length of time till when the output of a logic
gate becomes stable and valid.
Setup Time
Setup time is the minimum amount of time
the data signal should be held steady
before the clock event so that the data is
reliably sampled by the clock.
Hold Time
Hold time is the minimum amount of time
the data signal should be held steady after
the clock event so that the data are
reliably sampled.
Clock Skew

In reality, clocks have some


uncertainty in their arrival times called clock
skew.
Latch and FF based Design

always @( reset or clock or d)


begin
if(reset)
begin
end
end
always @( posedge clock or posedge d)
If (clock ==1)
Finite State Machine
A FSM is any circuit specifically designed to sequence
through specific patterns of states in a predetermined
sequential manner, and which conforms to the structure
shown in Figure. A state is represented by the binary value
held on the current state register.
The FSM structure consists of three parts and may, or may
not, be reflected in the structure of the HDL code that is
used to model it.
FSM
1. Current State Register. Register of n-bit flip-flops used to hold the
current state of the FSM. Its value represents the current stage in the
particular sequence of operations being performed. When operating, it
is clocked from a free running clock source.
2. Next State Logic. Combinational logic used to generate the next stage
(state) in the sequence. The next state output is a function of the state
machine's inputs and its current state.
3. Output Logic. Combinational logic is used to generate required output
signals. Outputs are a function of the state register output and possibly
state machine inputs.
State table and state diagrams
Condition/State Operation
if
if (condition)
statements;

if (condition)
Statements;
else
statements;

if (condition)
statements;
else if (condition)
Statements;
else
statements;
Case statement

reg [1:0] sel;


case (sel)
0 : y = a;
1 : y = b;
2 : y = c;
3 : y = d;
default : $display("Error in SEL");
endcase
Loop opeations
In Verilog, loops are generally avoided for
synthesizable designs due to their sequential
nature, which doesn't align well with hardware's
parallel execution model.
Instead, designers typically use constructs like
generate blocks for repetitive instantiation of
hardware components. This approach ensures
efficient synthesis and better adherence to
timing constraints, resulting in optimized
hardware designs.
System on Chip
Bus System
Address
Data
Control
Status
Layers
Application
Presentation
Session
Transmission
Network
Data Link
Physical
Network Layer
Defines protocol used for communication
between different modules or components in
the design.
Defines the rules and procedures for
transferring data, addressing, and controlling
access to the bus by multiple devices.
AXI (Advanced eXtensible Interface), AHB
(Advanced High-performance Bus), and
Wishbone.
Data Link Layer

Manages Effective Bandwidth while using data
packets or transactions between modules. In
other words, effective bandwidth is determined
by traffic pattern and queue size.

Buffer Requirement is determined by traffic
pattern.

Fram the data, error detection (such as parity
or CRC checks), and handling flow control
mechanisms if applicable.
Physical Layer
Defining the signals, buses, wires, or other
communication channels used for connecting
modules within the design.
• Power
Bitwidth vs Frequency
Vswing vs SNR
• Area
Bitwidth
Differential / Single-ended
• Circuitry
specifying the physical connections and ensuring proper signal integrity,
timing, and voltage levels.
Synchronization
A synchronizer is a circuit that accepts an
input that can change at arbitrary times
and produces an output aligned to the
synchronizer’s clock.
Synchronization
Arbiters

The arbiter determines which of two


(multiple) inputs arrived first.
Scheduler
Scheduler creates a link (allocate resource)
to one of the multiple inputs based on
programmed or run-time priorities
AMBA Bus
Request, Hold and Grant
Tasks
Write Encoder and Decoder IN RTL
Write A StateMachine RTL code for Two
Traffic Signals
Understand Blocking and Nonblocking
Assignments with codes.

Synthesize the RTL codes iverilog, vvp,


gtkwave, rewrite them in systemverilog

You might also like