University of Gondar Institute of Technology

IoT
Very Large Scale Integrated (VLSI ) Design
(CoEng4094)

Lecture 04: Introduction to HDL

By Beyene Jember
 Outlines
 An introduction to VHDL

 VHDL basics and syntax

 Design Units

 Architecture Modeling Fundamentals

 Understanding VHDL and Logic Synthesis

2
 HDLs in Digital System Design
 Hardware description languages (HDL)
 An essential computer aided design (CAD) tool for the modern design and synthesis of
digital systems
 Language to describe hardware
 Two popular languages
 VHDL: Very High Speed Integrated Circuits Hardware Description Language
 IEEE Standard 1076-1987/1993/200x
 Based on the ADA language
 Gate level through system level design and verification
• Verilog
 IEEE Standard 1364-1995/2001/2005
 Based on the C language
3
 ASIC – Application Specific Integrated Circuit
 HDLs in Digital System Design
 Applications of HDL:
 Model and document digital systems
 Different levels of abstraction
 Dataflow, Behavioral, structural, etc.
 Verify design
 Synthesize circuits
 Convert from higher abstraction levels to lower abstraction levels

4
 Simulation and Synthesis
 The two major purposes of HDLs are logic simulation and synthesis.
 Simulation: Verifying circuit/system design.
 Describe the behavior of the circuit in terms of input signals, the output signals,
knowledge of delays.
 Inputs are applied to a module and the outputs are checked to verify that the module operates
correctly.
 Behavior described in terms of occurrences of events and waveforms on signals
 Synthesis: Translating HDL to a circuit
 The textual description of a module is transformed into logic gates.
 Using components from a technology library
 Output is primitive cell-level netlist (gates, flip flops, etc.)
 When writing a VHDL program, think of the hardware that synthesis tool would infer
from it 5
 Development and Design Verification Cycle
 Typical Product Development & Design Verification Cycle Using HDLs
Specifications
Behavioral
Simulation
Architectural
design
RTL
Simulation
Register-level
design
Logic and
Timing
Gate-level
design
Timing
Physical
design

6
Implementation – ASIC, FPGA, etc.
 Basic Domains of HDLs
 HDL can describe a digital system at several different levels
 Data Flow level (RTL): a data flow description at the register level
 In this style of modeling the flow of data through the entity is expressed using
concurrent signal assignment statements.
 Structural level: Components and their interconnections (netlist) hierarchical designs
 In this style of modeling the entity is described as a set of interconnected statements.
 Behavioral level: describes I/O responses & behavior of design
 This style of modeling specifies the behavior of an entity as a set of statements that are
executed sequentially in the specified order.

7
 Intro to VHDL
 VHDL
 An industry standard language used to describe hardware from the abstract to concrete
level.
 It describes the behavior of an electronic circuit or system, from which the physical circuit
or system can then be attained (implemented).
 HDL allows one to model and develop complex digital systems in a dynamic
environment.
 Allows to raise the entry abstraction layer to a level which is more user friendly than
schematics
 VHDL is a standard, technology/vendor independent language, and is therefore portable and
reusable.
 VHDL is intended for circuit synthesis as well as circuit simulation.
8
 Intro to VHDL…
 The two main immediate applications of VHDL are
 In the field of Programmable Logic Devices (including CPLDs and FPGAs)
 In the field of ASICs (Application Specific Integrated Circuits).
 Once the VHDL code has been written, it can be used either to implement the circuit in a
programmable device (from Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for
fabrication of an ASIC chip.
 Currently, many complex commercial chips (microcontrollers, for example) are designed
using such an approach.

9
 Intro to VHDL…
 What are the challenges when you learn a new language, whether it be human language
computer language?
 When one learns a new language, one needs to study the alphabet of the new language, its
vocabulary, grammar, syntax rules, and semantics of language descriptions.
 The process of learning VHDL is not much different.
 One needs to learn the alphabet, vocabulary or lexical elements of the language, syntax
(grammar and rules), and semantics (meaning of descriptions).
 The lexical elements of the language include various reserved words, special symbols,
identifiers, and literals.
 The syntax or grammar determines what combinations of lexical elements can be
combined to make valid VHDL descriptions.
 Then one needs to understand the semantics or meaning of VHDL descriptions. 10
 Intro to VHDL…
 Identifiers are used both as names for VHDL objects, procedures, functions, processes, design
entities, etc., and as reserved words.
 VHDL identifier Rules
 VHDL is not case-sensitive.
 Identifiers may consist of letters, numbers and underscores (‘_’).
 The first character must be a letter, and two underscores in succession are not allowed.
 Meaningful, non-cryptic names should be used, based on English words.
 Use mixed-case with consistent use of case.
 Don’t use excessively long identifiers (use 15 characters or fewer).
 Don’t redefine predefined identifiers, such as BIT or TIME.
11
 All names and labels in a given entity and architecture must be unique
 Intro to VHDL…
 Whitespace and Comments
 Whitespace(spaces, carriage returns)
 Should be used to make models more readable.
 There is no difference between one whitespace character and many.
 Comments
 Comments may be included in a VHDL description by putting two hyphens on a line.
 (‘--’). All text between the hyphens and the end of the line is ignored.
 Each VHDL file should include a header as a comment, which typically contains:

 The name(s) of the design units in the file;  Any operating system and tool dependencies;
 File name;  The author(s), including a full address;
 A description of the code;  A revision list, including dates.
 Limitations and known errors;
12
 Intro to VHDL…
 Since VHDL is a hardware description language, it differs from an ordinary programming
language(Pascal, C, C++.) in several ways.
 Most importantly, VHDL has statements that execute concurrently since they must model
real hardware in which the components are all in operation at the same time.
 VHDL is for describing a digital system for mainly two purposes
 Simulation
 Synthesis
 Consists of
 Binary signals that may take values of 1 or 0.
 Components
 Gates, flip-flops, counters, etc.
 Transforms input signals to output signals
 Wires that connect components. 13
 EDA Tools
 There are several EDA (Electronic Design Automation) tools available for circuit synthesis
and simulation using VHDL.
 Some tools are offered by CPLD/FPGA companies
 Altera, Xilinx, etc.
 Others are offered by third-party software companies
 Mentor Graphics, Synopsys, Cadence, etc.
 Some examples are listed below.
 From Altera: Quartus II (for synthesis and graphical simulation)
 From Xilinx: ISE (XST for synthesis, ISE Simulator for simulation)
 From Mentor Graphics: Precision RTL and Leonardo Spectrum (synthesis), ModelSim
(simulation).
 From Synopsys/Synplicity: Design Compiler Ultra and Synplify Pro/Premier (synthesis), VCS
(simulation).
 From Cadence: NC-Sim (simulation)
 From Aldec: Active-HDL (simulation) 14
Translation of VHDL Code into a Circuit

15
 Simulation results from the VHDL
Simulation results from the VHDL design of full-adder

16
 Fundamental VHDL Units
 Library: Contains a list of all libraries to be used in the design.
 For example: ieee, std, work, etc.
 Entity: Specifies the I/O pins of the circuit.
 Used to define external view of a model. i.e. symbol
 Architecture: Used to define the function of the model. i.e. schematic
 Contains the VHDL code proper, which describes how the circuit should behave (function).
 Package- defines global information that can be used by many entities..
 Configuration- it binds component instances of a structure design into architecture pairs.
 It allows a designer to experiment with different variations of a design by selecting
different implementations.
17
 VHDL Design Units
 All VHDL designs provide an external interface and an internal implementation

18
 VHDL Design Unit: Entities
 An entity is a specification of the design's external interface
 It is a list with specifications of all input and output pins (PORTS) of the circuit
 A black box with interface definition
 Functionality will be defined in architecture
 Defines the inputs/outputs of a component (pins)
 Defines the generic parameters (e.g., signal width)
 A way to represent modularity in VHDL
 Reserved word ENTITY

19
 Entity Declarations
 Entity declarations specify the following:
1. The name of the entity
2. A set of generic declarations specifying instance-specific parameters(this is optional)
3. A set of port declarations defining the inputs and outputs hardware of the design
 port is used to specify connections between the entity and the outside world.

20
 Entity Declarations…
 The following is an example of an entity declaration for an AND gate:
ENTITY andgate IS
PORT ( NOTE:
a : IN std_logic; In the PORT declaration, the semi-colon is used as a
separator.
b : IN std_logic;
c : OUT std_logic
);
END andgate;

ENTITY comparator IS
PORT (
a_in : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
b_in : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
eq_out : OUT STD_LOGIC
);
END comparator;

21
 Example Entity Declaration…
Entity name

entity full_adder is
port ( -- I/O ports
a: in bit; -- addend input
b: in bit; -- augend input
I/O Port
cin: in bit; -- carry input Declarations
sum: out bit; -- sum output
cout: out bit); -- carry output
end full_adder;
Comments follow double-dash
Signal type

Signal name
Signal direction (mode)
22
 Entity: Ports
 Provide communication channels (pins) between the component and its environment
 Each port must have a name, direction and a type
 An entity may omit port declaration, e.g., in test bench
 Port directions:
 IN: The port is only an input port. A value of a port can be read inside the component, but
cannot be assigned. (The port should appear only on the right-hand side of the statement.)
 OUT: The port is only an output port. Assignment can be made to a port, but data from a port
cannot be read.
 INOUT: The port can be used as both an input and output. Bi-directional, assignments can be
made and data can be read. Multiple assignments allowed. (not recommended inside a chip)
 BUFFER: An out port with read capability. May have at most one assignment (not
recommended)
23
 Entity: Ports…
 Port name choices:
 Consist of letters, digits, and/or underscores
 Always begin with a letter
 Case insensitive
 Port direction choices:

 NOTE:
A buffer is an output that can be "read" by the architecture of the entity. 24
 Entity: Ports….
 IEEE standard 1164-1993 defines a package which provides a set of data types that are useful
for logic synthesis
 The external pins of a synthesizable design must use data types specified in the
std_logic_1164 package
 IEEE recommends the use of the following data types to represent signals in a
synthesizable system:
std_logic
std_logic_vector(<max> DOWNTO <min>)

25
 VHDL Design Unit: Architectures
 Architecture specifies the internals of a design unit and is coupled to a certain entity
 Defines functionality
 Every entity has at least one architecture
 One entity can have several architectures
 Architecture statements execute concurrently (Processes)
 Architectures can describe design on many levels
 RTL (Register Transfer Level)
 Structural level
 Behavioral level
 Switch-Level

26
 Architectures Declarations…
 Like in the case of an entity, the name of an architecture can be basically any name (except
VHDL reserved words), including the same name as the entity’s

ARCHITECTURE architecture_name OF entity_name IS

[declarations]
BEGIN
(code)
END architecture_name;

27
 Architectures Declarations…
 As shown above, an architecture has two parts:
 A declarative part (optional), where signals and constants (among others) are declared
 The code part (from BEGIN down).
 VHDL statements that assign output to each of the output signal defined in the
entity declaration.
 Two main approaches
1. Define new functionality with control statements
 e.g., if, for, case, (arch2) or (arch1 ) shown in the next slide examples
1. Instantiate existing components and define interconnections between them (structural)

28
Architectures Declarations…

29
 Architectures Declarations…
ARCHITECTURE arch1 OF andgate IS
BEGIN

c <= a AND b;

END arch1;

ARCHITECTURE arch2 OF comparator IS

BEGIN
eq_out <= ’1’ WHEN (a_in = b_in) ELSE ’0’;
END arch2;

30
 Signals
 Used for communication inside the architecture, carry data
 Signal serves to pass values in and out the circuit, as well as between its internal units.
 In other words, a signal represents circuit interconnects (wires).
 All Ports of an Entity are signals by default.
 Can represent wires and storage elements
 Wires (connecting logic gates)
 Wires with memory (i.e., FF’s, latches etc.)
 Signals are associated with a data type
 VHDL allows many types of signals
 bit vectors, integers, even multidimensional arrays and records
 Declared in the architecture body’s declaration section
 Defined inside architectures
31
 Signals…
 Signals have attributes
 VHDL is a strongly-typed language:
 Explicit type conversion is supported
 Implicit type conversion is not supported
 Signal declaration:
SIGNAL signal_name : datatype;
SIGNAL name : type [range] [:= initial_value];
 Signal assignment:
 signal_name <= new_value;
 Example:
SIGNAL control: BIT := '0';
SIGNAL count: INTEGER RANGE 0 TO 100;
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); 32
 Signals…
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY simp IS
PORT(
r, t, g, h : IN STD_LOGIC;
qb : OUT STD_LOGIC);
END ENTITY simp;
ARCHITECTURE logic OF simp IS
SIGNAL qa : STD_LOGIC;
SIGNAL qa : STD_LOGIC; Signal declaration inside architecture
BEGIN
qa <= r OR t;
qa <= r OR t; • r, t, g, h, and qb are signals (by default)
qb <= (qa AND NOT(g XOR h));
qb <= (qa AND NOT(g XOR h)); • qa is a buried signal and needs to be declared
END ARCHITECTURE logic;

33
 VHDL Design Unit: Configurations
 A configuration is a specification of the mapping between an architecture and a particular
instance of an entity.
 Associate an Entity and Architecture
 Associate a component to an Entity-Architecture
 By default, a configuration exists for each entity
 The default configuration maps the most recently compiled architecture to the entity
 Configurations are most often used to specify alternative architectures for hardware designs
 Widely used in Simulation environments
 Provides a flexible and fast path to design alternatives

CONFIGURATION <identifier> OF <entity_name> IS

FOR <architecture_name>
END FOR;
END CONFIGURATION; 34
 VHDL Design Unit: Libraries and Packages
 Libraries provide a set of packages, components, and functions that simplify the task of
designing hardware.
 Packages provide a collection of related data types and subprograms.
 Packages typically contain
 Constants
 Like header.h in conventional programming languages
 General-purpose functions
 E.g., Log2(x)
 Design-specific definitions
 E.g., own data types, records (structs)
35
 VHDL Design Unit: Libraries and Packages
 The following is an example of the use of the ieee library and its std_logic_1164
package:
LIBRARY library_name;
USE library_name.package_name.package_parts;
 At least three packages, from three different libraries, are usually needed in a design:
 ieee.std_logic_1164 (from the ieee library)
 standard (from the std library)
 work (work library).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
36
 VHDL Operators
 VHDL provides several kinds of pre-defined operators:
 Logical operators
 Arithmetic operators
 Relational operators
 Shift operators
 Assignment operators
 Concatenation operators

37
 Logical Operators
 Logic operators are the heart of logic equations and conditional statements
 Perform logical operations, such as AND, OR, NAND, NOR, NOT, and XOR.
 The operation can be on two operands or on a single operand.
 The operand can be single or multiple bits.
 The data must be of type BIT, STD_LOGIC, or STD_ULOGIC (or, obviously, their
respective extensions, BIT_VECTOR, STD_LOGIC_VECTOR, or STD_ULOGIC_VECTOR).
 These operators should appear only on the right-hand side of statements.
 The operators are bitwise.
 They operate on corresponding bits of two signals.
 Example:
Z := X XOR Y If X is four-bit signal 1011 and Y is four-bit signal 1010, then
Z = 0001
38
Logical Operators…

Notes: The NOT operator has precedence

over the others

39
 Relational Operators
 Relational operators are implemented to compare the values of two objects. The result
returned by these operators is in Boolean: false (0) or true (1).
 VHDL has extensive relational operators.
 Their main implementations are in the if and case statements.

If (A = B) then .....

If (A < B) then .....

40
Arithmetic Operators
 VHDL arithmetic operators operate on numeric
and physical operand.
 Physical data types are those that can be
measured in units, such as time and voltage.

41
 Shift and Rotate Operators
 Shift and rotate operators are implemented in many applications, such as in multiplication and
division.
 A shift left represents multiplication by two, and
 a shift right represents division by two.
 Used for shifting data
 Shift operators are unary operators; they operate on a single operand.
 The left operand must be of type BIT_VECTOR, while the right operand must be an
INTEGER ( + or - in front of it is accepted).

42
Shift and Rotate Operators…

43
 Assignment Operators
 Assignment Operators are used to assign values to signals, variables, and constants.
 They are:
 <= Used to assign a value to a SIGNAL.
 := Used to assign a value to a VARIABLE, CONSTANT, or GENERIC.
 Used also for establishing initial values.
 => Used to assign values to individual vector elements or with OTHERS

44
 Data Attributes
 The pre-defined, synthesizable data attributes are the following:
 d’LOW: Returns lower array index  d’LEFT: Returns leftmost array index
 d’HIGH: Returns upper array index  d’RIGHT: Returns rightmost array index
 d’RANGE: Returns vector range  d’LENGTH: Returns vector size
 d’REVERSE_RANGE: Returns vector range in reverse order
 SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0); Then:
d'LOW=0, d'HIGH=7, d'LEFT=7, d'RIGHT=0, d'LENGTH=8,
d'RANGE=(7 downto 0), d'REVERSE_RANGE=(0 to 7).

45
 Signal Attributes
 Let us consider a signal s. Then:
 s‘EVENT: Returns true when an event occurs on s
 s’STABLE: Returns true if no event has occurred on s
 s’ACTIVE: Returns true if s= ‘1’
 s’QUIET <time>: Returns true if no event has occurred during the time specified
 s’LAST_EVENT: Returns the time elapsed since last event
 s’LAST_ACTIVE: Returns the time elapsed since last s = ‘1’
 s’LAST_VALUE: Returns the value of s before the last event; etc.

46
 Signal Attributes
IF (clk‘ EVENT AND clk='1')... -- EVENT attribute used with IF
IF (NOT clk'STABLE AND clk='1')... -- STABLE attribute used with IF
WAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT attribute used with WAIT
IF RISING_EDGE(clk)... -- call to a function

47
 Data Types
 VHDL is a type-oriented language; many operations will not be executed if the right type for
the operands has not been chosen.
 The type of any element or object in VHDL determines the allowed values that element can
assume.
 Objects in VHDL can be Signal, Variable, or Constant.
 These objects can assume different types; these types can be classified into five groups
depending on the nature of the values the object can assume:
 Scalar, composite, access, file, and other

48
Data Types…

49
 Data Types…
 VHDL contains a series of pre-defined data types, specified through the IEEE 1076 and IEEE
1164 standards.
 More specifically, such data type definitions can be found in the following packages / libraries:
 std: Defines BIT, BOOLEAN, INTEGER, and REAL data types.
 std_logic_1164 : Defines STD_LOGIC and STD_ULOGIC data types.
 std_logic_arith : Defines SIGNED and UNSIGNED data types, plus several data
conversion functions, like conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), and
conv_std_logic_vector(p, b).

50
 Data Types…
 BIT and BIT_VECTOR :2-level logic (‘0’, ‘1’)
SIGNAL x: BIT; -- x is declared as a one-digit signal of type BIT.
-- y is a 4-bit vector, with the leftmost bit being the MSB.
SIGNAL y: BIT_VECTOR (3 DOWNTO 0);
-- w is an 8-bit vector, with the rightmost bit being the MSB.
SIGNAL w: BIT_VECTOR (0 TO 7);

x <= '1'; -- x is a single-bit signal whose value is '1'

-- Notice that single quotes (' ') are used for a single bit.
y <= "0111"; -- y is a 4-bit signal whose value is "0111" (MSB='0')
-- Notice that double quotes (" ") are used for vectors.
w <= "01110001"; -- w is an 8-bit signal, whose value is "01110001" (MSB='1')

51
 Data Types…
 STD_LOGIC and STD_LOGIC_VECTOR: 8-valued logic

‘X’ Forcing Unknown (unknown) ‘W’ Weak unknown

‘0’ Forcing Low ( logic ‘1’) ‘L’ Weak low
‘1’ Forcing High logic ‘0’) ‘H’ Weak high
‘Z’ High impedance (tri-state buffer) ‘–’ Don’t care
-- x is declared as a one-digit (scalar) signal of type STD_LOGIC.
SIGNAL x: STD_LOGIC;
-- y is declared as a 4-bit vector, with the leftmost bit being the MSB.
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";
-- The initial value (optional) of y is "0001".
--Notice that the ":=" operator is used to establish the initial value.
52
 Data Types…
 BOOLEAN: True, False.
 INTEGER: 32-bit integers (from -2,147,483,647 to +2,147,483,647).
 NATURAL: Non-negative integers (from 0 to +2,147,483,647).
 REAL: Real numbers ranging from -1.0E38 to +1.0E38. Not synthesizable.
 Physical literals: Used to inform physical quantities, like time, voltage, etc
 Character literals: Single ASCII character or a string of such characters.
 SIGNED and UNSIGNED: data types defined in the std_logic_arith package of the ieee
library.

53
 Data Types…
x0 <= '0'; -- bit, std_logic, or std_ulogic value '0'
x1 <= "00011111"; -- bit_vector, std_logic_vector, std_ulogic_vector, signed,
or unsigned
x2 <= "0001_1111"; -- underscore allowed to ease visualization
x3 <= "101111" -- binary representation of decimal 47
x4 <= B"101111"
x5 <= O"57" -- octal representation of decimal 47
x6 <= X"2F" -- hexadecimal representation of decimal 47
n <= 1200; -- integer
m <= 1_200; -- integer, underscore allowed
IF ready THEN... -- Boolean, executed if ready=TRUE
y <= 1.2E-5; -- real, not synthesizable
q <= d after 10 ns; -- physical, not synthesizable
54
 Data Types…
 Read more on Data Types
 Signed and Unsigned Data Types
 Enumerated Data Type
 Arrays
 User Defined data type
 Records
 Data Conversion

55
 Data Objects
 In VHDL code information is represented as data objects.
 VHDL provides two objects for dealing with non-static data values: signal and variable
 It also provides means for establishing default (static) values: CONSTANT
 A signal can be declared in a package, entity or architecture (in its declarative part).
 Variable can only be declared inside a piece of sequential code (in a Process, for example)
 Constant and signal can be global (that is, seen by the whole code), and can be used in either
type of code, concurrent or sequential.
 A variable, on the other hand, is local, for it can only be used inside a piece of sequential
code (that is, in a process, function, or procedure).

56
 Constant
 A Data Objects of class constant holds a single value of a specific type.
 The value is assigned to the constant during its declaration and the value cannot be changed
 A constant can be declared in a Package, Entity, or Architecture.
 Constant declaration:
constant name : type := value;
constant Bus_Width: integer := 16;
constant GNDLogic: bit := '0';
constant AnchoBus: integer := 16;
constant Message: string := “End of simulation";
constant error_flag: boolean := true;
constant ClkPeriod: time:= 50 ns;
constant datamemory : memory := (('0','0','0','0'),
('0','0','0','1'),
('0','0','1','1'));
57
 Variable
 Contrary to constant and signal, a variable represents only local information.
 It can only be used inside a process, function, or procedure (in sequential code), and its value
can not be passed out directly.
 Variables are used to hold intermediate values between sequential instructions (like variable
in the conventional software languages)
 To declare a variable, the following syntax should be used:
variable name : type [:= init_value];

 Examples:
variable control: BIT := '0';
VARIABLE count: INTEGER RANGE 0 TO 100;
VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
58
 Variable
 Contrary to constant and signal, a variable represents only local information.
 It can only be used inside a process, function, or procedure (in sequential code), and its value
can not be passed out directly.
 To declare a variable, the following syntax should be used:
variable name : type [range] [:= init_value];
 Examples:
variable control: BIT := '0';
variable count: INTEGER RANGE 0 TO 100;
variable y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
 Variable assignment statement
<variable> := <expression>;
count := 5;
59
Signal versus Variable

60
VHDL Reserved Words

61
 Next Classes
 Combinational Logic
 Concurrent Statement
 Concurrent Signal Assignment Statements
 Simple signal assignment statements(for logic or arithmetic expressions)
 Selected signal assignments (when-else )
 Conditional signal assignments (with-select-when)
 Generate statements
 Component instantiation statement
 Sequential Logic
 Processes
 Sequential Statements
 IF, WAIT, CASE, and LOOP Statements
 Finite State Machine(FSM) 62
You are in control of your thoughts, actions, and
feelings.
You are in control of your words, the series you
watch on TV, and the people you spend your time
with.
If you don't like your results, change your input
- your thoughts, emotions, and expectations.