University of Gondar Institute of Technology

IoT
Very Large Scale Integrated (VLSI ) Design
(CoEng4094)

Lecture 04C: VHDL for Sequential logic

By Beyene Jember
 Outlines
 Styles of Description in VHDL
 Data flow
 Behavioral
 Structural
 Switch level
 Mixed type
 VHDL Sequential Statements
 Process Statement
 IF statements
 CASE statements
 LOOP statement
 Variable Assignment 2
 Styles of Description in VHDL
 Several styles of code writing can be used to describe the system.
 Selection of the styles depends on the available information on the system.
 For example:
 Some systems may be easily described by the Boolean function of the output;
 While other systems, such as biological mechanisms, it will be hard to obtain the
Boolean function of the output, but they can be described if the relationship between
the changes of the output with the input is known.
 Types of VHDL Description (Modeling Styles)
1. Data flow
2. Behavioral
3. Structural
4. Switch level
5. Mixed type 3
Styles of Description in VHDL
VHDL Description
Styles

dataflow structural behavioral

Concurrent Components Sequential statements

statements and • Registers
interconnects • Shift registers
• Counters
• State machines
Synthesizable
4
 Data Flow Description
 A data-flow style description specifies a circuit as a concurrent representation of the flow of
data through the circuit.
 It describes how the system’s signals flow from the inputs to the outputs.
 It simulates the system to be described by showing how the signal flows from the system
inputs to its outputs.
 Usually, the description is done by writing the Boolean or Arithmetic function of the outputs.
 The data-flow statements are concurrent;
 The three forms of concurrent statements, Simple signal assignment, Conditional and
Selected signal assignments are all statements that are found in data-flow style description.
 Data-flow modeling works fine for small and relatively simple circuits.
 Such as adders, multiplexers, and latches.
 But as circuits become more complicated, it is often advantageous to switch to behavioral
style models.
5
 Data Flow Description…
 Half Adder

A
Sum

B Cout

A B Sum Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Sum  AB  AB  A  B
Cout  AB
6
 Behavioral Description
 A behavioral description models the system as to how the outputs behave with the inputs;
usually, a flowchart is used to show this behavior.
 It describes the system by showing how outputs behave with the changes in inputs.
 In this description, details of the logic diagram of the system are not needed;
 what is needed is how the output behaves in response to a change in the input.
 The heart of the behavioral style description is the process statement
 The behavioral description is a powerful tool to describe systems for which Boolean function
or digital logic structures are not known or are hard to generate.
 Examples of such systems are
 Complex arithmetic units
 Computer control units
 Biological mechanisms that describe the physiological action of certain organs such as
the brain, kidney or heart. 7
 Behavioral Description
 Behavioral description of the output S of the half adder.

Behavior of output S with changes in inputs a and b

8
 Structural Description
 Structural description models the system as components or gates.
 This description is identified by the presence of the keyword component in the architecture.
 It is the VHDL modular design approach directly supports hierarchical design which is
essentially employed when attempting to understand complex digital designs.
 Structural description is very close to schematic simulation.
 Structural description simulates the system by describing its logical components.
 The components can be
 Gate level (such as AND gates, OR gates, or NOT gates), or
 A higher logical level, such as register-transfer level (RTL) or processor level
 All statements in structural description are concurrent.
 At any simulation time, all statements that have an event are executed concurrently.
 Structural description is best implemented when the digital logic of the details of hardware
9
Structural Description…

10
 Switch-Level Description
 The switch-level description is the lowest level of description. The system is described using
switches or transistors.
 It implements switches (transistors) to describe relatively small-scale digital systems.
 It is usually implemented in very-large-scale integrated (VLSI) circuit layouts.
 It is the lowest HDL logic level that can be used to simulate digital systems.
 Only small-scale systems can be simulated using pure switch-level description.

11
 Mixing Description Styles
 Mixing Description Styles Inside of an Architecture

architecture architecture_name of entity_name is

-- Declarations: signals, constants, functions,
-- procedures, component declarations, ...
begin
-- Concurrent statements:
-- Concurrent simple signal assignment
-- Conditional signal assignment
-- Selected signal assignment
Concurrent Statements
-- Component instantiation statements

-- Process statement
-- inside process you can use only
--sequential statements
end architecture_name;
12
VHDL Sequential Statements

VHDL Sequential Statements

13
 VHDL Sequential Statements
 We have introduced concurrent assignment statements in the previous lecture
 All have the property that the order in which they appear in VHDL code does not affect the
meaning of the code
 Concurrent code is intended only for the design of combinational circuits
 VHDL provides a second category of statements, sequential assignment statements, for which
the ordering of the statements may affect the meaning of the code.
 The order or sequence of sequential statements is very important
 VHDL requires that sequential assignment statements be placed inside another statement, the
process statement
 Sequential Statements
• IF statements
• CASE statements
• LOOP statement
• Variable Assignment
• Signal Assignment 14
 VHDL Sequential Statements
 Sequential code can be used indistinctly to design both sequential circuit and combinational
circuits.
 Can be used to model, simulate and synthesize:
 Combinational logic circuits
 Sequential logic circuits
 They are used inside of
 Processes
 Functions
 Procedures
 Note that we should not confuse sequential statements with sequential circuits.
 Sequential statements are VHDL statements inside a process
 Sequential circuits are circuits with internal states. 15
 Process Statement
 Process Statement is the basic unit of behavioral descriptions.
 A process is a concurrent statement, but it is the primary mode of introducing sequential
statements.
 That is, a process is executed in just one delta time
 The execution time of a process can be thought of as zero time.
 Multiple processes can be executed in parallel
 Statements inside the process are evaluated in sequential order
 This is true from a simulation standpoint
 From a synthesized hardware point-of-view, multiple assignments to a single signal
(variable) generally implies multiplexing of the assignments to produce a single output
 Assignments made inside the process are not visible outside the process until all statements in
the process have been evaluated
 If there are multiple assignments to the same signal inside a process, only the last one has any
16
visible effect.
 Process Statement
 A process has two states: execution and wait(suspend)

execution

Until a
condition is wait
satisfied

 Once the process has been executed, it will wait for the next satisfied condition
 From the traditional programming view, it is an infinite loop
17
Process - Syntax

process sensitivity_list 1
[declarations;]
begin
sequential_statements;
end process;

process
2
[declarations;]
begin
sequential_statements;
wait on sensitivity_list;
end process;
18
 Process - Syntax
[process_label:] process [(sensitivity_list)] [is]
[process_data_object_declarations]
begin
variable_assignment_statement
signal_assignment_statement
wait_statement
if_statement
case_statement
loop_statement
null_statement
Sequential Statements
exit_statement
next_statement
assertion_statement
report_statement
procedure_call_statement
return_statement
[wait on sensitivity_list]
end process [process_label]; 19
 Parts of a Process
 sensitivity_list
 List of all the signals that are able to trigger(activate) the process
 This list includes, at most, all the (input) signals used inside the process
 Simulation tools monitor events on these signals
 Any event on any signal in the sensitivity list will cause to execute the process at least once.
 Whenever there is an event on any of the those signals, the process fires.
 Every time the process fires, it will run in its entirety
 declarations
 Declarative part. Types, functions, procedures and variables can be declared in this part
 Each declaration is local to the process

 sequential_statements
 All the sequential statements that will be executed each time that the process is activated
20
 Signal Behavior in a Process
 While a process is running ALL the SIGNALS in the system remain unchanged
 Signals are unaffected CONSTANTS during process execution, EVEN after a signal
assignment, the signal will NOT take a new value.
 Signal are updated at the end of a process or in a wait statement

 Signals are the interface between VHDL’s concurrent domain and the sequential domain
within a process
 Signals are a mean of communication between processes ->
 VHDL can be seen as a network of processes intercommunicating via signals.
 While a process is running ALL the Variables in the system are updates IMMEDIATELY by a
variable assignment statement

21
 Combinational Process
 In a combinational process all the input signals must be contained in the sensitivity list
 If a signal is omitted from the sensitivity list, the VHDL simulation and the synthesized
hardware will behave differently
 All the output signals from the process must be assigned a value each time the process is
executed.
 If this condition is not satisfied, the signal will retain its value (latch!)

22
Combinational Process
entity example3 is
port ( a, b, c: in bit;
z, y: out bit);
end example3;
architecture beh of example3 is
begin
process (a, b, c)
begin
if c='1' then
z <= a;
else
y <= b;
end if;
end process;
end beh;

23
 Clocked Process
 Clocked processes lead to all the signals assigned inside the process resulting in a flip-flop
 Variables can also give a flip-flop in a clocked process.
 If a variable is read before it is assigned a value, it will result in a flip-flop for the
variable (bad practice!)
 If a signal is not assigned a value in a clocked process, the signal will retain the old value
 A clocked process can result in combinational logic besides the flip-flop(s).
 All logic caused by a signal assignment in a clocked process will end up on the “left” of
the flip-flop (before the flip-flop’s input)

24
Clocked Process

25
 Sequential Signal Assignment Statement
 The simplest sequential statement is a sequential signal assignment statement.
 The simplified syntax is
Signal_name <= value-expression;
 The statement must be encapsulated inside a process.
 Although its syntax is similar to that of a simple concurrent signal assignment statement, the
semantics are different.
 When a signal is assigned multiple times inside a process, only the last assignment takes
effect. process(a, b)
process(a, b)
begin
begin
c <= a and b;
c <= a or b;
c <= a or b;
end process;
end process;

 The result will be very different if the multiple assignments are the concurrent signal
assignment statements. 26
 Variable Assignment Statement
 The syntax of a variable assignment statement is
Variable_name := value_expression;
 The immediate assignment notion, :=, is used for the variable assignment.
 There is no time dimension (i.e., no propagation delay) and the assignment takes effect
immediately.
signal a, b, y : std_logic;
process (a, b)
variable tmp0, temp1,temp2 : std_logic;
begin
tmp0 := '0';
tmp1 := tmp0 or a;
tmp2 := tmp1 or b ;
y <= tmp2;
end process; Conceptual implementation of simple variable assignments

27
 Sequential if Statement
if (boolean_expr_l) then
sequential_statements;
elsif (boolean_expr_2) then
sequential_statements;
 Syntax elsif (boolean_expr_3) then
sequential_statements;
...
else
sequential_statements;
end if;

 The Boolean_expr_i term is a Boolean expression that returns true or false.

These Boolean expressions are evaluated sequentially.
 When an expression is evaluated as true, the statements in the corresponding branch will be
executed and the remaining branches will be skipped.
 If none of the expressions is true and the else branch exists, the statements in the else branch will
be executed 28
 Sequential if Statement
 The conditions in the successive branches of an if statement are evaluated independently
 There can be any number of conditions, each of which will be independent of the others.
 Each branch of an if statement can contain any number of statements, it is not limited to a
single statement.
 Due to the structure of the if statement, the earlier conditions are tested first
=> There is a priority.
 In a multi-branch if statements, each condition can be, and will normally be, dependent on
different signals and variables.
 A case statement should be used when every branch is dependent on the same signal or
variable.
 It’s important to remember the prioritization of the conditions to avoid redundant tests.
 An if statement must always be terminated with an end if
29
 Sequential if Statement
 Example 1: Implements a 2:1 MUX using if statement.

architecture behavior of mux2to1 is

begin
process (A,B,sel)
begin
if sel = '0' then
out <= A;
else
out <= B;
end if;
end process;
end behavior;

30
 Sequential if Statement
 Example 2: Implements a 4:1 MUX using if statement.
architecture behavior of mux4_to_1 is
begin
process (D0, D1, D2, D3, sel)
begin
if (sel = "00") then
y <= D0;
elsif (sel =“01”) then
Y <= D1;
elsif(sel =“10”) then
Y <= D2;
else
Y <= D3;
end process;
end behavior;

31
 Sequential if Statement
 Example 2: Implements a 4:1 MUX using if statement.

32
 Sequential if Statement
 For the priority encoder (4-to-2)
architecture behavior of priority is
begin
process (I) Input Output
begin I3 I2 I1 I0 Y1 Y0 V
if I(3) = '1' then 1 x x x 1 1 1
Y <= "11";
0 1 x x 1 0 1
elsif I(2) = '1' then
Y <= "10"; 0 0 1 x 0 1 1
elsif I(1) = '1' then 0 0 0 1 0 0 1
Y <= "01";
0 0 0 0 0 0 0
else
Y <= "00";
end if;
end process;
V <= '0' when I = "0000" else '1';
end behavior;
33
 if Statement Vs. Conditional Signal Statement
 An if statement and a concurrent conditional signal assignment statement are somewhat
similar.
 The two statements are equivalent if each branch of the if statement contains only a
single sequential signal assignment statement.
 As in a conditional signal assignment statement, the if statement infers a similar priority
routing structure during synthesis
 Consider the following conditional signal assignment statement:

34
 Case statement
 The simplified syntax of a case statement is

case sel is
when choice_l =>
sequential statements;
when choice_2 =>
sequential statements;
when choice_3 =>
sequential statements;
...
when choice_i =>
sequential statements;
when others =>
sequential statements;
end case;
35
 Case statement…
 A case statement uses the value of case_expression to select a set of sequential statements.
 The case_expression can be a signal, variable, any discrete type: integer or
enumerated, or an array
 The case_expression term functions just as the select_expression term of the concurrent
selected signal assignment statement.
 Its data type must be a discrete type or one-dimensional array.
 The choice_i term is a value or a set of values that are compared with case_expression.
 The choices have to be mutually exclusive (no value can be used more than once) and all-
inclusive (all values must be included).
 The type of each choice must be of the same type as the type resulting from the
case_expression.
 The special choice others is used to handle all possible values of case_expression not
mentioned on previous alternatives.
36
 Case statement …
 2-to-1 mux Case Statement implementation

37
 Case statement …
 4-to-1 mux Case Statement implementation

38
 Case statement …
 2-to-4 binary Decoder Case Statement implementation

X1 y
3
X
X0 y
2
Y
y
1
en EN y
0

39
 Case statement …
 2-to-4 binary Decoder Case Statement implementation

40
 Case statement Vs. Selected signal statement
 A case statement and a concurrent selected signal assignment statement are somewhat similar.
 The two statements are equivalent if each branch of the case statement contains only a
single sequential signal assignment statement.
 For example, the previous statement.

 As in a selected signal assignment statement, the case statement infers a similar multiplexing
structure during synthesis.
41
 Case statement Vs. Selected signal statement
 The simple if and case statements are equivalent to the conditional and selected signal
assignment statements.
 However, an if or case statement allows any number and any type of sequential statements in
their branches and thus is more flexible and versatile.
 Disciplined use can make the code more descriptive and even make a circuit more efficient.

42
 Unintended memory
 Although a process is flexible, a subtle error in code may infer incorrect implementation.
 One common problem is the inclusion of unintended memory in a combinational circuit.
 If the target signal is part of a combinatorial circuit, it has to gets a value under all
possible conditions of the branch (if/case statement) in the process.
 The VHDL standard specifies that a signal will keep its previous value if it is not
assigned a value in a process.
 During synthesis, this infers an internal state (via a closed feedback loop) or a
memory element (such as a latch).

 Generally the following conditions infer unwanted memory.

 Incomplete sensitivity list
 Incomplete branch
 Incomplete signals assignment
43
 Unintended memory…

There are two usual situations where a signal does not receive a value in a process:
 A missing else in if statement
 When the signal is not assigned value in some branches of the if/case statement

The signal preserve the previous value

unwanted Latch!

44
 Unintended memory…
 To prevent unintended memory, we should observe the following rules while developing
code for a combinational circuit:
1. Include all input signals in the sensitivity list.
 All input signals and signals on left hand side (LHS) of signal assignments must be
included in the sensitivity list!
2. Include the else branch in an if statement and when others in case statement.
3. Assign a value to every signal in every branch.
 Make sure that every signal that gets a value in an if statement also get assigned on
every branch of the if and in the else part.
or
 Make sure to have the signals assigned in all when clauses

2. Initialize the signals in the an unconditional assignment before the if/case statements.
 Assign a default value for all output (LHS) signal in the beginning of the process
45
 Unintended memory
 For example, code segment for comparator

 Although the syntax is correct, it violates all three rules.

 gt will keep its previous value when the a>b expression is false and a latch will be
inferred accordingly.
 eq also keep its previous value when a=b is false i.e. implicit memory is introduced

46
 Unintended memory
 The corrected codes that avoid Unintended Memory

47
 Synthesis Guidelines
 Guidelines for using sequential statements
 Variables should be used with care. A signal is generally preferred.
 A statement like n:=n+1 can cause great confusion for synthesis
 Except for the default value, avoid overriding a signal multiple times in a process.
 Think of the if and case statements as routing structures rather than as sequential control
constructs.
 An if statement infers a priority routing structure, and a larger number of elsif branches
leads to a long cascading chain.
 A case statement infers a multiplexing structure, and a large number of choices leads to a
wide multiplexer.
 Think of a for loop statement as a mechanism to describe the replicated structure

48
 Synthesis Guidelines
 Guidelines for combinational circuits
 Include all input signals in the sensitivity list to avoid unexpected behavior
 Include all branches of an if statement to avoid unwanted latch.
 An output signal should be assigned in every branch of the if and case statements to avoid
unwanted latch.
 It is a good practice to assign a default value to each signal at the beginning of the process.

49
 Modeling Sequential Circuits
 Introduction to Sequential Circuit
 Basic storage elements
 D latch
 D FF (Flip-Flop)
 Synchronous and asynchronous reset
 Multiplexed inputs
 Enable inputs
 Registers
 Counters
 Variables

50
 Modeling Sequential Circuits
 A sequential circuit is a circuit that has an internal state, or memory.
 Unlike a combinational circuit, in which the output is a function of input only, the output
of a sequential circuit is a function of the input and the internal state.

Inputs Outputs
Combinational Logic
Present State
Next State
Memory
Clock (State)

 Synchronous sequential circuits use a clock signal

 The clock signal is an input to the memory elements
 The clock determines when the memory should be updated
 The present state => output value of memory (stored)
 The next state = input value to memory (not stored yet) 51
 Modeling Sequential Circuits
 General sequential circuits
 A general sequential circuit is an interconnection of gates and flip-flops
 The flip-flops are called state registers
 The current state and current input determine
 The current output
 The next state, that is, the state after one clock pulse
 Sequential circuits use combinational logic to determine what the next state of the system
should be, based on the present state and the current input values.
input + present state => next state

52
 Modeling Sequential Circuits
 There are two Types of Sequential Circuits
1. Synchronous Sequential Circuit
 Uses a clock signal as an additional input
 Changes in the memory elements are controlled by the clock
 Changes happen at discrete instances of time
2. Asynchronous Sequential Circuit
 No clock signal
 Changes in the memory elements can happen at any instance of time

 A synchronous sequential circuit, in which all memory elements are controlled by a global
synchronizing signal, greatly simplifies the design process and is the most important and
commonly used design methodology.
 In this methodology, all storage elements are controlled (i.e., synchronized) by a global clock
signal and the data is sampled and stored at the rising or falling edge of the clock signal
53
 Basic Memory elements
 Basic memory elements
 D latch
 D FF (Flip-Flop)
 Register
 RAM (not possible to derive a portable, device-independent VHDL code to infer a
RAM module)

 The most basic storage component in a sequential circuit is a D-type flip-flop (D-FF).
 A general sequential circuit is an interconnection of gates and flip-flops

54
 Basic model of a synchronous circuit
 Conceptual diagram of a synchronous sequential circuit

Output output
logic

external Next-state D Q
logic state_next state_reg
inputs FF
clk

State registers (state_reg) represent the memory elements.

Next state logic represent the combinational circuit that determines state_next

55
 Basic model of a synchronous circuit
 Synchronous Circuits Operation is as follows:
 At the rising edge of the clock, state_next is sampled and stored into the register
(and becomes the new value of state_reg)
 The external inputs and state_reg signals propagate through next-state and output
logic to determines the new values of the state_next and output signals
 At the rising edge of the clock, the new value of state_next is sampled and stored
and the process repeats
Note that the clock period needs to be large enough to accommodate the propagation delay
of the next-state logic, the clock-to-q delay and the setup time of the FFs

56
 Basic model of a synchronous circuit
 Advantages of synchronous design
 A single global clock makes the task of satisfying the timing constraints of a design
with of thousands of FFs manageable and doable
 The synchronous model separates the combinational components from the memory
elements, making it possible to treat the combinational part by itself
 Propagation delay anomalies such as hazards can be dealt with easily by focusing on
the worst case timing behavior
 Therefore, the synchronous model reduces a complex sequential circuit to a single closed
feedback loop and greatly simplifies the design process

57
 Basic model of a synchronous circuit
 Types of synchronous circuits
 Regular sequential circuit
 State representation, transitions and next-state logic have a simple, regular
pattern, as in a incrementor or shift register
 Random sequential circuit (FSM)
 More complicated state transitions and no special relationship between states
and their binary representations -- next-state logic is random
 Combined sequential circuit (FSM with a Data path, FSMD -- RTL)
 Combines regular sequential circuit and an FSM, with FSM acting as control
for the sequential circuit

58
 D-Latch
Truth table
D Q
Clock D Q(t+1)
Clock
0 – Q(t)
1 0 0
Graphical symbol 1
1 1

t1 t2 t3 t4
Clock
D
Q
Time

Timing diagram
59
 D-Latch: Level Sensitive
library ieee;
use ieee.std_logic_1164.all;
entity latch is
D Q
port(
d, clk : in std_logic; Clock
q : out std_logic);
end latch;

architecture behavior of latch is

begin
process (d, clk )
begin
if clk = '1' then
q <= d;
end if;
--No else branch
-- implied memory implementation
-- use the last assigned value
end process;
end behavior; 60
 D Flip-Flop: Edge Triggered
Truth table
D Q
 We consider three types of D FFs:
Clock  D FF with synchronous reset
 D FF with asynchronous reset
Graphical symbol  D FF with synchronous enable

Time diagram 61
 Processes Modeling for Sequential Circuits
 Clocked Process - general format
architecture behav Of flip-flop is
begin
Process (clock signal, [asynchronous signals])
begin
if asynchronous_conditions then
--Sequential statements for reset or preset
elsif clock_edge then
-- sequential statements for clock_edge
end if;
end process;
end behav;

• Sensitivity list must always include clock and asynchronous signals

• All signal assignments in process result in flip-flops
62
D Flip-Flop: Edge Triggered

63
 D flip-flop with asynchronous reset
 A D FF may contain an asynchronous reset signal.
 Asynchronous reset, as its name implies, is not synchronized by the clock signal and thus
should not be used in normal synchronous operation.
 The major use of a reset signal is to clear the memory elements and set the system to an
initial state.
 The signal clears the D-FF to ’0’ any time and is not controlled by the clock signal.
 It actually has a higher priority than the regularly sampled input.
 Using an asynchronous reset signal violates the synchronous design methodology and thus
should be avoided in normal operation.
 Its major application is to perform system initialization.
 Some D-FFs may also have an asynchronous preset signal that sets the D FF to ’1’

64
D flip-flop with asynchronous reset

65
D flip-flop with asynchronous reset

66
 D flip-flop with Sync Enable
 A D-FF may include an additional control signal, en, to enable the FF to sample the input
value.
 Note that the en signal is examined only at the rising edge of the clock and thus is
synchronous.
 If it is not asserted, the FF keeps its previous value.
 The enabling feature of this D-FF is useful in maintaining synchronism between a fast
subsystem and a slow subsystem.

67
D flip-flop with Sync Enable…

68
 Coding Practice
 First identify and separate the memory elements and then derive the next state logic and output
logic.
 A clear separation between memory elements and combinational circuits is essential for the
synthesis of large, complex design and is helpful for the verification and testing processes.
 Our VHDL code description follows this principle and we always use an isolated VHDL
segment to describe the memory elements
 Use an individual VHDL code segment to infer memory elements. The segment should be the
standard description of a D FF or register.
 Use the suffix _reg to represent the output of a D-FF or a register.
 Use the suffix _next to indicate the next value (the d input) of a D-FF or a register.

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 Register
 A register is a collection of D FFs that are controlled by the same clock and reset signals.
 Like a D FF, a register can have an optional asynchronous reset signal and a synchronous
enable signal.
 The code is identical to that of a D FF except that the array data type, std_logic_vector,
is needed for the relevant input and output signals.

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Generic N-bit Register

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 Shift Registers
 Free-Running Shift Register (no control signals)

Serial in Serial Out

Serial in Serial Out

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Shift Registers

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Shift Registers

Serial in Serial Out

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Shift Registers

Serial in Parallel Out

75
Shift Register With Parallel Load

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Shift Register With Parallel Load

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 Universal Shift Register
 Universal Shift Register
 Designed to implement 4 ops: parallel load, shift right, shift left, pause

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79
 Register file
 A register file is a collection of registers with one input port and one or more output ports.

Conceptual diagram of a 4-by-8 (four words and 8 bits per word) register file
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 Register file
The write address signal, w_addr, specifies where to store data
The read address signal, r_addr, specifies where to retrieve data.
The register file is generally used as fast, temporary storage.
As showed in conceptual diagram of a register file, the design consists of
 Four registers with enable signals
 A write decoding circuit
 Read multiplexing circuits.
 The write decoding circuit examines the wr_en signal and decodes the write port address.
 If the wr_en signal is asserted, the decoding circuit functions as a regular 2-to- 22 decoder
 The w_data signal will be sampled and stored into the corresponding register at the rising edge
of the clock.
 The read multiplexing circuit consists of a 4-to-l multiplexer.
 It utilizes r_addr as the selection signal to route the desired register output to the read port.
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82
Register file…

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 Counter Modeling with VHDL
 Counters are simple examples of sequential circuits
 Counters can be modeled as arbitrary FSMs, but this is not the most straightforward method o
modeling these circuits
 Counters can be easily modeled using basic arithmetic expressions
 Options include:
 Arithmetic operations on UNSIGNED and SIGNED signals
 Use of the INTEGER data type

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 Free-Running Binary Counter
 Free-running binary counter: An n-bit binary counter has a register with n FFs, and its output is
interpreted as an unsigned integer.
 This counter increments the content of the register every clock cycle, counting from 0 to
2n -1and then repeating.
 In addition to the register output, we assume that there is a status signal, max_pulse ,which
is asserted when the counter is in the all-one state.
 The next-state logic consists of an incrementor, which calculates the new value for the next
state of the register.

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RTL schematic of free running binary counter
Counter Modeling with VHDL: 4-bit up counter

86
Counter Modeling with VHDL: 4-bit up counter

87
Up-Down Counter

88
Up-Down Counter

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 Mod-m Counter
 Instead of utilizing all possible 2n states of an n-bit binary counter, we sometime only want the
counter to circulate through a subset of the states.
 We define a mod-m counter as a binary counter whose states circulate from 0 to m-1 and then
repeat.
 A mod-m counter counts from 0 to m-1 and wraps around.

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Mod-m Counter…

91
 Differences: Signals vs Variables
 Variables can only be declared and used within processes or procedures.
 Used to hold temporary results.
 Signals can only be declared in architecture.
 Used for inter-process communications.
 Variables are updated immediately.
 Signals are updated after current execution of a process is finished.
 Assignment Statement:
 Syntax of signal assignment:
SIG_NAME <= <expression>;
 Syntax of variable assignment:
VAR_NAME := <expression>;
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 Differences: Signals vs Variables

process (a, b, c, s) process (a, b, c, s)

begin begin
s <= a and b; o <= s xor c;
o <= s xor c; s <= a and b;
end process; end process;

process (a, b, c)
variable s : std_logic;
process (a, b, c) begin
variable s : std_logic; o <= s xor c;
begin s := a and b;
s := a and b; end process;
o <= s xor c;
end process;
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Differences: Signals vs Variables

94
Differences: Signals vs Variables

95
 Differences: Signals vs Variables

X1 S1
C1

X2 S2
C2

96
 Differences: Signals vs Variables

X1 V
C1

X2 S
C2

97