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Question Bank -2023

Paper Name : Computer Architecture Discipline : CSE
Paper Code : PCC-CS402 Semester : 4th
[PART-A]
Multiple Choice Questions (each question carries 1 mark)

1. The performance of a pipelined processor suffers if

(a) the pipeline stages have different delays
(b) consecutive instructions are dependent on each other
(c) the pipeline stages share hardware resources
(d) all of these.

2. What will be the speed up for a 4-segment linear pipeline when the number of instruction n=64?
(a) 4.5 (b) 3.82 (c) 8.16 (d) 2.95

3. In which type of memory mapping there will be conflict miss?

(a) Direct mapping (b) Set associative mapping
(c) Associative mapping (d) Both (a) & (b).

4. Example of a recirculating network is

(a) 3 cube networks (b) Ring network
(c) Tree network (d) Mess connected iliac network.

5. Array process is present in

(a) MIMD (b) MISD (c) SISD (d) SIMD

6. Which type of data hazard is not possible?

(a) WAR (b) RAW (c) RAR (d) WAW

7. In general, 64 input Omega network requires ____________ stages of switches?

(a) 6 (b) 64 (c) 8 (d) 7

8. Virtual address space can be divided into some fixed size

(a) segment (b) block (c) pages (d) none of these.

9. MIPS means
(a) Multiple Instructions per Second (b) Millions of Instruction per Second
(c) Multi-Instruction Performed System (d) None of these.

10. Which is not the property of a memory module?

(a) Inclusion (b) Consistency (c) Capability (d) Locality.

11. A pipeline stages

(a) is sequential circuit (b) is combinational circuit
(c) Consists of both sequential and combinational circuits (d) none of these.

12. Utilization pattern of successive stages of a synchronous pipeline can be specified by

(a) Truth table (b) Excitation table (c) Reservation table (d) Periodic table.

13. SPARC stands for

(a) Scalable Processor Architecture (b) Superscalar Processor A RISC Computer
(c) Scalable Processor A RISC Computer (d) Scalable Pipeline Architecture.

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14. Which of the following is not RISC architecture characteristic?
(a) Simplified and unified format of code of instructions
(b) No specialized register
(c) No storage/storage instruction
(d) Small register file.

15. The time to access shared memory is same in which of the following shared memory multiprocessor
models?
(a) NUMA (b) UMA (c) COMA (d) ccNUMA.

16. Which of the following architectures corresponds to von-Neumann architecture?

(a) MISD (b) MIMD (c) SISD (d) SIMD.

17. In absence of TLB, to access a physical memory location in a paged-memory system how many
memory accesses are required?
(a) 1 (b) 2 (c) 3 (d) 4

18. A direct mapped cache memory with n blocks is nothing but which of the following set associative
cache memory organizations?
(a) 0-way set associative (b) 1-way set associative
(c) 2-way set associative (d) n-way set associative

19. Portability is definitely an issue for which of the following architectures?

(a) VLIW processor (b) Super Scalar processor
(c) Super pipelined (d) None of these.

20. Which of the following is not the cause of possible data hazard?
(a) RAR (b) RAW (c) WAR (d) WAW.

21. Assume a system where main memory is of size 16 K X 12 and cache memory is of size IK X 12. For a
direct mapping system which statement is correct?
(a) Tag field is 9 bits and index field are 6 bits
(b) Tag field is 4 bits and index field are 10 bits
(c) Tag field is 7 bits and index field are 8 bits
(d) None of these.

22. The advantage of RISC over CISC is that

(a) RISC can achieve pipeline segments, requiring just one clock cycle
(b) CISC uses many segments in its pipeline with the longest segment requiring two or more clock cycle
(c) Both (a) & (b)
(d) None of these.

23. The expression for Amdahl’s law is

(a) S(n) =1/f where n → ∞ (b) S(n) = f where n → ∞
(c) S(n) =1/T where n → ∞ (d) None of these.

24. The vector stride value is required to

(a) deal with the length of vectors
(b) find the parallelism in vectors
(c) access the elements in multi-dimensional vectors
(d) execute vector instruction.

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25. Which MIMD systems are best according to scalability with respect to the number of processors?
(a) Distributed memory computers (b) ccNUMA systems
(c) nccNUMA systems (d) Symmetric multiprocessors.

26. In general, an n input Omega network requires ______ stages of 2x2 switches.
(a) 2 (b) 4 (c) 8 (d) 16.

27. Dynamic pipeline allows

(a) Multiples function to evaluate (b) Only streamline connection
(c) To perform fixed function (d) None of these.

28. The performance of a pipeline processor suffers if

(a) the pipeline stages suffer different delay
(b) consecutive instructions are dependent on each other
(c) the pipelining stages share same resources
(d) all of these.

29. Superscalar processors have CPI of

(a)Less than 1 (b)Greater than 1 (c)More than 2 (d)Greater than 3.

30. The main memory of a computer has 2 cm blocks while the cache has 2 c blocks. If the cache uses the
set associative mapping scheme with 2 blocks per set; then block k of the main memory maps to the set
(a) (k mod m) of the cache (b) (k mod c of the cache
(c) (k mod 2c of the cache (d) (k mod 2 cm) of the cache.

31. Overlapped register windows are used to speed up procedure call and return in
(a) RISC architecture (b) CISC architecture
(c) Both (a) and (b) (d) None of these.

32. Which of the following is example of 2-dimensional topologies in static network?

(a) Mesh (b) 3C3 Network (c) Linear Array (d) None of these.

33. Advantage of MMX technology lies in

(a) Multimedia application (b) VGA
(c) CGA (d) none of these.

34. Basic difference between Vector and Array processors is

(a) pipelining (b) interconnection network
(c) register (d) none of these.

35. Stride in Vector processor is used to

(a) differentiate different data types (b) registers
(c) differentiate different data (d) none of these.

36. Which one of the following has no practical usage?

(a) SISD (b) SIMD (c) MISD (d) MIMD.

37. Difference between RISC and CISC is

(a) RISC is more complex
(b) CISC is more effective
(c) RISC is better optimizable
(d) none of these.
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38. For 2 Instructions I and J, WAR hazard occurs if
(a) R(I) ∩ D(J) ≠ φ (b) R(I) ∩ R(J) ≠ φ
(c) D(I) ∩ R(J) ≠ φ (d) none of these.

39. The seek time of a disk is 50ms. It rotates at the rate of 30 rotations/ second. The capacity of each track
is 300 words. The access time is approximately
(a) 62 ns (b) 60 ns (c) 47 ns (d) none of these.

40. Non-linear pipeline contains

(a) Only streamline connections (b) Only feed-forward connections
(c) Only feedback connections (d) all of them

41. Consider the cache memory with access time 40 ns has the hit ratio of 80%. The regular memory has an
access time of 100 ns. What is the effective access time for CPU to access memory?
(a) 52 ns (b) 60 ns (c) 70 ns (d) 80 ns.

42. What is a main advantage of classical vector systems (VS) compared to RISC based systems (RS)?
(a) VS have significantly higher memory bandwidth than RS
(b) VS have higher clock rate than RS
(c) VS are more parallel than RS
(d) None of these.

43. Associative memory is a

(a) pointer addressable memory (b) very cheap memory
(c) content addressable memory (d) slow memory.

44. The principle of locality justifies the use of

(a) Interrupts (b) polling (c) DMA (d) cache memory.

45. How many address bits are required for a 512 x 4 memory?
(a) 512 (b) 4 (c) 9 (d)

46. The division of stages of a pipeline into sub-stages is the basis for -
(a) pipelining (b) super-pipelining (c) superscalar (d) VLIW processor

47. The seek time of a disk is 30ms. It rotates at the rate of 30 rotations/second. The capacity of each track
is 300 words. The access time is approximately
(a) 62ms (b) 60ms (c) 47ms (d) none of these

48. Full form of ICV

(a) Internal Collision Value (b) Initial Collision Vector
(c) Instruction Collision Vector (d) none of these

49. A single bus structure is primarily found in

(a) Main frames (b) High performance machines
(c) Mini and Micro- computers (d) Supercomputers.

50. The number of cycles required to complete n tasks in a k stage pipeline is

(a) k+ n- 1 (b) nk + 1 (c) k (d) none of these

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51. A computer with cache access time of 100ns, a main memory access time of 1000 ns, and a hit ratio of
0.9 produces an average access time of
(a) 250 ns (b) 200 ns (c) 190 ns (d) none of these.

52. Which of the following types of instructions are useful in handling sparse vectors or sparse matrices
often encountered in practical vector processing applications?
(a)Vector-Scalar instruction (b)Masking instruction
(c)Vector-memory instructions (d)None of these.

53. A 4-ary 3-cube hypercube architecture has

(a) 3 dimensions with 4 nodes along each dimension
(b) 4 dimensions with 3 nodes along each dimension
(c) both (a) and (b)
(d) none of these.

54. Which of these are examples of 2-dimensional topologies in static networks?

(a) Mesh (b) 3 CCC networks
(c) Linear array (d) none of these.

55. Assuming a Main memory of size 32 K x 12, Cache memory of size 512 x 12 and block size of 1 word,
the addressing relationships using direct mapping would be
(a) tag field-6 bits, index field-9 bits (b) tag field-9 bits, index field-6 bits
(c) tag field-7 bits, index field-8 bits (d) none of these.

56. Overlapped register windows are used to speed-up procedure call and return in
(a) RISC architectures (b) CISC architectures
(c) both (a) and (b) (d) none of these.
57. For 2 Instructions I and J, RAW hazard occurs if
(a) R(I) ∩ D(J) ≠ φ (b) R(I) ∩ R(J) ≠ φ
(c) D(I) ∩ R(J) ≠ φ (d) none of these.

58. The prefetching is a solution for

(a) Data hazard (b) Structural hazard
(c) Control hazard (d) none of these.

59. Performance (P) and execution time (T) of CPU are related by
(a) P ∞ T (b) P ∞ 1/T (c) P = T (d) none of these.

60. Loop scheduling includes

(a) loop unrolling (b) software pipelining
(c) Both (a) & (b) (d) none of these.

61. Pipeline computers perform computations to exploit

(a) temporal parallelism (b) spatial parallelism
(c) sequential behaviour of program (d) modularity of program.

62. The number of machine instructions to be executed in the program is called

(a) cycle (b) time period (c) instruction counts (d) none of these.

63. Array processor are put under which of these categories?

(a) SISD (b) SIMD (c) MISD (d) MIMD
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64. Full form of MAL
(a) Minimum Average Latency (b) Maximum Average Latency
(c) Multiple Average Latency (d) none of these

65. A program segment chosen for parallel processing is known as

(a) grain (b) cluster (c) work station (d) none of these.

66. An n- dimensional hypercube has

(a) nodes (b) n nodes (c) 2n nodes (d) none of these.

67. The vector stride value is required

(a) to deal with the length of vectors
(b) to find the parallelism in vectors
(c) to access the elements in multi-dimensional vectors
(d) none of these.

68. Forbidden latency means:

(a) distance between any two checkmarks in the same column of the reservation table
(b) distance between any two checkmarks in the same row of the reservation table
(c) distance between all the checkmarks
(d) none of these

69. Effective access time ( ) of memory is given by

(a) (b)

(c) (d) none of these.

70. Scatter operation is reverse of

(a) gather (b) masking (c) chaining (d) none of these.

71. For 2 Instructions I and J, WAW hazard occurs if

(a) R(I) ∩ D(J) ≠ φ (b) R(I) ∩ R(J) ≠ φ
(c) D(I) ∩ R(J) ≠ φ (d) D(I) ∩ D(J) ≠ φ.

72. Consider a 4-segment pipeline with stage delays (2 ns, 8 ns, 3 ns, 10 ns). Find the time taken to execute
100 tasks in the above pipeline
(a) 910 ns (b) 1000 ns (c) 1030 ns (d) 1140 ns

[PART-B]
Module 1 (Introduction)
1. Describe the function of Major Components of a digital computer with neat sketch
2. What are the different parameters used in measuring CPU performance? Briefly discuss each.

Module 2 (Pipelining)
1. Identify the hazards in the following instruction stream.
l1 : r2← r2+r3
l2 : if r2=0 then goto L3
l3 : M[500] ←R2
l4 : L3: M[600] ←M[500] +r5

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2. Identify the hazards in the following instruction stream.
l1 : R2← r5/r8
l2 : r9←r2/r7
l3 : r5←r10<<r6
l4 : r11←r9*r5
l5 : r10←r12
l6 : r8←r15 OR r2

3. What is meant by pipeline stall?

4. What are the different hazards in pipeline?

5. Show that maximum speed-up of a pipeline is equal to number of stages.

6. What is the difference between static pipeline and dynamic pipeline? Write how data dependency
hazard is solved.

7. a) Explain how the throughput in a pipelined processor increases compared to a non-pipelined

processor.
b) Prove that a k-stage linear pipeline can be at most k-times faster than that of a non-pipelined scalar
processor.

8. What do you mean by hazard in pipeline? Describe different type of hazard. How data-dependency is
detected. What is effect of branch instruction in pipelining? Find out effective throughput due to branch
instruction. Write how branch hazard is handled.

9. Consider five stage pipelined processor specified by following reservation table:

1 2 3 4

S1 X X

S2 X

S3 X

S4 X X

(a) List the set of forbidden latencies and collision vector.

(b) Draw the state transition diagram
(c) List all simple cycles from state diagram
(d) Identify the simple cycles among greedy cycles.
(e) Find out minimum average latency
(f) Find out maximum throughput of this pipeline.

10. Distinguish static pipeline from a dynamic pipeline. Define speed-up. Deduce that the maximum speed-
up in a k-stage pipeline processor is k. Is this maximum speed-up always achievable? Explain.

11. Suppose the time delays of the 4 stages of a pipeline are t1=60ns, t2=50ns, t3=90 ns and t4=80ns
respectively and the interface latch has a delay t1=10 ns, then
i)What would be the maximum clock frequency of the above pipeline?
ii) What is the maximum speed-up of this pipeline over that of its non-pipeline counterpart?

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12. a. Show that when K jobs are processed over an N-stage pipeline, the speed-up obtained is
b. Define speed-up of a parallel processing system.
c. Explain structural hazards in a pipeline processing.
d. With the help of a neat diagram, show the structure of a typical arithmetic pipeline performing
subtraction.

13. What are instruction and arithmetic pipeline? Give examples.

Module 3 (Memory Organization)

1. “The program counter is called memory pointer”- justify your answer

2. What is “miss penalty”?

3. What is dirty bit?

4. Explain the memory hierarchy pyramid, showing both primary and secondary memory in the diagram
and explain the relationship of cost, speed and capacity.

5. Compare and contrast:

(a) Static RAM versus Dynamic RAM
(b) Memory Interleaving versus Memory having multi-port

6. What is Cache? What is set associative mapping in cache memory?

7. What is cache mapping? Explain direct mapping for 256 x 8 RAM and 64 x 8 cache.

8. Draw the block diagram for an associative memory cell and explain it.

9. Suppose a computer using direct mapped cache has 220 words of main memory and a cache of 32
blocks, where each cache block contains 16 words.
(a) How many blocks of main memory are there?
(b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag,
block, and word fields?
(c) To which cache block will the memory reference 0DB6316 map?

10. Explain the concept of locality of reference and state its importance to memory systems.
11. What do you mean by m-way interleaving? In the system with pipeline processing, is the memory
interleaving useful? If yes, explain why.

12. Draw the block diagram of C-access memory function. Why is it necessary and how does it improve the
memory access time?

13. How do you speed up memory access in case of vector processing? With architecture and timing
diagram explain S-access memory organization

14. a. What is cache mapping? Explain cache mapping for 256 x 8 RAM and 64 x 8 cache.
b. Explain how a RAM of capacity 2 Kbytes can be mapped into the address space (1000)H to (17FF)H
of a CPU having a 16 bit address lines. Show how the address lines are decoded to generate the chip-
select condition for the RAM.

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15. a. Explain the reading and writing operations of a basic Static MOS cell.
b. Why a DRAM cell needs refreshing?
c. Given the following, determine size of the sub-fields (in bits) in the address for the Direct Mapping,
associative and set associative mapping cache schemes:
 We have 256 MB main memory and 1 MB cache memory.
 The address space of this processor is 256 MB.
 The block size is 128 bytes
 There are 8 blocks in a cache set.

16. a. With example explain spatial and temporal locality.

b. What is an associative memory? With a suitable diagram explain the search operation in associative
memory.
c. Briefly explain the two write policies write through and write back for cache design. What are the
advantages and disadvantages of both the methods?

17. a. What is cache memory? How does it increase the performance of a computer? What is hit ratio?
b. A three-level memory system having cache access time of 5 nsec and memory access time of 40 nsec,
has a cache hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the disk access time to
achieve an overall access time of 16 nsec?
c. A hierarchical three-level memory system having cache access time of 10 nsec and memory access
time of 150 nsec, has a cache hit ratio of 0.97 and main memory hit ratio of 0.9. What should be the disk
access time to achieve an overall access time of 20 nsec?

18. a. What is Cache memory? Why is it needed? Explain the Write-through and Write –back mechanism.
b. Why is set-associative mapping technique more advantageous than direct or associative mapping
technique?
c. A computer has 512 KB cache memory and 2 MB main memory. If the block size is 64 bytes, then
find out the subfields for
i. direct mapping cache
ii. associative
iii. 8-way set associative cache
d. Why memory hierarchy is needed? What are the different levels in memory hierarchy?
19. a) What is cache memory? Explain different cache memory mapping techniques.
b) What is TLB? What is virtual memory? How virtual memory is implemented?

20. a) What are the differences between centralized shared memory architecture and distributed shared
memory architecture?
b) Write difference between direct mapped and set-associative caches with example

21. What is virtual memory? How virtual memory is implemented?

Module 4 (Instruction Level Parallelism)

1. Compare CISC and RISC.
2. What is RISC architecture? Write short note on PowerPC.
3. a. What are some typical distinguishing characteristics of RISC organization?
b. A large register file in RISC design is substitute of cache memory in CISC design-Justify.
c. Explain the concept of register window for procedure calls in RISC design.
4. a) compare and contrast CISC and RISC processor architecture. Give example for each.
b) What are the different addressing modes for RISC architecture? How effective address is calculated
in those modes?
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Module 5 (Multiprocessor Architecture)
1. Discuss about vector stride in vector processor.

2. Draw 42x32 delta network.

3. Write Flynn’s classification of computer?

4. Design a parallel algorithm to perform matrix multiplication using 2D pipeline processor (systolic array
processor). What will be the time complexity if the size of each matrix is NxN.

5. What are the differences between shared memory multiprocessor system and message passing
multicomputer system? Draw 16x16 butterfly networks.

6. What do you mean by vector processor? What are the differences between memory-to-memory
architecture and register-to-register architecture? Describe different types of vector instructions. Give
the block diagram to indicate the architecture of a typical vector processor with multiple function pipes.

7. What is vector processor? How does it differ from SIMD machine? What are the different types of
vector operations? Give different fields in a vector instruction. Write the differences between scalar
processor and vector processor.

8. What are the differences static network and dynamic network? What do you mean by bisection width of
a network? Draw 8x8 Omega network and show how connection is established between a source node
and destination node.

9. What do you mean by multi-stage interconnection network? Draw 16×16 omega network and show the
path between source node2 and destination node 13.

10. Compare superscalar processor and VLIW processor.

Module 5 (Non Von Neumann Architecture)

1. What are the bottlenecks of Von Neumann concept?

2. Implement the data routing logic of SIMD architecture to compute

3. a) What do you mean by “data flow computer”?

b) What are the differences between data flow computer and control flow computer?
c) Draw data flow graph to represent the following computation

[PART - C]
Module I (Introduction & Pipelining)

1. Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI),
Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The
stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are
intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting
of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor. Instruction I4 is the only
branch instruction and its branch target is I9. If the branch is taken during the execution of this program,
what is the time (in ns) needed to complete the program? [4]

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2. Why register renaming is necessary in pipelined processors? [2]

3. How static scheduling approach of instruction pipeline can improve performance system? You may give
an example. Can you increase performance of the system by introducing dynamic scheduling? Explain
your answer. [2+3]

4. Consider a pipelined processor with the following four stages:

IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock
cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle
and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the
pipelined processor.
What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0
MUL R4, R3, R2
SUB R6, R5, R4 [4]

5. A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first
stage of the pipeline. A conditional branch instruction computes the target address and evaluates the
condition in the third stage of the pipeline. The processor stops fetching new instructions following a
conditional branch until the branch outcome is known. A program executes 109 instructions out of
which 20% are conditional branches. If each instruction takes one cycle to complete on average, what is
the total execution time of the program? [3]
6. A5 stage pipelined CPU has the following sequence of stages:
IF - Instruction fetch from instruction memory.
RD - Instruction decode and register read.
EX - Execute: ALU operation for data and address computation.
MA - Data memory access - for write access, the register read at RD state is used.
WB - Register write back.
Consider the following sequence of instructions:
I1 : LOAD R0, loc 1; // R0 ← M[ loc l ]
I2 : ADD R0, R0; // R0 ← R0 + R0
I3 : SUB R2, R2 R0; // R2 ← R2 - R0
Let each stage take one clock cycle.
What is the number of cock cycles taken to complete the above sequence of instructions starting from
the fetch of I1? [3]

7. A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers
that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate
evaluate the total time taken to process 1000 data items on this pipeline. [3]

8. For a pipelined CPU with a single ALU, consider the following situations
i) The j + 1-st instruction uses the result of the j-th instruction as an operand
ii) The execution of a conditional jump instruction
iii) The j-th and j + 1-st instructions require the ALU at the same time
Which of the above can cause a hazard and why? [3]

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9. Consider a 5-stage pipeline – IF (Instruction Fetch), ID (Instruction Decode and register read), EX
(Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the
second phase of a clock cycle and writes occur in the first phase of the clock cycle. Consider the
execution of the following instruction sequence:
11: sub r2, r3, r4;
12: sub r4, r2, r3; /* r4 ← r2 – r3 */
13: sw r2, 100(r1) /* M[r1+100] ← r2 */
14: sub r3, r4, r2; /* r3 ← r4 – r2 */
(a) Show all data dependencies between the four instructions.
(b) Identify the data hazards.
(c) Can all hazards be avoided by forwarding in this case? [3+2+1]

10. Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-
pipelined but identical CPU, we can say that (Give explanation)
(a) T1 = T2
(b) T1 > T2
(c) T1 < T2
(d) T1 is T2 plus the time taken for one instruction fetch cycle [3]

11. An instruction pipeline consists of 4 stages – Fetch (F), Decode field (D). Execute (E) and Result Write
(W). The 5 instructions in a certain instruction sequence need these stages for the different number of
clock cycles as shown by the table below.
Instruction F D E W
1 1 2 1 1
2 1 2 2 1
3 2 1 3 2
4 1 3 2 1
5 1 2 1 2

Find the number of clock cycles needed to perform the 5 instructions. [3]

12. A 40 MHz processor was supposed to execute 200000 instructions with following instruction mix and
CPI needed for each instruction
Instruction type CPI Instruction count
Integer arithmetic 2 60%

Data transfer 4 18%

Floating point 6 12%

Control transfer 5 10%

Determine the effective CPI, MIPS rate and execution time. [3]

13. What is branch target buffer (BTB) ? Why is it used in pipelining? [4]

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14. Consider five stage pipelined processor specified by following reservation table:

1 2 3 4 5 6
S1 X X
S2 X X
S3 X
S4 X
S5 X X

a) List the set of forbidden latencies and collision vector.

b) Draw the state transition diagram
c) List all simple cycles from state diagram
d) Identify greedy cycles among simple cycles.
e) Find out minimum average latency
f) Find out maximum throughput of this pipeline. [2+2+2+2+1+1]

Module II (Memory Organization)

1. Consider the virtual page reference
string 1, 2, 3, 2, 4, 1, 3, 2, 4, 1
on a demand paged virtual memory system running on a computer system that has main memory size of
3-page frames which are initially empty. Let LRU, FIFO and OPTIMAL denote the number of page faults
under the corresponding page replacement policy. Then (Give explanation)
(A) OPTIMAL < LRU < FIFO
(B) OPTIMAL < FIFO < LRU
(C) OPTIMAL = LRU
(D) OPTIMAL = FIFO [6]

2. Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory
consists of 256 blocks and the request for memory blocks is in the following order:
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.
Which memory block among 3, 8, 129 and 216 will NOT be in cache if LRU replacement policy is
Used? [3]

3. A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-
aside buffer (TLB) which can hold a total of 128-page table entries and is 4-way set associative. The
minimum size of the TLB tag is: (Give explanation)
(A) 11 bits (B) 13 bits (C) 15 bits (D) 20 bits [3]

4. Why is C-access memory organization necessary and how does it improve the memory access time?
[3]
5. In the system with pipeline processing, is the memory interleaving useful? If yes, explain.
[2]
6. What is memory bandwidth? Can interleaved memory increase memory bandwidth? If yes, how?
[1+3]
7. What is the 90-10 rule and its relationship to the locality of references? [1+2]

Prepared By

Prof. Subhankar Roy and Prof. Suman Goswami

Question Bank for PCC-CS402 Page | 13