INTERNATIONAL JOURNAL of RENEWABLE ENERGY RESEARCH

C. Koseoglu et al., Vol.10, No.1, March, 2020

A Hybrid Overload Current Limiting and Short

Circuit Protection Scheme for Voltage Mode
Inverters

Cem Koseoglu*, Necmi Altin **, Fevzi Zengin*, Hasan Kelebek*, and Ibrahim Sefa**

* Inform Elektronik Sanayi ve Ticaret A.S., 34785, Istanbul, Turkey

** Electrical Electronics Engineering Department, Faculty of Technology, Gazi University, 06500, Ankara, Turkey
([email protected], [email protected], [email protected], [email protected], [email protected])

‡
Cem Koseoglu, 34785, İstanbul, Turkey, Tel: +90 (262) 751 16 00 /8311, [email protected]

Received: 30.11.2019 Accepted:21.01.2020

Abstract- In this study, a current limiting technique which combines an analog comparator circuit and a digital current limiting
algorithm is proposed for voltage mode – controlled inverters. Thus, providing smooth output voltage waveform feature of
digital current limiting technique and very fast response feature of the analog technique are combined. A three-phase 10kVA
voltage mode – controlled inverter has been used to test the performance of the proposed method. Besides, the digital and the
analog current limiting techniques have been tested separately to highlight and compare the performance of the proposed
hybrid method. It is seen from experimental tests that the proposed technique provides fast response and a successful current
limiting performance at short circuit and overcurrent conditions. In addition, the proposed method improves the reliability and
fault tolerance capability of the inverter significantly. Moreover, the proposed current limiting algorithm adds fault clearing
capability function to the inverter.
Keywords Overcurrent protection; overload; short circuit protection; current limiter; fault-tolerant inverter; voltage source
inverter (VSI).
Nomenclature
VSI Voltage Source Inverter Inverter Output Reference Voltage
UPS Uninterruptible Power Supply Digital Current Limiter Input Signal
Measured DC Bus Voltage Digital Current Limiter Output Signal
Measured Inverter Output Voltage Positive Alternance Analog Current Limit Peak Value
Measured Inverter Output Current Negative Alternance Analog Current Limit Peak
Digital Current Limiter Parameter Value
Analog Current Limiter Measured Current
Digital Current Limit Value

1. Introduction
are the major reason of power circuitry damages. It is
The voltage source inverters (VSIs) which are
reported that about 38% of the faults in a power circuitry of
employing several semiconductor power switches, such as the VSI is due to failures of switching devices [2]. Therefore,
IGBTs and MOSFETs are commonly used in industrial designing a proper protection and fault detection system for
applications including the Uninterruptible Power Supplies
these inverter circuits is very important requirement to obtain
(UPSs), Distributed Generation (DG) systems, and motor
a high-reliability inverter especially for high power systems
drives [2 – 8]. Among the other causes, power switch faults
[2].
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C. Koseoglu et al., Vol.10, No.1, March, 2020

UPS applications and stand-alone renewable energy

systems are most common voltage mode – controlled
inverter applications. Since the UPS’s are used to provide
uninterruptible power to the critical loads, the reliability of
the inverter is very important. Therefore, the protection and
fault detection systems employed are one of the major
subsystems. Same conditions are also valid for stand-alone
inverters supplied by the renewable source and battery back-
up. Since the IGBT chip has a finite current capacity, the
overcurrent as a result of overload or short circuit operation
causes the overheat of the chip. This overheat is the typical
reason of the destruction of semiconductor power switches
employed in power inverters [3]. Fig. 1. A general diagram of an DC–AC converter.
The short circuit is one of the most critical conditions to The voltage–controlled inverters are commonly used at UPSs
be considered. It may cause serious problems [2, 9]. and stand–alone renewable energy applications such as
Different short-circuit protection schemes have been photovoltaic systems and fuel cell applications. Since the
designed and implemented. Using the collector-emitter UPSs are installed to supply the critical loads where the
saturation voltage of the IGBT to detect the short circuit energy continuity is very important, instead of turning the
condition is one of these schemes [10]. However, a settling semiconductor devices off, limiting their fault (short-circuit
time is required to measure this voltage, and this increases or overcurrent) current is the main purpose of this study. A
the response time. Typically, it takes about 10 µs to turn off hybrid model, combining both analog and digital schemes is
the IGBT with this method. This delay causes severe presented in this paper. Experimental studies have been
temperature to raise (about 70°C) in the junction temperature carried out to test the proposed system for short circuit and
of 1200V rated IGBTs during the short circuit. As a result, over current conditions along with the temporary overcurrent
the high thermal and electrical stresses destroy the switch [2]. states such as turning on a nonlinear or inrush current drawn
load. Analog and digital current limiting techniques are also
Measuring the device current is another protection tested and obtained results are compared with proposed
method which is used to protect the inverters against the method. The experimental results show that the proposed
overcurrent and short circuit conditions. In this method, the hybrid method provides better performance even with the
device current is measured. When it reaches the maximum low filter inductance value and prevents the destruction of
allowable current value of the device, the protection IGBTs.
algorithm is enabled, and the device is turned off [11].
However, turning off the device before it is desaturated may 2. Current Limitation Techniques
also destroy the device, because the operation point of the
device shall be out of its safe operation area (SOA) [2]. Proposed hybrid current limiting technique consist of
Monitoring di/dt of the device current is another method to two parts: A digital current limiting algorithm which can be
protect the device against the short circuit [12]. However, implemented with a DSP, FPGA or another digital system,
this method suffers from misdetection of short circuit and an analog current limiting circuit. Each technique will be
conditions. discussed separately, and then the proposed hybrid technique
Another method employing a protection inductor has combining these two techniques will be explained.
been also proposed to protect the device against the short
circuit [13]. Although this method provides fast response, 1.1. Digital Current Limiting Algorithm
additional inductor and thyristor increase the cost and size of
the system. In Fig. 1, a general structure of a DC – AC converter is
given. The digital current limiting algorithm limits the
The triple-loop-control algorithm is proposed to limit the inductor or output current digitally. The algorithm can be
overload and short circuit current and provide protection applied to different converter topologies including two–level
against these conditions. Along with the voltage and current or three–level inverters. Since the algorithm is based on
loops, a most inner current hysteretic controller is employed. limitation of the control signal, it is independent of the
When the inverter works in normal operation conditions, the inverter topology.
third loop does not have any effect on the system. However,
when a short circuit is detected and the traditional current In Fig. 2 a general control block diagram of an inverter is
controller cannot handle it, the current hysteretic controller shown. The current limiting algorithm is placed between
limits the current by disabling the PWM pulse. If the preset controller and PWM modulator. Different algorithms may be
values are reached, the inverter is shut off immediately [9]. used for the inverter control, and it does not have any effect
However, as discussed above, immediate turn off the on current limiting algorithm. Current limiter block limits the
devices, working out of the SOA, may also destroy the control signal and acts as a variable limiter for the control
switching devices. signal of the controller. By this way the duty cycle is also
limited. Limitation of the control signal is current dependent.
This paper has been focused on the overload and short
circuit protection of the voltage mode – controlled inverters.

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the constant voltage mode. During overcurrent states, the

inverter control signal is limited by the current limiting
algorithm leading the transition of the inverter operation to
the constant current mode.
Fig. 2. Inverter control block diagram.
1.2. Analog Current Limiting Technique

For fast changing currents such as a short circuit current,

the sample-based digital limitation may not be fast enough.
Since a short circuit current has a high current changing rate
(di/dt), the current may reach dangerous values between two
sampling period. For this reason, an analog circuit may be
used to detect these types of fast changing currents. An
Fig. 3. Detailed block diagram of the digital current analog circuit can detect signals at continuous time domain.
limiting algorithm. Despite the delay effect of the low pass filters used in the
current measurement circuits and delays caused by other
The block diagram of the proposed algorithm is given in non–ideal elements, analog circuits are fast enough to catch
Fig 3. Interaction of current limiter and control system can be the fast–changing currents.
seen in Fig. 3 in more detail. The digital current limiting
algorithm is executed at every sampling period together with In an AC system, the rising rate of the IGBT current of
the voltage control loop. In this way at every PWM cycle the inverter at a short-circuit instant depends on the short-
current limiting action is obtained. In Fig. 3, and circuit occurring angle. If short-circuit occurs when the
voltage is small, the short circuit current shall have lower
are real time measured values. and are current
(di/dt). However, if short circuit occurs at the peak of the AC
limiting algorithm parameters. voltage, the current shall have the maximum rise speed
Equation (1) is implemented as block diagram in Fig. 3 (di/dt).
and shows the principle of the algorithm more clearly. A practical short–circuit case analysis:
(1) For a worse–case scenario, a case in which the short
circuit is occurred at the peak value of the inverter output
Equation (1) generates a variable limiting value for the
voltage will be discussed. Since short circuit is a very short
controller output, depending on the output current. As the
duration, inverter voltage at the short circuit instant may be
output current increases, the limit value decreases. Similarly,
assumed as constant. At this instant, the load is short
as the current decreases, the limit value increases. The switch
circuited, and the only current limiting element is the filter
in Fig. 3 decides if the limiting action will be applied or not.
inductor. In this case, the rising speed of the current depends
If measured current exceeds the I_limit the right-hand side of
on the inverter voltage value at the short circuit instant and
the (1) becomes negative, and takes a lower
the inductance value.
value than the measure output voltage. Thus, the control
signal is limited leading a decrease on the output current. If Here, a 10kVA, 220VAC inverter with 10kHz switching
the measured current is below the I_limit, then the Vout_ref_limited frequency will be analyzed.
takes higher value than the measured output voltage. In this • Since short circuit is an instant and assumed to occurred
case there will be no limiting in the control signal as well as at the peak, 311V is used as the voltage value during the
output current. short-circuit and is assumed as constant.
Ki_limit parameter adds a weighting effect to the algorithm • A single sampling period for 10kHz system allows
depending on the current. By using Ki_limit output voltage maximum 100µs uncontrolled current rise.
oscillations can be minimized during transient (overcurrent
or short-circuit) states. Smaller Ki_limit values yields more • Single-phase power of the inverter is 3.3kW. The Root-
stable output voltage and smaller fluctuations. However, this Mean-Square (RMS) value of the inverter output current
slew limitation effect has a negative impact on the dynamic is 15A. The maximum value of the inverter output
response of the voltage controller. Output voltage current is 21A for linear load condition.
oscillations and dynamic response are the tradeoffs that
For these parameters, the rise rate of the current (di/dt)
should be considered while tuning the Ki_limit. In practical
will be investigated. Another important element of the circuit
implementation, it is seen that Ki_limit around 0.1 – 0.8 yields
is the inverter filter inductor. The filter inductor is the only
good response for a unity gain control system.
element in the circuit that has a real effect on the current
In normal conditions, the current limiter block is at limiting action. Stray inductances and other non–ideal
bypassed state. Thus, the limiter has no effect on the inverter parasitic elements in the circuit has no remarkable effect on
regulation. But when an overcurrent occurs, it limits the the rate of the current rise.
control signal depending on the current value. From another
The inductance value of the filter inductor decreases
perspective, at normal current conditions, the inverter is
with the increasing current at short circuit conditions. This
under the control of the inverter regulation and it operates in
decrease in filter inductance leads higher di/dt which limits

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the current limiting capacity and makes fault current limiting this case at the first short circuit instant, digital technique
more difficult. Therefore, the current limiting effect of the may not detect this fast current and destruction of the IGBT
filter inductor which limits di/dt of the device current in short is possible.
circuit conditions should be investigated.

Fig. 6. An implementation of the window comparator

circuit for the analog current limiting.
In this study, a window–comparator circuit is proposed
Fig. 4. A sample test results of an inductor with Kool to overcome the problem. An analog circuit can detect these
Mµ core. types of fast changing currents. In Fig. 6, a window
comparator circuit for the analog current limitation is shown.
The analog comparator circuits are fast enough to detect
short circuit currents. Comparators can detect and respond at
a range between nanoseconds to microsecond. Also, the
speed of the comparison depends on the voltage difference
between comparator inputs called overdrive. The overdrive
parameter should be considered when selecting the
comparator for this application.
In Fig. 6 the upper comparator is used to detect the
positive half cycle of the inverter output current and the
Fig. 5. Test results of the filter inductor used in the lower comparator is used to detect the negative half cycle of
experimental tests. the inverter current. In Fig. 6, the system is designed to
operate in single supply. Hence, the measured current signal
Kool Mµ is a very popular material which is used in high is shifted to positive voltage levels. In Fig. 6, positive half
frequency inductors in the industry. It has advantage of being cycle maximum peak current limit value is defined by iref_high,
low cost and has low core losses. Although it has good negative half cycle maximum peak current limit value is
properties, characteristics of a Kool Mµ core inductor defined by iref_low voltage reference.
significantly changes with the current. As the current
increases, the inductance value of the inductor decreases If current is outside of the limits, the output of the
significantly [14]. As discussed earlier, the filter inductance comparator shuts down PWM signal coming from controller
value has a big effect on the rising rate of the current. using “AND” gate. Thus, PWM signal to the driver is limited
Smaller filter inductance value leads faster short-circuit by using comparators. Then, the current shall decrease until
current, and this makes the current limiting more difficult. the measured current signal to be lower than the hysteresis
boundary of the comparators. The hysteresis band of the
In Fig. 4 and Fig. 5, characteristics of two different comparators determines the current ripple caused by analog
inductors with Kool Mµ cores are given. As it can be easily current limiting. After fault current is decreased to a certain
seen from figures inductance values decreases very level defined by comparator limits and hysteresis, the drive
significantly with increasing current. If short-circuit occurs signals are enabled again, and IGBTs continue their normal
just after the current sampling, current shall rise freely operation.
depending on the short-circuit voltage and inductance value
for . For worst – case scenario, the Eq. (2) is used to 3. Proposed Current Limitation Technique
calculate the current.
For VSIs, the limitation of excessive (over-load) and
(2) short-circuit currents are very important functions. Even a
discharged capacitor or a nonlinear load at the first instant
(3)
shall behave like a short circuit condition. At the turn on
(4) instant, a discharged capacitor operates like a short circuit
and draws very high currents which may destroy the
By using equation (2), (3) and (4), the short circuit switching devices. In addition, a load which includes
current rising is obtained as 48A within a single sampling magnetic components may draw high inrush currents during
cycle while the rated current is 21A. In addition, if the the magnetization transients. Therefore, employing a fast
inverter is operating at full load, the situation will be worse. current limiting function is very important feature for
The digital algorithm samples the current at 10kHz rate. In voltage-controlled inverters.

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In this study a hybrid current limiting method is mode from the constant voltage mode to constant current
proposed. This method combines the analog and digital mode, and IGBT current is limited successfully. After the
current limiting methods discussed earlier. In previous first cycle, the nonlinear load capacitors are charged. Then
sections, both methods are discussed and either method has the current decreases and system reaches to its steady state.
some disadvantages. By incorporating these two methods At the steady state, waveforms become periodical as seen in
together, better current limitation action can be achieved. Fig. 7. The digital current limiting algorithm can be applied
to single- or three-phase inverters. Here, all three phases of
In digital current limiting technique, the system operates
the three-phase inverter are controlled separately. From Fig.
in constant voltage mode if the current is below the digital
7 and 8, it is seen that digital current limiting technique
current limit. If the current is higher than digital current limit,
provides smooth output voltage waveforms at current
the system operates in constant current mode. The algorithm
limiting duration.
performs these transitions automatically. The digital
technique has advantage of generating smooth voltage Table 1. Parameters of the inverter used in experimental
waveform during current limiting. But for fast changing studies.
currents, the digital technique may not be able to catch the
faults and limit the fault currents. The analog current limiting Symbol Value
technique can detect and limit these currents. Unfortunately, Output Power, Pout 10 kVA
the analog technique cannot produce smooth waveforms
during current limiting stage when compared to digital Output Voltage, Vout 230 V
technique. Filter Inductor, Lf 900 µH
The analog and digital current limiting techniques are Filter Capacitor, Cf 20 µF
employed together to gain advantages of each technique. The Switching Frequency, fsw 10 kHz
reference value for the analog current limiting technique
should be set a higher value than the digital current limiting
algorithm. In this way, the analog current limiting technique
stops the current if the digital technique is insufficient. The
analog comparator circuit works at the first instant of the
excessive current and then the digital current limiting takes
over the control and provides a smooth current limiting
waveform.
The inverter and switching devices are immediately
protected from the high fault currents by the analog control
technique when the digital control is insufficient and fast
changing currents are handled. During the current limitation Fig. 7. Performance of the digital current limiting
transients, sensitive loads are not affected from inverter algorithm for nonlinear load.
voltage distortion because of the smooth current limiting
action of the digital technique. In addition, combinational use
of the digital current limiting technique yields higher RMS
voltage value than the analog technique during the current
limiting transients, which is also better for the sensitive
loads.
In the experimental part effect of both techniques will be
discussed separately, and then combination of the two
techniques will be discussed.

4. Experimental Tests and Results Fig. 8. Performance of the digital current limiting
algorithm for three-phase nonlinear load.
Proposed hybrid current limiting technique is
implemented and tested with the three-phase 10kVA inverter. Fig. 9 shows the current limiting response of the analog
Parameters of the inverter used in experimental tests are current limiting technique. The analog current limiting
given in Table 1. An uncontrolled rectifier with a filter technique successfully limits the overcurrent, but it has much
capacitor at its output is defined as a standard nonlinear test more ripple content compared to digital limiting technique.
load. For testing excessive currents, this standard load shall Besides, the resultant current oscillations cause audible noise
be used. in inverter filter inductances. For some applications, the
distorted inverter voltage may affect sensitive loads. If the
First inverter is tested with the standard nonlinear load. inverter supplies sensitive loads and nonlinear loads at the
In Fig. 7 and Fig. 8, the results obtained from these tests same time, every transient state caused by overcurrent can
when the digital current limiting technique is employed are disturb sensitive loads. Therefore, use of the analog current
given for single-phase and three-phase, respectively. At the limiting alone is not a good solution. In addition to that,
first instant, the algorithm is changed the inverter operation analog technique charges nonlinear load capacitance in a

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longer time compared to digital technique. Hence, transient

state durations are longer in the analog current limiting.
These may also have further effect on the sensitive loads.
The hybrid current limiting technique, as mentioned
before, combines the analog and digital current limiting
techniques to take benefits of both. In the proposed method,
the analog limit should always set at a higher value than the
digital limit value. In Fig. 10, the analog current limit level is
set to 55A whereas the digital limit is set to 18A. As seen
from the Fig. 10, at the first instant of the overcurrent, the
current is limited at 56A by the analog circuit. After a short Fig. 10. The current limitation performance of the hybrid
duration, the current limiting technique with nonlinear load when the
the analog current limiting value is set to 55A.
digital technique takes over the control, and the current is
reduced to 18A which is the digital current limiting value. To
show the current limiting capability of the analog technique,
the analog limiting level is reduced to 30A and same test is
repeated. Again, the nonlinear load is switched at the peak of
the inverter voltage which is the worst case. Fig. 11 shows
that the peak overcurrent current is now reduced to 29.6A by
analog circuit whereas the digital limit is stayed same as
18A. The nonlinear load tests in Fig. 10 and Fig. 11 are done
in the same conditions and at the same angle of the sine
(a)
wave. According to the experimental results proposed hybrid
current

(b)

Fig. 11. The current limitation performance of the hybrid

current limiting technique with nonlinear load when the
the analog current limiting value is set to 30A.

(c)
Fig. 9. Inverter response while the only analog current
limiting is active, a) The linear load condition, b)
Detailed look of linear load response, c) Nonlinear load
condition.
Fig. 12. Current limitation transient with nonlinear load.

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Fig. 13. The limitation of short circuit current. Fig. 17. Changing the current limiting set value during
the phase-to-phase short circuit.
limiting technique can stop the current at defined levels and
ensures the peak current value never exceeds the upper
analog limit. As it is clearly seen in Fig. 12, the proposed
hybrid current liming technique provides a smooth voltage
waveform at overcurrent conditions and gives fast current
limiting capability even at peak voltage short circuits.
Another important overcurrent topic is the short-circuit
conditions. The proposed technique can stop overcurrent
caused by different types of short-circuits without any
Fig. 14. The fault current when the short-circuit occurs modification on algorithm and analog circuit. In Fig. 13, the
at the peak of the inverter output voltage. phase-to-neutral short-circuit test result is given. Before the
short-circuit instant, the inverter operates at constant voltage
mode. When the short circuit occurs, the inverter switches to
constant current mode and output current becomes a square–
wave. At the short-circuit condition, the inverter output
voltage is nearly zero. It is clearly seen from Fig. 13 that the
proposed technique can successfully limit the short circuit. In
Fig. 14, the short-circuit duration is zoomed in. The short-
circuit condition occurring at the peak value of the output
voltage can be accepted as a worst case. It is seen that the
proposed hybrid technique can overcome short-circuit events
event at the worst case.
Fig. 15. The effect of short-circuit current set value. The fault current level which will occur at the short-
circuit instants can be controlled by changing
parameter in the digital current limiting algorithm. Fig. 15
shows the effect of this set value. The set value is decreased
at the short-circuit condition and obtained response is
depicted in the figure. As seen from the figure, the fault-
current is kept at this set value. The heat generated in the
semiconductor because of the conduction losses can be
minimized by changing the short-circuit current limit level.
Usually, cooling fans are supplied by the inverter output
voltage. Therefore, fans do not work at short-circuit
conditions. Decreasing the short circuit current may be a
solution for these kinds of semiconductor heating problems.
Fig. 16. The limitation of phase-to-phase short-circuit
current.

Fig. 18. Transition to normal operation from phase-to-

phase short-circuit.

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inductance values and thus helps to decrease on system cost

and size. The proposed current limiting algorithm is easy to
implement and easy to understand. Parameters of the
algorithm is also easy to tune. The algorithm has no effect on
the inverter voltage regulation under normal conditions and it
shows effect on the control path only at overcurrent
situations. Therefore, the proposed algorithm can run
together with different voltage regulation algorithms.

Acknowledgements
Fig. 19. Transition to normal operation from phase-to-
neutral short-circuit. This work was supported by the Scientific and
Technological Research Council of Turkey (TUBITAK)
By using proposed operation method longer short circuit under Grant 3161102.
currents can be supplied. In this way, the circuit breakers at
the load side can isolate the short–circuited load by removing References
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