Allegro PCB Design Solution

Managing complexity for faster, more cost-effective implementations

Systems companies are impacted by new devices and design methodologies offered by the semiconductor
industry. New devices often bring more challenges, like increasing pin counts packaged in shrinking pin
pitch ball grid arrays (BGAs). Additionally, new devices use evolving standards-based interfaces, such as
DDR3, DDR4, PCI Express® (PCIe®) Gen3, USB 3.0, and others, that may require learning new ways to
implement them on the board. Coupled with these increasingly complex technologies is the desire by
companies to differentiate their offerings and get them to market faster, cheaper, with more functionality
and in reduced end product size. As a result, many companies now outsource to or partner with companies
in low-cost geographies. To manage such increasing complexities, PCB designers need a solution that
addresses their technological and methodological challenges.

Allegro PCB
Design Solution
Cadence ® Allegro ® PCB Designer
is a scalable, proven PCB design
environment that addresses
technological and method-
ological challenges while making
the design cycles shorter and
predictable. Available in base
plus options configuration, the
PCB design solution contains
everything needed to create
a PCB layout with a fully inte-
grated design flow. The base—
Allegro PCB Designer—includes
a common, consistent constraint
management solution, PCB
Editor, an auto-interactive
router, as well as interfaces for
manufacturing and mechani-
cal CAD. PCB Editor provides a Figure 1: Allegro PCB design solution brings together all the tools needed to design simple-to-
complete placement and rout- complex PCBs
ing environment—from basic
floorplanning, placement, and • Eliminates unnecessary iterations • Features a common, consistent
routing to placement replication and through constraint-driven PCB constraint-management system
advanced interconnect planning—for design flow for creation, management, and
simple to complex PCB designs. validation of constraints from front
• Supports a comprehensive rule
to back
set for physical, spacing, design
Benefits for fabrication (DFF), design for • Open environment for third-party
• Offers a proven, scalable, assembly (DFA), and design for test application improves productivity
cost-effective PCB editing and (DFT), high-density interconnect while providing access to best-of-
routing solution in on-demand base (HDI), and electrical (high-speed) breed integrated point tools
plus options configuration domains
 Allegro PCB Design Solution

PCB Editor Technology

Constraint-Driven PCB Editing
Environment
At the heart of Allegro PCB Designer is
a PCB Editor—an intuitive, easy-to-use,
constraint-driven environment for creat-
ing and editing simple to complex PCBs.
Its extensive feature set addresses a wide
range of design and manufacturability
challenges:

• A powerful set of floorplanning and

placement tools including placement
replication for accelerating placement Figure 2: DFA rules-driven placement allows for compact placement of components without
of the design introducing errors

• Powerful shape-based shove, hug

cal representation of whether constraints Placement Replication
interactive etch creation, editing
pass (highlighted in green) or fail (high-
establishes a highly productive Superior placement replication technology
lighted in red). This approach allows
interconnect environment while within Allegro PCB Designer allows users
designers to immediately see the progress
providing real-time, heads-up displays to quickly place and route multiple similar
of the design in the spreadsheets, as well
of length and timing margins circuits in a design. It allows users to create
as the impact of any design changes.
a template using one instance of placed
• Dynamic shape capability offers
Floorplanning and Placement and routed circuit that can be applied to
real-time copper pour plowing and
other instances within the design. The
healing functionality during placement The constraint and rules-driven method-
saved placement template can be used
and routing iterations ology of PCB design solutions includes
with other designs where similar circuits
a powerful and flexible set of place-
The PCB Editor can also generate a full are used. When replicating placement,
ment capabilities, including interactive
suite of phototooling, bare-board fabrica- users can flip or mirror the circuit from top
and automatic. The engineer or designer
tion, and test outputs, including Gerber layer to bottom layer. All associated etch
can assign components or subcircuits
274x, NC drill, and bare-board test in a elements, including blind buried vias, are
to specific “rooms” during design entry
variety of formats. mapped to correct layers when circuit is
or floorplanning. Components can be
moved from top layer to bottom layer.
Constraint Management filtered and selected by reference desig-
nator, device package/footprint style, Display and Visualization
A constraint management system dis-
associated net name, part number, or the
plays physical/spacing and high-speed The built-in 3D viewer is available in all
schematic sheet/page number.
rules along with their status (based on PCB Editor products. The 3D environment
the current state of the design) in real With thousands of components compris- supports several filtering options, camera
time and is available at all stages of the ing today’s boards, precise management views, graphic display options such as
design process. Each worksheet provides is critical. Real-time assembly analysis solid, transparency, and wireframe, and
a spreadsheet interface that enables and feedback can facilitate this manage- mouse-driven controls for pan, zoom, and
users to define, manage, and validate the ment—helping designers increase spinning the display. 3D viewing also sup-
different rules in a hierarchical fashion. productivity and efficiency by placing ports the display of complex via structures
With this powerful application, designers components according to corporate or or isolated sections of the board. Multiple
can graphically create, edit, and review EMS guidelines. Dynamic DFA-driven display windows can be opened using the
constraint sets as graphical topologies placement offers real-time package- context sensitive command structure, and
that act as electronic blueprints of an to-package clearance checking during 3D images can be captured and saved in
ideal implementation strategy. Once they interactive component placement (see JPEG format. (See Figure 3.)
exist in the database, constraints can drive Figure 2). Driven from a two-dimensional
The flipboard capability “flips” the design
the placement and routing processes for spreadsheet array of classes and package
about its Y axis inverting the design data-
constrained signals. instances, real-time feedback provides
base in the canvas. This “flip” reorganizes
minimum clearance requirements. Based
The constraint management system is the display of the design such that what
on the package’s side-to-side, side-to-
completely integrated with the PCB Editor, was displayed as top through to bottom
end, designers can simultaneously place
and constraints can be validated in real becomes bottom through to top. Having
devices for optimum routability, manufac-
time as the design process proceeds. The a true bottom side view from within the
turability, and signal timing.
result of the validation process is a graphi- CAD system is essential for hardware

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 Allegro PCB Design Solution

ogy requirements—and it’s no wonder

that traditional CAD tools and technolo-
gies fall short of capturing a designer’s
specific routing intent and acting upon it.
The Allegro PCB Designer Design Planning
Option provides the technology and
methodology to capture as well as adhere
to a designer’s intent. Through the inter-
connect flow planning architecture and
the global route engine, users can for the
first time put their experience and design
intent into a tool that understands what
they want—natively.

Users create abstracted interconnect data

(through the interconnect flow planning
architecture) and can quickly converge on
a solution and validate it with the global
Figure 3: Built-in 3D viewer allows reviewing of a section of the board or complex via structures route engine. The interconnect abstrac-
with pan, zoom, rotation, and spinning to reduce iterations with mechanical design teams or PCB
tion reduces the number of elements the
fabricators without introducing errors
system has to deal with—from potentially
tens of thousands down to hundreds—
resulting in a significant reduction in the
engineers when debugging a board in the hours with traditional one trace at a time.
manual interaction required.
lab, or for assembly/test engineers on the Hug-contour option takes care of insert-
manufacturing floor. Flipboard is not just ing traces with curves that are aligned to Using the abstracted data, the planning
limited to viewing; design edits can also contour of the flex portion of the design. and routing process can be accelerated
be performed while in this mode. (See Figure 4.) by providing a visual/spatial map of the
open area in relation to the data and the
Interactive Etch Editing
Design Planning Option user’s design intent. The route engine can
The routing feature of the PCB Editor then deal with the details of the routing,
Highly constrained, high-density designs
provides powerful, interactive capabili- adhering to the specified intent, with-
dominated by bussed interconnect can
ties that deliver controlled automation to out the user having to both visualize and
take significant time to strategically plan
maintain user control, while maximizing solve the interconnect problems at once.
and route. Compound this with the
routing productivity. Real-time, shape- This significant simplification over current
density issues of today’s components,
based, any-angle, push/shove routing design tools means users converge on a
new signaling levels, and specific topol-
enables users to choose from “shove-
preferred,” “hug-preferred,” or “hug-
only” modes.

During etch editing, the designer can view

a real-time, graphical heads-up display of
how much timing slack remains for inter-
connect that has high-speed constraints.
Interactive routing also enables group
routing on multiple nets and interactive
tuning of nets with high-speed length or
delay constraints.

Multi-Line Routing
Multi-line routing allows users to quickly
route multiple lines as a group on the
PCB. Coupled with “hug-contour” option,
this utility can help designers route
multiple lines on the flex portion of the
Figure 4: Multi-line routing with contour hug option accelerates through no-click routing on flex
rigid-flex design in minutes instead of section of the PCB designs

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 Allegro PCB Design Solution

system then provides feedback through

the constraint manager if a signal doesn’t
conform to the topology or the rules asso-
ciated with the topology, ensuring that
issues are identified (and therefore can be
addressed) as quickly as possible.

The High-Speed Option also enables

checking of delays through vias, connec-
tor pins, and IC package-pin for die2die
length/delay matching. It includes, utilities
to identify trace segments crossing voids
(return path issues that cause re-spins),
supports back drilling (remove through
hole antennas) as well as provides a
timing environment that can acceler-
ate timing closure of critical nets up to
60-70%.
Figure 5: The Design Planning Option allows users reduce layer counts and shorten design cycle
through design planning Accelerated Timing Closure

successful interconnect solution far faster It offers an extensive range of electrical As the data rates increase and supply volt-
and more easily than ever before, reduc- rules to ensure that the PCB design imple- ages decrease in today’s advanced inter-
ing design cycle time through increased mentation is complaint with the specifica- faces like DDR3/DDR4, PCIe, SATA, etc.,
efficiency and productivity. (See Figure 5.) tion for advanced interfaces. Additionally, PCB designers must spend more time to
it allows users to extend the rules through ensure signals in an interface meet timing
Getting routes out of dense BGAs is requirements. With increasing density on
the use of formulas with existing rules
increasingly difficult for PCB designers. PCBs, the effort to get to timing closure—
or post-route data such as actual trace
With increasing pin counts and shrink- ensuring all signals meet timing require-
lengths.
ing pin pitches, the time PCB designers ments—can increase significantly. PCB
spend on getting routes in and out of The High-Speed Option allows users to designers need new tools to meet this
BGAs has gone up significantly. The tradi- apply a topology to a set of signals. A increasingly complex challenge.
tional approach of performing breakouts topology can include a set of routing
first then routing the traces between two preferences as well as constraints such Timing Vision
BGAs is running out of steam because as putting the termination resistor closer
Timing Vision is an innovative and unique
resolving the resulting crossovers takes up to either the driver or a receiver on a
environment that allows users to graphi-
a lot of time and board real estate. signal. The constraint-driven PCB design
cally see real-time delay and phase infor-
AiBT
Auto-interactive Breakout Technology
(AiBT) improves user efficiency by
allowing users to plan to break out on
both ends. AiBT can be used with the
new, Split View, and Bundle Sequence
commands to dramatically shorten the
time required to develop a high-quality
and properly ordered breakout solution
(see Figure 6).

High-Speed Option
Increasing use of standards-based
advanced interfaces such as DDR3,
DDR4, PCIe, USB 3.0 are bringing a set of
constraints that must be adhered to while
implementing a PCB.

The Allegro PCB Designer High-Speed

Option makes adhering to constraints
on advanced interfaces quick and easy. Figure 6: Split View allows working on both ends of a zoomed-in interface

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 Allegro PCB Design Solution

Backdrilling
The High-Speed Option allows users to
specify which vias on critical high-speed
signals should be back drilled to avoid
reflections. An output report—Backdrill
NC and Legend Files from Bottom, Top, or
Any Layer if backdrilling the inner core(s)
of the PCB—allows users to send back-
drilling instructions to their PCB manufac-
turers

Manufacturing Option
The Allegro PCB Designer Manufacturing
Option provides a comprehensive, power-
ful, easy-to-use suite of tools that makes
it efficient and cost effective for PCB
designers to streamline the development
of release-to-manufacturing packages for
their products. It includes three modules:
Design for Manufacturing (DFM) Checker,
Documentation Editor, and Panel Editor.

Figure 7: AiDT shortens time to tune high-speed signals by 50% or more.

DFM Checker
The Manufacturing Option’s DFM Checker
mation directly on the routing canvas. AiPT module is designed for engineers and
Traditionally, evaluating current status designers who appreciate the benefits
Differential pairs in an interface like DDRx of manufacturing analysis and want to
of timing/length of a routed interface
require designers to match static as well conduct it in a robust environment, with
requires numerous trips to Constraint
as dynamic phase. Matching phase for all ease and sensibility at any phase of the
Manager and/or use of the Show
differential pairs in an interface is a neces- PCB design process. DFM Checker offers
Element command. Using an embed-
sary first step before tuning and matching comprehensive analysis for all major
ded route engine to evaluate complex
the rest of the signals. AiPT automatically PCB design tools, Gerber files, intelli-
timing constraints and interdependen-
matches dynamic and static phase for gent manufacturing files, and NC data to
cies amongst signals shows current status
the selected differential pairs. It works ensure the content supplied to the manu-
of a set of routed signals—a DDRx byte
with a set of parameters that allows the facturer will minimize costly delays.
lane or a complete DDRx interface—
user several options for trace lengthen-
via custom trace/connect line coloring;
ing or shortening as well as pad entry/exit Documentation Editor
stipple patterns and customized data tip
options. With AiPT, users can significantly
information to define the delay problem The Manufacturing Option’s
shorten the time to match static and
in the simplest terms possible. Documentation Editor is a PCB documen-
dynamic phases for differential pairs.
tation-authoring tool that intelligently
With the embedded route engine, Timing
AiDT automates your documentation creation
Vision provides real-time feedback to
process to produce complex PCB docu-
the user during interactive editing and Delay tuning for signals for interfaces like mentation in a fraction of the time versus
enhances the user’s ability to develop DDRx takes up too much time when using traditional methods. Documentation
a strategy for resolving timing on large traditional, manual methods. AiDT auto- Editor enables you to quickly create the
buses or interfaces such as DDRx, PCIe, matically generates tuning patterns on a manufacturing drawings that drive PCB
etc. Coupled with Auto-interactive Phase user-selected routed byte lane or interface fabrication and assembly.
Tuning (AiPT) and Auto-interactive Delay based on user-defined timing constraints
Tuning (AiDT) capabilities, users can and tuning parameters. AiDT computes Panel Editor
accelerate the time to tune advanced the required length for the connections
The Manufacturing Option’s Panel Editor
interfaces like DDRx in one-third the time to meet timing constraints and utilizes
module intelligently automates the
it takes to do it manually using traditional controlled push/shove techniques when
complex process of panel definition and
methods. adding tuning patterns (see Figure 7).
documentation, simplifying the design
process. This solution enables designers
to quickly create electronic manufactur-
ing documents that clearly articulate

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 Allegro PCB Design Solution

the panel specification and instructions inner layers. The Miniaturization Option Routing Option
for successful fabrication, assembly, and offers constraint-driven embedded compo-
The Allegro PCB Designer Routing Option
inspection of their designs. nent placement and routing. It supports
is tightly integrated with the PCB Editor.
direct- and indirect-attach techniques, and
Design Data Transfer to Through the Routing Option interface, all
supports embedding components with
Manufacturing design information and constraints are
dual-sided contacts, vertical components,
automatically passed from the PCB Editor.
A full suite of phototooling, bare-board and embedding in dielectric on a two-layer Once the route is completed, all route infor-
fabrication, and test outputs, including PCB. Additionally it offers the ability to mation is automatically passed back to the
Gerber 274x, NC drill, and bare-board test create and manage cavities on layers speci- PCB Editor.
in a variety of formats, can be generated. fied for embedding components.
Increased design complexity, density,
More importantly, Cadence supports
Analog/RF Option and high-speed routing constraints make
the industry initiative toward Gerber-less
manual routing of PCBs difficult and
manufacturing through export and import The Allegro PCB Designer Analog/RF time-consuming. The challenges inher-
of design data in IPC-2581 format. The Option offers a mixed-signal design envi- ent in complex interconnect routing are
IPC-2581 data is passed in a single file ronment, from schematic to layout with best addressed with powerful, automated
that creates accurate and reliable manu- back annotation, proven to increase RF technology. The robust, production-
facturing data for high-quality manufac- design productivity up to 50%. It allows proven autorouter includes a batch rout-
turing. Users have a choice to export a engineers to create, integrate, and update ing mode with extensive user-defined
subset of the design data for protecting analog/RF/microwave circuits with digi- routing strategy control as well as built-in
their IP. Import of IPC-2581 is intended for tal/analog circuits in the Allegro PCB automatic strategy capabilities.
overlaying artwork data on the design for Design environment. With its rich layout
viewing purposes only. capability and powerful interfaces with DFM Rules-Driven Autorouting
RF simulation tools, it allows engineers The design for manufacturing capabil-
Miniaturization Option to start RF design from Allegro Design ity within the Routing Option signifi-
Authoring, Allegro PCB Designer, or cantly improves manufacturing yields.
Constraint-Driven HDI Design Flow Keysight Technologies Advanced Design Manufacturing algorithms provide a
System (ADS). spreading capability that automatically
With BGA pin pitches decreasing to below
1mm, (0.8mm or lower with 0.65mm increases conductor clearances on a
or 0.5mm pin pitches), users are forced
Team Design Option space-available basis. Automatic conduc-
to implement a buildup PCB technology Globally dispersed design teams are on tor spreading helps improve manufactu-
using HDI. the rise, which compounds the challenge ability by repositioning conductors to
of shortening design cycle times. Manual create extra space between conductors
While miniaturization is not necessar- and pins, conductors and SMD pads, and
workarounds that address multi-user
ily the primary objective in many market adjacent conductor segments. Users gain
issues are time-consuming, slow, and
segments, the move to buildup technol- prone to error. the flexibility to define a range of spacing
ogy is necessary for fanning out a BGA— values or to use the default values.
particularly if it has three or four rows of The Allegro PCB Designer Team Design
Option provides a multi-user, concurrent Mitered corners and test points can be
pins on each side.
design methodology for faster time to added throughout the routing process.
The Allegro PCB Designer Miniaturization market and reduced layout time. Multiple The manufacturing algorithms auto-
Option offers a proven constraint-driven designers working concurrently on a matically use the optimal setback range,
HDI design flow with a comprehensive layout share access to a single database, starting from the largest to the smallest
set of design rules for all different styles regardless of team proximity. Designers value. Test point insertion automatically
of HDI designs, from a hybrid buildup/ can partition designs into multiple adds testable vias or pads as test points.
sections or areas for layout and editing Testable vias can be probed on the front,
core combination to a complete buildup
by several design team members. back, or both sides of the PCB, support-
process like ALIVH.
Designs can be partitioned vertically ing both single side and clamshell testers.
In addition, it includes automation for (sections) with soft boundaries or hori- Designers have the flexibility to select the
adding HDI to shorten the time to create zontally (layers). As a result, each designer test point insertion methodology that
designs that are correct by construction. can see all partitioned sections and conforms to their manufacturing require-
update the design view for monitoring ments. Test points can be “fixed” to avoid
Embedded Components costly test fixture modifications. Test point
the status and progress of other users’
sections. Such partitioning can dramati- constraints include test probe surfaces, via
Reducing end product size can be accom-
cally reduce overall design cycles and sizes, via grids, and minimum center-to-
plished in many different ways. One of
accelerate the design process. center distance.
the approaches PCB designers are taking
is to embed packaged components on

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 Allegro PCB Design Solution

High-Speed Constraints-Driven Allegro PCB Designer Base Plus Options Features

Autorouting
Feature Allegro PCB Designer
High-speed routing constraints and algo-
Allegro Design Authoring •
rithms handle differential pairs, net sched-
Allegro Design Entry CIS •
uling, timing, crosstalk, layer set routing,
and the special geometry requirements Constraint Manager: Physical, spacing, and samenet rules •
demanded by today’s high-speed circuits. Constraint Manager: Properties and DRCs •
The autorouting algorithms intelligently Constraint Manager: Differential pair rules •
handle routing around or through vias, Constraint Manager: Region rules •
and automatically conform to defined
Floorplanning, placement, placement replication •
length or timing criteria. Automatic net
DFA, DFF, DFT •
shielding is used to reduce noise on noise-
sensitive nets. Separate design rules may Dynamic feedback on DFA compliance during placement •
be applied to different regions of the IDF3.0, DXF in/out •
design; for example, you can specify tight EDMD schema-based ECAD-MCAD co-design •
clearance rules in the connector area of a Native 3D viewer •
design and less stringent rules elsewhere. Hierarchical interconnect flow planning •
Length-based rules for high-speed signals •
Operating System Support
Constraint-driven flow for length-based high-speed signals •
Allegro Platform Technology: Match groups, layer sets, extended nets •

• Sun Solaris T-point rules (pin to T-point) •

6-layer automatic shape-based autorouter •
• Linux
High-speed rules-based autorouting •
• IBM AIX Layer-specific rules-based autorouting •

• Windows Design planning - plan spatial feasibility analysis and feedback Design Planning Option
Design planning - generate topological plan Design Planning Option
OrCAD Technology: Design planning - Convert topological plan to traces (CLINES) Design Planning Option
• Windows Auto-interactive Delay Tuning High-Speed Option
Constraint Manager: Electrical rule set (relection, timing, crosstalk) High-Speed Option
Constraint-driven flow using electrical rules High-Speed Option
Electrical constraint rule set (ECSets) / topology apply High-Speed Option
Formula and relationship-based (advanced) constraints High-Speed Option
Backdrilling High-Speed Option
Die2Die pin delay, dynamic phase control, Z-axis delay High-Speed Option
Return path management for critical signals High-Speed Option
Constraint Manager: HDI rule set Miniaturization Option
Micro-via and associated spacing, stacking, and via-in-pad rules Miniaturization Option
Constraint-driven HDI design flow Miniaturization Option
Manufacturing rule support for embedding components Miniaturization Option
Embedd components on inner layers Miniaturization Option
HDI micro-via stack editing Miniaturization Option
Dynamic shape-based filleting, line fattening, and trace filleting Miniaturization Option
Hug contour routing (Flex) Miniaturization Option
Support for cavities on inner layers Miniaturization Option
Concurrent team design - layer-by-layer partitioning Team Design Option
Concurrent team design - functional block partitioning Team Design Option
Concurrent team design - team design dashboard Team Design Option
Concurrent team design - soft nets Team Design Option
Edit constraints in a partition Team Design Option
Manage netclasses in a partition Team Design Option
Parameterized RF etch elements editing Analog/RF Option
Asymmetrical clearances Analog/RF Option
Bi-directional interface with Keysight ADS Analog/RF Option

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 Allegro PCB Design Solution

Cadence Services and Support Feature Allegro PCB Designer

• Cadence application engineers can Import Keysight ADS schematics into DE-HDL Analog/RF Option
answer your technical questions by Layout-driven RF design creation Analog/RF Option
telephone, email, or Internet—they can Flexible Shape Editor Analog/RF Option
also provide technical assistance and 256-layer autorouting Routing Option
custom training
DFM rules-based autorouting Routing Option
• Cadence certified instructors teach Automatic trace spreadiing Routing Option
more than 70 courses and bring their ATP generation Routing Option
real-world experience into the classroom Layer-specific rules-based autorouting Routing Option
• More than 25 Internet Learning
Series (iLS) online courses allow you
the flexibility of training at your own
computer via the Internet

• Cadence Online Support gives you 24x7

online access to a knowledge base of
the latest solutions, technical documen-
tation, software downloads, and more

For More Information

For product sales, support, or additional
information on Allegro solutions, visit
www.cadence.com/contact_us to locate
a Cadence Sales office or channel partner
in your area.

Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify today’s mobile, cloud, and connectivity applications. www.cadence.com

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