738 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO.

4, JULY/AUGUST 1998

A Zeroth-Order Phase-Locked
Loop Control Algorithm
Novica A. Losic, Senior Member, IEEE

Abstract— A method of minimizing dynamics and reducing

phase error toward zero for arbitrary input frequency/phase
while maintaining stability in phase-locked loops (PLL’s) is pre-
sented. The system transfer function becomes theoretically of zero
order and the error is zero. Practically, the steady-state phase
error is zero and the system is of minimum dynamics/order. The
method is in synthesizing a feedforward control that is added
to the standard PLL. The feedforward, effected from the system
input to a summing junction, comprises an inverse feedforward Fig. 1. Illustrating standard PLL.
control principle relative to the part of the feedback loop seen
after the summing junction.
a type-1 system, i.e., the system having in the control loop
Index Terms—Feedforward control, phase-locked loops, track- (in loop gain) one pole at the origin, is required to maintain
ing control. zero steady-state error for step change in input, while it is
I. INTRODUCTION required to have type-2 or type-3 system to eliminate steady-
state error for ramp or parabolic input change, respectively.

A PHASE-LOCKED loop (PLL) is a control system that

controls a phase of an output oscillation signal to align
it with the phase of an input/reference oscillation signal. In
However, this requirement usually results in the system not
being stable at higher frequencies if not properly compensated,
because of the increased system order (wih each new pole at
doing so, it obviously makes the frequencies of the two origin an additional 90 of phase shift is ultimately contributed
signals equal and then tries to minimize the phase error through the loop). As a general rule, it can be stated that
between them. As a byproduct of this action, a voltage the tradeoff between system stability and performance, i.e.,
signal proporional to the change in frequency/phase of the the magnitude of the error, has to be made. This reduces to
input signal is generated at the point in the loop and it achieving higher performance at the expense of more complex
represents the system’s actual output. Thus, if the input signal stability compensating schemes.
is frequency- or phase-modulated, this voltage signal becomes Before leaving the description of the system of Fig. 1, it
the demodulated output of the PLL. A block diagram of a should be noted that, fundamentally, the PLL can operate
standard/classical PLL is shown in Fig. 1. There exist linear, on input signals buried in noise as the low-pass filtering
digital, all-digital and software PLL’s [1]. The system in Fig. 1 effectively averages control action, so that the frequency fed
can be used to represent any of them. back through the loop is equal to the average frequency of
In Fig. 1, the phase/frequency detector (PFD) compares the the input and, thus, no control action is produced with respect
input frequency and phase with the frequency and phase of the to the essentially stochastic noise behavior. Nevertheless, the
signal fed back through the loop. The error is low-pass filtered noise rejection is directly proportional to the order of the
as it can be shown that only dc varying components are of low-pass filter (LPF) which, again, calls for an increasingly
interest. The filtered voltage controls an oscillator to produce elaborated stabilization scheme.
a feedback signal of such a frequency and phase which, after a It is, therefore, desirable to synthesize a PLL system to force
possble frequency division by an integer should be the same steady-state phase error to zero for any type of change of input
as the frequency and phase of the input signal, thus forcing frequency and/or phase and to maintain the system stability
the steady-state phase error at the detector output toward with the simplest possible means. This simplicity would be
zero. As in any feedback control system, the error would be possible if the system order is kept low. As a matter of fact,
exacly zero, regardless of the type of change of the frequency as it will be shown, the system order will theoretically be zero
or phase of input signal, e.g., step, ramp, parabolic, cubic, and practically minimized.
etc., if the system is of the appropriate type. For example, The synthesis method is described in Section II. The veri-
Paper MSDAD 97–44, presented at the 1994 Industry Applications Society fication results are shown in Section III. Section IV gives the
Annual Meeting, Denver, CO, October 2–7, and approved for publication conclusions.
in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Au-
tomation and Control Committee of the IEEE Industry Applications Society.
Manuscript released for publication March 30, 1998. II. THE SYNTHESIS METHOD
The author is with AlliedSignal Aerospace Canada, Etobicoke, Ont., M9W
6L7 Canada. Fig. 2 illustrates a zeroth-order PLL. A feedforward control
Publisher Item Identifier S 0093-9994(98)05428-0. is added to the standard loop. The feedforward path consists
0093–9994/98$10.00  1998 IEEE
LOSIC: A ZEROTH-ORDER PLL CONTROL ALGORITHM 739

transfer function of the low-pass filtering/stabilizing circuit in

V/V, is the VCO gain in rad/s/V, is the frequency
division integer, is the gain of the f/V in V/rad/s, and
is the gain of the correction circuit in V/V. The radial
frequencies and in rad/s are integrated to produce
the respective phases and in rad, which are then
compared in the phase comparator, the output of which is a
phase error
Fig. 2. Illustrating zeroth-order PLL. From Fig. 3,
(1)

(2)
(3)

It is seen from (1) that a zero phase error, i.e.,

may be achieved for any type of change of input
phase/frequency if the gain of the correction circuit in the
feedforward path is set to a constant value
Fig. 3. Block diagram of zeroth-order PLL.
(4)

The zero phase error is achievable only in steady state,

of a frequency-to-voltage converter (f/V) followed by a gain
because in physical systems, nonzero transient errors are
correction circuit. The feedforward control voltage is summed
unavoidable due to the finite energy capability of physical
with the voltage from the LPF. The resulting control voltage
sources, finite power dissipation ratings of physical com-
is applied to the voltage-controlled oscillator (VCO).
ponents, and finite speed of transition of control signals.
For the appropriate gain in the feedforward path, the steady-
However, for the correction gain set to the value called
state phase error will be zero for any type of change of input
for in (4), and for the optimum adjustment of the stabilizing
frequency/phase. At the same time, the system order will be
circuit of transfer function a minimum transient error
zero. The system phase/gain margin is controlled by the filter-
is achieved.
ing/stabilizing circuit, which can be chosen to remain simple.
Substituting (4) in (2),
The phase/frequency detector (PFD) can also be chosen to
be simple; it can be only a phase detector, for example. The (5)
system in Fig. 2 operates such that the feedback loop and the
feedforward path act together to reduce the error to zero. the result that could have been expected from the zero phase
Since, in general, the feedforward is not a robust control, error result, as
while the feedback is, their mutual operation is necessary for Equation (5) implies a zeroth-order system. A generalized
robustness, i.e., to minimize the effects of possible changes of synthesis of zeroth-order systems, different from the method
the parameters of the plant (VCO, in this case). described here, has been reported in [5]. Some applications,
Adding feedforward control to a feedback control system is based on algorithms not applicable here, are described in [6]
done relatively often in practice. An example may be found and [7].
in robotic applications [2]. The feedforward control is also From (1) and (2), it is seen that both transfer functions have,
found in process control systems and for disturbance rejection as expected, the same denominators:
purposes (if the disturbance can be measured). In these exam- (6)
ples, the required transfer function of the feedforward control
block may be rather difficult to implement, and sometimes it For the system in Fig. 3 to be stable, its poles, which are
is not realizable [3]. It is basically a function of the plant. the roots of the characteristic equation
Nevertheless, in many applications, an approximation to the
(7)
required feedforward transfer function is realized to improve
the system performance. It can be furthermore argued that, must all lie in the left-half plane of the plane. Clearly, the
even if the exact transfer function of the feedforward control locations of the characteristic roots are functions of the transfer
block is realized, a transfer function is only an approximate function of the filtering/stabilizing circuit , as seen from
model of a physical system [4]. (3), (6), and (7). Thus, the system stability, i.e., the phase
As it will turn out, the required transfer function of the and gain margin obtained from Bode plots of magnitude and
feedforward control in Fig. 2 is a constant, which greatly phase of the loop gain is controlled by an appropriate
simplifies its realization. It should be noted at this point that the -domain
A block diagram of the zeroth-order PLL is shown in Fig. 3. analysis, performed here, is valid only when the system is
In Fig. 3, is the detector gain in V/rad, is the in lock, otherwise the system is nonlinear and alternative
740 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO. 4, JULY/AUGUST 1998

(a) (b)

(c) (d)
Fig. 4. Illustrating low-pass filtering/stabilizing circuits.

techniques, such as a phase-plane method, are to be used for forward to implement. It can be shown that the proposed
the analysis. feedforward control requires that the system transfer function
Both results, i.e., the zero steady-state error and zeroth- denominator, obtained upon substitution of the feedforward
order system, are ideally achievable only for the exact value algorithm in it, is a Hurwitz polynomial. This requirement,
of the feedforward gain as called for in (4), valid only if as it turns out, may be satisfied by appropriate choice of
the pure gains indeed model the blocks involved on the the loop compensator and by the numerator of the
right-hand side of (4). Such an ideal situation would imply plant transfer function being itself a Hurwitz polynomial. (It
that the system poles and zeros are at exactly the same should be recalled that a Hurwitz polynomial is characterized
locations in the plane, cancelling each other in (2), which as having all of its zeros lying in the left half of the
then results in (5). Any deviation from this ideal case would plane). The requirement for the numerator of the plant transfer
provide no perfect pole–zero canellation, with the outcome less function to be a Hurwitz polynomial classifies such plant
than the ideal. However, in a practical system, no algorithm as a minimum phase system. Thus, it can be stated that the
of the nature of the closed-form expression as in (4) is inverse dynamic feedforward control is possible if, and only
ideally implementable (ultimately because of the component if, the given system is minimum phase. In robotic applications,
tolerance or finite precision in software implementation), and the feedforward control usually requires that one or more
an approximation to the desired algorithm is always used, at derivatives of the input/reference signal be applied as direct
least within the mentioned ultimate constraints. Nevertheless, inputs to the given system, as a physical system, i.e., the plant
even with these constraints, the system performance is greatly is generally characterized by a strictly proper transfer function,
improved. i.e., its denominator is usually of a higher degree than its
The algorithm in (4) is actually a result of the inverse (dy- numerator.
namic) feedforward control applied, in particular, in robotics In the case of the system of Fig. 3, the plant is greatly
[2]. There, the implementation is more involved, as the plant simplified. Here, it is the VCO. (In some PLL’s it may be a
is, in general, a higher order system. It is used to enable current-controlled oscillator, which does not affect the method
tracking of a time-varying trajectory that, in general, may be a presented here.) If it is characterized by a pure gain the
high-order polynomial function of time, with zero steady-state most straightforward implementation of the control algorithm
error. Clearly, the required control would be considerably more follows from (4). As will be discussed in the next section,
complex than a simple proportional integral derivative (PID) a practical VCO may not have quite linear, i.e., constant
controller. gain, transfer characteristic. It may also have some voltage
The inverse dynamic feedforward control was found to be offset, i.e., a nonzero voltage is required to produce zero
an alternative control technique that was relatively straight- output frequency from the VCO. While the latter is relatively
LOSIC: A ZEROTH-ORDER PLL CONTROL ALGORITHM 741

easy to compensate for by summing an extra offset voltage to

the feedforward voltage and the low-pass-filtered voltage, the
nonlinearity may require appropriate (inverse) correction in the
algorithm in (4). The appropriate correction is also required if
the f/V in Fig. 3 cannot be characterized by pure/linear gain
and without offset. Of course, the algorithm of (4) in the case
of a frequency synthesis should be implemented for variable
As for the requirement that the system transfer function
denominator, obtained upon substitution of the feeforward
algorithm in it, is a Hurwitz polynomial, it is easily satisfied by
the appropriate choice of in the characteristic equation
(7), obtained from (6) and (3), wherein in (3), is
replaced by
For a first-order filter, the characteristic equation becomes a
standard second-order equation (due to the inherent integration
in the loop), the roots of which can easily be placed in the left
half of the plane. While higher order filters may be used in (a)
standard PLL’s, the choice of one of several types of first-order
filters will be discussed here. It should be noted that the order
of the filtering/stabilizing circuit is not of a consequence to the
functioning of the algorithm of (4), as long as the described
Hurwitz polynomial is maintained.

A. The Low-Pass Filtering/Stabilizing Circuits

Fig. 4 shows several types of the first-order filters com-
monly used in a standard PLL. Any of these, or others not
shown here, may be used in conjuction with the system of
Fig. 3. It is preferred, however, to use the simplest possible
scheme, as long as the noise rejection requirement does not
impose the use of a higher order filter. The objection of the
noise going through the f/V and, thus, bypassing the filter
neglects the inherent integration/low-pass filtering in an f/V,
i.e., the fact that an f/V is a block which performs an integration (b)
(1/s, in s) upon the input frequency, in 1/s, and multiplies the Fig. 5. Response to input phase step change (input frequency is Dirac
impulse change). (a) Standard system. (b) Zeroth-order system.
(dimensionless) result with a voltage.
The simplest (passive) LPF, in Fig. 4(a), has a pole at
finite angular frequency , while the passive filter PLL of Fig. 3 allows the simplest filter of Fig. 4(a) to be used
of Fig. 4(b) has a pole frequency at and a zero and to still achieve zero steady-state phase error for any order
frequency at The active filter in Fig. 4(c) has a of polynomial describing the input frequency/phase change,
dc gain of a pole frequency at , and whereas the stability problem is minimized. This is the main
a zero frequency at Finally, the active filter in advantage of the system of Fig. 3.
Fig. 4(d) has a zero frequency at and a pole at
origin with, consequently, the highest possible dc gain, equal
to the op amp open-loop gain. Thus, while the first three filters III. THE PERFORMANCE RESULTS
would have created a nonzero phase error in steady state after, Both simulation and experiment have been used to verify
for example, a step change in input frequency, the filter in the results of the synthesis. In evaluating the PLL systems of
Fig. 4(d) would force this error to essentially zero, so that its Figs. 1 (standard) and 2 (zero order), the filter of Fig. 4(a) has
output, obtained by multiplying the essentially zero error with been used to emphasize its sufficiency to the synthesis of the
the circuit dc gain equal to the op amp open-loop gain, would zeroth-order system and the insufficiency of this simplest filter
settle to a required new dc voltage level after the step change for the standard PLL as the order of the polynomial describing
to support the new required frequency of the VCO. However, the input phase/frequency change increases. As discussed in
for a higher order polynomial describing input frequency/phase the previous section, using any of the (first order) filters of
change, the phase error would be nonzero and the PLL might Fig. 4 results in a second-order PLL.
not be able to lock in (nonzero frequency error would exist). In The simulation results, shown in Figs. 5–8, are obtained for
such cases, as well as for further noise rejection, higher order a progressively increasing order of polynomial describing the
LPF’s could be used, requiring a more complex stabilization change of input frequency/phase. It is seen from Fig. 5 that,
scheme for such higher order systems. Using the zeroth-order as expected, the standard PLL using the LPF of Fig. 4(a) is
742 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO. 4, JULY/AUGUST 1998

(a) (b)

(c) (d)
Fig. 6. (a) Response to input frequency step change—standard system. (b) Response to input frequency step change—zeroth-order system. (c) Response to
input phase ramp change—standard system. (d) Response to input phase ramp change—zeroth-order system.

able to maintain zero steady-state phase error for input phase order system, as seen from the same figure, locks to any input
step change, corresponding to a Dirac impulse change in input frequency change and has a zero steady-state phase error. It
frequency, because of the inherent pole at the origin due to the has less error, even for very large deviation in the required
transformation of the frequency of the VCO to phase in the value of , as seen from Fig. 8(a) and (c).
loop. Furthermore, as seen from Fig. 6, the standard system In Figs. 5–8, input, output, and average phase error are
is able to lock to the step-changed input frequency, i.e., to represented by voltages V(VTETAIN), V(VTETAOUT), and
maintain zero steady-state frequency error for the prescribed V(VTETAE), respectively, while the input and output fre-
magnitude of the change, because of the pure integration (pole quency are represented with V(VFIN) and V(VFOUT), respec-
at origin) performed upon the input frequency, i.e., in the path tively. An offset voltage exists in connection with the VCO
of the signal. However, a nonzero steady-state phase error which, when accounted for, eliminates “negative” frequency
now exists for the corresponding ramp change of input phase. responses in some of the figures.
In addition to the inherent pole at the origin of the VCO, the In the breadboard circuit of Fig. 9, the industry standard
standard system would need another pole at the origin provided 4046 PLL IC has been used to prototype the inverse feed-
by an LPF, such as the one in Fig. 4(d), with the associated forward control around it. The feedforward path consists of
stability problems, to force this error to zero. an f/V, correction gain ciruit, and summing circuits. The f/V
In Figs. 7 and 8, the standard system cannot lock to the ramp conditions input pulses by differentiating and inverting them
and parabolic changes in input frequency, respectively, i.e., the for triggering the 555 monostable, which feeds the conditioned
steady-state frequency error (constant in Fig. 7 and linearly pulses to the second-order active LPF followed by a first-order
increasing in Fig. 8) exists. The steady-state phase error for the passive integrating network. The gain correction and summing
corresponding parabolic and cubic change in the input phase is circuits are built using TL 084 op amps. The LPF, as seen
linearly and parabolically increasing, respectively. The zeroth- from Fig. 9, is of the type shown in Fig. 4(b) (needed for
LOSIC: A ZEROTH-ORDER PLL CONTROL ALGORITHM 743

(a) (b)

(c) (d)
Fig. 7. (a) Response to input frequency change consisting of ramp segments—standard system. (b) Response to input frequency change consisting of
ramp segments—zeroth-order system. (c) Response to input phase change consisting of parabolic segments—standard system. (d) Response to input phase
change consisting of parabolic segments—zeroth-order system.

optimum performance of the standard circuit). The necessary The phase detector further deteriorates the standard system
buffering to prevent loading the relevant blocks of Fig. 3 performance; the performance of the zeroth-order system is
is implemented, too. There is no frequency division in the unaffected.
feedback loop, thus, the required correction gain is found from Fig. 11 shows the responses of standard and zeroth-order
(4) for systems, in the form of the VCO driving voltage, for the
The transfer characteristics of the VCO and f/V were exper- step-modulated input frequency. It is seen that, for the size of
imentally found and plotted in Fig. 10. As seen from Fig. 10, the step modulation, the standard system is effectively unable
the VCO has an offset voltage. [Denoting the offset voltage to lock (the variation in the VCO voltage is effectively the
the output frequency versus the driving voltage is variation in its frequency). The zeroth-order system pulls in
given by ]. To eliminate the effects of the perfectly and stays locked. The peak to peak of the frequency
offset voltage, the same amount of voltage is added to the sum- step modulation is 15.43 kHz, i.e., 7.715 kHz relative to the
ming junction. Fig. 10 also indicates that a slight nonlinearity VCO center frequency set to 16.66 kHz. Thus, the VCO is
is present in the VCO characteristic. An approximately linear modulated to change its frequency from 8.945 to 24.375 kHz
portion of the characteristic, between about 9–25 kHz, is used in a step manner. The frequency of the modulation is about
for the VCO frequency to sweep through in response to the 70 Hz.
input frequency step modulation. Otherwise, the nonlinearity The principle of the described synthesis has been applied
should be appropriately incorporated in the expression of (4). in designing a PLL used in a projection system synchronizing
The 4046 IC has two types of detectors, an “exclusive or” logic section. When a VCR signal was fed to the system, the signal
gate (EXOR) phase detector and a PFD. Both were evaluated was difficult to synchronize to in the case of a worn-out
and the results in Fig. 11 are for the PFD detector used. tape. In such a case, the input frequency/phase change could
744 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO. 4, JULY/AUGUST 1998

(a) (b)

(c) (d)

(e) (f)
Fig. 8. (a) Response to input frequency parabolic change—standard system. (b) Response to input frequency parabolic change—zeroth-order system. (c)
K K
Response of the zeroth-order system for large variations in C of Fig. 3. C halved with respect to the required value (bottom trace represents output
K K
frequency). (d) Response of the zeroth-order system for large variations in C of Fig. 3. C doubled with respect to the required value (top trace represents
output frequency). (e) Response to input phase cubic change—standard system. (f) Response to input phase cubic change—zeroth-order system.
LOSIC: A ZEROTH-ORDER PLL CONTROL ALGORITHM 745

Fig. 9. Circuit diagram of the experimental system.

Fig. 10. Transfer characteristics of VCO and f/V.

be considered an th-degree polynomial-like change. The at this point that, after the completion of this work, it was
zeroth-order algorithm greatly improved the pull-in process, brought to the author’s attention that “helping a PLL” by
increasing capture and hold range, i.e., providing the lock “adding a f/V converter” appeared in [8]. However, in [8],
under the unfavorable conditions. It should also be mentioned the subject matter is given from a brief, intuitive, point of
746 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO. 4, JULY/AUGUST 1998

implementation alone may be sufficient. However, because

the plant here, which is the VCO, is slightly nonlinear, but
is approximated by a constant gain which, on the other side,
(a)
may change (for example, with temperature—the temperature
change actually representing the disturbance in the plant),
to minimize the effects of the disturbance (as well as to
(b)
linearize the plant), i.e., to improve the system “robustness,”
the feedback part of the PLL is used in addition to the
feedforward. The implementation of the inverse feedforward
control requires, nevertheless, some extra circuitry to realize
an f/V, a correcting amplifier, and summing means. This,
(c) however, may be justified if the performance described above
is needed. In addition to providing for zero steady-state phase
error for any input change without aggravating the stability
problem, the synthesis also essentially increases the phase
margin of a classical PLL, as seen from some simulation and
experimental results.

REFERENCES
Fig. 11. Response of the VCO driving voltage to a step input frequency [1] R. E. Best, Phase-Locked Loops, 2nd ed. New York: McGraw-Hill,
modulation of approximately 50% of the VCO center frequency. (a) Standard 1993.
system. (b) Zeroth-order system. (c) Modulation. [2] W. A. Wolovich, Robotics: Basic Analysis and Design. New York:
Holt, Rinehart and Winston, 1987, pp. 331–336.
[3] J. V. de Vegte, Feedback Control Systems, 2nd ed. Englewood Cliffs,
NJ: Prentice-Hall, 1990, pp. 240–241.
view (quotations above are from [8]), without mention of the [4] C. L. Phillips and R. D. Harbor, Feedback Control Systems. Engle-
use of the inverse dynamic control principle and associated wood Cliffs, NJ: Prentice-Hall, 1988, pp. 160–161.
mathematical treatment, such as that developed and described [5] N. A. Losic et al., “Control basic building block (CBBB),” U.S. Patent
5 282 129, May 1993.
here. [6] , “Synthesis of drive systems of infinite disturbance rejection ratio
and zero-dynamics/instantaneous response,” U.S. Patent 4 990 001, Feb.
1991.
IV. CONCLUSIONS [7] , “Current-free synthesis of improved parameter-free zero-
impedance converter,” U.S. Patent 5 034 872, July 1991.
Using the inverse feedforward control principle, a zeroth- [8] “LM2907 tachometer/speed switch building block applications,” Na-
order PLL has been synhesized. It is able to lock to an tional Semiconductor Corp., Santa Clara, CA, Application Note 162,
1989, p. 13.
arbitrary input frequency/phase change profile, described by
an th-order polynomial, with zero steady-state error ensuring
simultaneously the system stability with the simplest possible
means, i.e., the simplest low-pass-filtering/stabilizing circuit Novica A. Losic (M’83–SM’94) was born in Zaje-
is used. Also, a simple phase detector, rather than a more car, Yugoslavia, in 1946. He received the Dipl.Ing.
degree from the University of Beograd, Yugoslavia,
complex PFD, may be used with the pull-in range practically and the M.Eng. and Ph.D. degrees from the Uni-
limited with only the frequency range of the VCO. Normally, versity of Toronto, Toronto, Ont., Canada, in 1970,
this property in standard PLL’s, regardless of the kind of the 1977, and 1981, respectively, all in electrical engi-
neering.
LPF, is obtained at the expense of a more involved PFD. During the past 25 years, he has been with Gen-
However, the use of the inverse feedforward control together eral Electric Company, University of Wisconsin,
with the PFD would make the system further improved, in Parkside, and Lockheed Martin-KAPL, Schenec-
tady, NY, where he designed and developed signal
that it would speed up the lock-in process and ensure it processing, power electronics, and control circuits, as well as teaching and
remains locked. As expected, the addition of the feedforward conducting research in the areas of circuits, systems, and controls. He is
path does not affect the system stability, i.e., it does not currently with AlliedSignal Aerospace Canada, Etobicoke, Ont., Canada. He
has published over 50 research papers and has been granted 11 U.S. patents.
change the closed-loop system characteristic equation. In an Dr. Losic is a member of the Professional Engineers of Ontario, Canada,
ideal case of a linear and invariant plant, the feedforward and the New York Academy of Sciences.