IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO.

1, JANUARY 2007 9

Design of High-Order Phase-Lock Loops

Alfonso Carlosena, Senior Member, IEEE, and Antonio Mànuel-Lázaro

Abstract—The analysis, and design of third-order, (and higher)

phase-locked loops (PLL) is difficult. This paper presents a novel
approach to overcome these difficulties by allowing high-order
loops to be viewed as a natural extension of lower order ones.
This is accomplished by adding nested first-order feedback loops
around a basic first-order loop filter. Our approach will also be
related to the concept of PLLs with aided acquisition. The model
presented has been implemented and tested in Simulink. Fig. 1. PLL block diagram.

Index Terms—Analog signal processing, feedback systems, loop

filters (LFs), phase-locked loops (PLLs).

I. INTRODUCTION

T HE exact analysis of third-order phase-locked loops

(PLLs), i.e., those including a second-order loop filter
(LF), is normally eluded because it is very complex. Even most
recent books on PLL limit themselves, at best, to calculating
-domain equations without giving any practical design guide-
lines [1], [2]. In these cases, iterative simulations or graphical Fig. 2. First-order loop-filter frequency response.
root locus analysis are used to tune the desired response and
deal with stability issues. A general practice is to approximate
the third-order response by a second-order one and proceed of instantaneous frequency with gain rads/(V s). As for the
with the well known design equations. The goal of this paper PD, its model depends on the implementation (multiplier, dig-
however, is to propose an alternative approach to the intuitive ital, etc.), but it is usually approximated by the phase difference
and analytic design of third-, and even fourth-order loops, as within a limited range, scaled by a gain . The LF is assumed
a natural extension of second-order PLL. The approach will linear, and thus the simplest case, apart from a trivial PLL with
also be seen as related to the extension of a conventional PLL no filter, is a first-order one. Thus, its most general transfer func-
(second order) with the so called “aided acquisition” loops [3]. tion, assuming unity dc gain, is
Our approach tries to combine a practical interest with a deeper
understanding of the PLL operation. The concepts shown here
are general, but of particular interest in applications where the (1)
PLL needs to be operated in a wide hold range, i.e., not a small
fraction of the free running frequency (FRF) of the oscillator,
Its bode plot is represented in Fig. 2 for . Design
such as in on-chip tuning applications [4], wideband signal
equations for this particular case can be found elsewhere, al-
generation detection, chirp radar signals or spread spectrum
though they are quite often buried by particular electrical pa-
clocking.
rameters dependent on the implementations of the filters (active,
passive, switched capacitor, etc.). Since dc filter gain is unity,
II. SECOND-ORDER PLL AND AIDED ACQUISITION LOOPS PLL gain is defined as .
Fig. 1 shows a typical model of an analog PLL including a In short, simple stability analysis shows that stability is guar-
phase detector (PD), an LF, and a voltage-controlled oscillator anteed if . An interesting case is when
(VCO). Signals and are input and output phases. VCO giving rise to a second-order Type II PLL. In this latter case,
is usually modeled by an integrator, since phase is the integral the zero must necessarily be finite, otherwise (a perfect inte-
grator) results in an unstable behavior. We note here that these
stability conditions are valid even when considering a nonlinear
Manuscript received May 15, 2006; revised June 7, 2006. This work was dependence for the PD [5] (i.e., a multiplier), but are not suffi-
supported in part by the Spanish “Dirección General de Investigación” under cient for switched PD, such as those found in charge pump and
Grant DPI2003-08637-C03. This paper was recommended by Associate Editor digital PLLs, where its time variant nature must be accounted
S. Callegari.
A. Carlosena is with the Universidad Pública de Navarra, Dpt. Electrical and for [6]–[8]. Design space of second-order loops is limited, since
Electronic Engineering, Campus de Arrosadia, E-31006 Pamplona, Navarra, there are few free parameters to control the rather complex be-
Spain (e-mail: [email protected]). havior. Tradeoffs are well known [1]–[3], [6] and for this reason
A. Mànuel-Lázaro is with the Universidad Politécnica de Cataluña, Centro
Tecnologico de Vilanova i la Geltrú, Avda. Victor Balaguer s/n, 08800 Vilanova
will not be looked at here.
i la Geltrú, Barcelona, Spain (e-mail: [email protected]). In an attempt to circumvent some of these problems, such as
Digital Object Identifier 10.1109/TCSII.2006.883205 increasing the hold-in range without changing the acquisition
1057-7130/$25.00 © 2007 IEEE
10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 1, JANUARY 2007

Fig. 5. Equivalent model to PLL in Fig. 4.

Fig. 3. PLL with aided acquisition loop.

Fig. 4. Model for an aided PLL. Fig. 6. Second-order loop-filter frequency response.

dynamics, aided acquisition loops have been proposed as an al- hop, the lower loop reacts and tries to correct the phase differ-
ternative. A possible model for such PLLs is shown in Fig. 3 ence in the same way as a conventional PLL (Fig. 1) would do.
[3]. The idea is to combine two feedback loops, in such a way If LF2 is also low pass, and has a long time constant, it will
that the (upper) only frequency detection (FD) loop provides filter out the fast variations at the differentiator output and error
the error signal when input and output frequencies are different. signal will remain almost unchanged at its dc value. As the
Once the two frequencies are close, and VCO input tends to frequency at VCO output gets closer to the input value, and
be constant, the PD loop begins to work, providing the neces- phase starts to be linear with time, the differentiator will give a
sary dc input to the VCO so that too. Then, the FD dc value proportional to the frequency (to the difference with the
loop gradually relinquishes the acquisition and becomes inac- FRF, actually), which will be transmitted at LF2 output, i.e, .
tive as the PD becomes more active [3]. The FD loop is somehow Then, signal , which initially produced the frequency change
“reset” in this process and ready for a new frequency hop and will reduce in the same amount. Thus, and under stationary con-
the hold-in range becomes infinite. The exact dynamics of the ditions, it is expected that tends to be zero giving rise to a
process will be dependent on the actual implementation of de- negligible phase error. The VCO input needed to sustain the ap-
tectors and LFs. propriate signal is produced by the upper loop, and the lower
Nonetheless, the distinction of phase and FD is somehow arti- loop relinquishes the acquisition. The above analysis indicates
ficial: since a PD implicitly contains the frequency information that operation of model in Fig. 3 is similar, in terms of the error
(the reverse is not true), a possible FD can be thought of as a signals produced by the two loops, to that in Fig. 4. This latter
PD followed by a differentiator. With this in mind, the concept model, though conceptually interesting, can be further simpli-
of aided acquisition will be revisited in the next section, without fied if one takes into consideration that the VCO can be modeled
resorting to separate Phase and FDs, giving rise to an alternative as an integrator. Then, integration by the VCO and the differen-
model for the PLL, which in turn will allow for a natural intro- tiator operation, comprising the scaling factor, cancel out giving
duction of higher order PLLs. the equivalent scheme shown in Fig. 5.
III. THIRD-ORDER PLLS Clearly, LF 2 can be now combined with LF 1 to give a single
LF. If LF 1 is of order one, as in (1), and LF 2 is also of order
To our view, the problem can be posed in terms of what the
one with a single pole at , i.e.,
functional dependence of the phase at the output of the PD is
like, how the frequency error information can be extracted from
it, and how they are combined to attain a given dynamics of the (2)
loop. Taking this into account, an aided acquisition loop could
be modeled as indicated in the Fig. 4, where the LF1 and LF2 we come up with a second-order LF and thus a third-order PLL.
are low-pass filters, and only a conventional PD is used. Differ- The global response of such filter, also known as Przedpelski
entiator represents derivative of the phase . Filter [9], is shown below, and its Bode plot represented in Fig. 6
Note that we do not claim this model is equivalent to that in
Fig. 3: Acquisition dynamics is a very complex process and a
nonlinear device such as a FD cannot be substituted by a linear
operator. In this sense architecture in Fig. 3 is more flexible and
can provide faster phase and frequency error signals resulting in (3)
a wider lock-in range. The resulting PLL is, not surprisingly, a third-order Type II
Operation of the above model can be described as follows. loop due to the additional pole at the origin introduced by LF2.
When a transient is produced at the input, because of a frequency It is well known that this pole is the minimum requirement
CARLOSENA AND MÀNUEL-LÁZARO: DESIGN OF HIGH ORDER PLLS 11

to allow the tracking of frequency hops with zero steady-state

phase error. The point to remark now is that we have shown
how a second-order PLL with the aided acquisition can be seen
as equivalent to a third-order, Type II PLL. In this process we
have gained some insight into the meaning of each one of the
time constants and signals into the circuit.
• On one side so that the transient of the loop
is similar to that of a second-order loop, but correcting af-
terwards the phase difference achieving the dynamics of a
third-order type II loop. In Section V, we will give prac-
tical guidelines to chose the ratio . Fig. 7. PLL with chirp tracking.
• Residual phase difference after a transient tends to be neg-
ligible within a time frame proportional to time constant
.
• Signal carries, in lock conditions, a value proportional
to .
• Additionally, stability conditions are very easy to check. If
we translate stability conditions given in [5] to our partic-
ular parameterization given by the separate loops, stability
is assured if

(4)

Note that in the case of a zero of LF 1 at infinity, first con- Fig. 8. third-order LF frequency response.
dition is automatically fulfilled. The second inequality is
also fulfilled if the second-order loop was stable, and the
added feedback has, as suggested, a longer time constant. If the filter LF3 is of first-order too, with cut-off frequency
We must however recall that above conditions are based on , then, the overall performance of the two loops can be as-
a continuous time analysis. For sampled PLL, remarkably similated to a single LF whose response is now
charge pump PLLs, additional stability conditions are ob-
tained based on Z-domain analysis. Charge pump PLLs are
essentially Type II PLLs of order 2 or 3, and thus stability
rules in terms of electrical variables, found elsewhere [6],
[7], can be easily translated to our parameters in (3) (5)
• In most practical cases, LF1 and LF2 are merged into a
single filter. For instance, in a charge pump PD LF is an Its bode plot is represented in Fig. 8 where the time constant
impedance. However, in some applications it might be in- of the new filter, , is higher than . This condition is
teresting to keep the two stages separate in order to control however not needed for the correct operation of the loop since,
both time constants independently, to dynamically modify according to (5), the two poles can be exchanged.
the filter order, or to have available error signals to tune The resulting filter is a generalization to third-order of the
other components of the loop [4]. order two LF suggested by Gardner [6], giving rise to a Type
III PLL of fourth order! (Gardner’s filter can be recovered but
just making ). The double pole at the origin in the
filter is an indication that the PLL is able to follow frequency
IV. HIGHER ORDER PLLS chirps with zero steady-state phase error, as originally suggested
for the Gardner’s filter. Note that typical fourth-order PLLs re-
The concept of introducing an additional feedback loop, can ported in most papers are not of this kind: the additional pole is
be once more used to detect, and correct, a typical situation not at the origin and its role is to reduce phase noise [10]. Sta-
where the input signal is a chirp whose frequency varies lin- bility conditions for a fourth-order loop cannot be analytically
early with time, either intentionally or due to Doppler effect. obtained and approximations have not been reported to the best
The modification in the loop studied so far is only able to correct of our knowledge. However, it can be expected that, in our par-
the phase error when the input frequency is constant (possibly ticular design case, the conditions for the third-order loop are
after a frequency step) but not to follow a chirp while keeping still valid.
zero phase error. One way to detect a chirp input in the model
of Fig. 5 is to compare the VCO input and the correction intro- V. SIMULATION RESULTS
duced by LF2. A constant value is an indication of the situation A Simulink model, which allows an evaluation of how the
described. Such a difference signal can be used with the appro- various feedback loops affect the operation of the PLL, and the
priate delay to further correct the VCO input and minimize the evolution of the signals involved, was implemented. We will
phase error. The proposed modification is shown in the Fig. 7. proceed by analyzing, first the operation of the second-order
12 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 1, JANUARY 2007

TABLE I
PLL PARAMETERS (FREQUENCIES IN rads/sec)

Fig. 10. VCO frequency with increasing PLL order.

Fig. 9. Second-order PLL transient response. Fig. 11. LF1 output with increasing PLL order.

loop and then appraise how it is affected by the introduction of transient and stays steady. When input ramps-up output follows
the new loops. This will mimic the design procedure to be fol- the chirp at the beginning but unlocks when frequency is ap-
lowed, regardless of whether the LF is implemented in a com- proximately , as initially predicted.
pact manner in the final design (just plug-in the LF parameters Taking this result as a reference and using the same input
from the design), or with the explicit feedback loops. signal, we will repeat a similar simulation but consecutively
connecting LF2 at instant 5 miliseconds, and LF3 at 20 millisec-
A. Transient Analysis onds. We can clearly see in Fig. 10 how now the PLL is able to
The parameters chosen for the PLL are as shown in Table I. track the input frequency in its successive ramps and steady pe-
Assuming that only LF1 is active, and the other disconnected, riods. However, what is really informative about the role of each
the expected behavior of the PLL can be summarized in the additional loop, and in turn the increase of the PLL order and
parameters also provided in Table I. PD has been modeled as type, is to see the evolution at the LF1 output, which is nothing
a perfect analog multiplier, while VCO is assumed ideal. but a filtered version of the phase error. This is shown in Fig. 11.
We have chosen an under-damped behavior to make tran- After the first transient at , signal tends to a steady dc
sients under abrupt frequency changes more apparent. Then, value, as a clear indication of a phase difference between input
Lock-in Range is about 30% of the FRF and Hold Range is and output signals. When LF2 is connected at instant ms,
about 60% of FRF [6]. By introducing the additional feed- PLL becomes third-order, but the new transient (equivalent to a
back loops, whose time constants are five times longer, we may frequency step) is still basically determined by LF1 parameters.
expect the hold-in to increase, and the remaining parameters to Now, error tends to a steady zero dc value, which indicates zero
remain substantially unchanged. Another significant difference phase error and thus an infinite hold-in range. The error signal
is that phase error will tend to be zero for a constant input fre- needed to achieve the correct frequency is self sustained by the
quency (when LF2 is working) and also for a linear chirp (when own filter LF2 (see Figs. 5 or 7). Once the frequency starts to
LF3 is working too). In a practical situation the VCO will limit ramp-up at instant 10 ms, the PLL is able to follow, but, in order
the operation range of the PLL, but here we are only interested to keep up the pace, a phase error, proportional to the slope, is
in showing the influence of the LF. needed. This is clear from to 15 ms. Then, from instant
The test signal employed in all examples is a sinusoid whose to 20-ms input frequency does not change and the PLL is
initial frequency is 72 krad/sec ( , which is within again able to recover a zero phase error. By the way, the transient
acquisition range), stays stable for 10 milliseconds, and then fol- duration is determined by the time constant of LF2. At instant
lows successive intervals of ramps-up and constant frequency of 20 ms, filter LF3 is connected at a time when a new ramp-up
5-ms duration (see Fig. 10). Under these conditions, in Fig. 9 we starts. After a transient, the PLL (that is now a fourth order), is
show the resulting instantaneous frequency of the PLL output, able not only to track the input frequency, but also to reduce the
when only LF1 is active (second-order Type I PLL). The system phase error to zero. The delay is proportional to the sum of the
is able to track the input frequency after a clearly under-damped two time constants of LF2 and LF3.
CARLOSENA AND MÀNUEL-LÁZARO: DESIGN OF HIGH ORDER PLLS 13

Fig. 12. Transient response for second- and fourth-order PLLs.

Fig. 13. Loop responses for second-, third-, and fourth-order PLLs.

In the next graph, Fig. 12, we compare the response, from

, of the second- and fourth-order loops. The initial tran- can be reduced in a 20% if a Bessel approximation was taken as
sient (see Figure inset) shows higher locking peaking and lower starting point. Interestingly, these figures are similar if LF1 was
damping factor in the fourth-order case, which also contributes a third-order filter. In Fig. 13 we show how the Phase Gain fre-
to an observed increase in the acquisition range. We note that the quency response of the PLL is changed when introducing LF2
time constants of LF2 and LF3 are only five times that of LF1. If and LF3, with , (i.e., a ratio of ten).
the factor were higher, both responses would become very close,
supporting the prediction that third- and fourth-order loops have VI. DISCUSSION OF RESULTS AND CONCLUSIONS
a locking transient behavior and stability requirements close to
that of the second-order ones [6]. We have presented high-order PLLs as a natural extension of
The added feedback loops in the fourth order are of relevance lower order ones, by the addition of feedback loops. The aim
when frequency excursions are large, to increase the hold-in of these loops is to reduce phase error under steady frequency
range, as seen in the evolution from millisecond 10 on. We note at the input, and chirp variations. In this way, the PLL behavior
that the curve obtained for the third-order PLL is almost indis- can be tuned by first designing the transient and steady state of
tinguishable from that of fourth, and thus has not been included a second-order PLL, and then taking care of the working opera-
in the Figure. They are different only in terms of phase error tion under steady frequency (third-order) and frequency ramps
(Fig. 11). (fourth order). This model can be used, regardless of whether
implementation contains separated loops or not, to gain insight
B. Steady State Analysis into the system’s behavior. The idea of using feedback loops in
the LF, has also been related to the concept of aided acquisition.
Not only transient behavior is important but also stationary A Simulink model has been developed to demonstrate the con-
response in terms of how filtering properties of the PLL preserve cepts presented here.
when the order is increased. This is particularly important for
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