Electronic Devices

Lecture 24
28-10-2022
Prof. Ramesha C K

BITS Pilani, K K Birla Goa Campus

 Classification of Transistors

Transistor

BJT Field Effect Transistor

JFET MOSFET
NPN PNP

Depletion Depletion Enhancement

N-Channel P-Channel N-Channel P-Channel N-Channel P-Channel

BITS Pilani, K K Birla Goa Campus

 Gate Control

Figure 6—5
Effects of a negative gate bias:
(a) increase of depletion region widths with VG negative;
(b) family of current–voltage curves for the channels as VG is varied.
 Pinch off Voltage Calculation

Figure 6—6
Simplified diagram of the channel with definitions of dimensions and differential
volume for calculations.
 Pinch-off Voltage Calculation
1/ 2 1/ 2
 2 (V0 − V )  N a + N d   2 (V0 − V )  1 1 
W =   =  + 
 q  Na Nd   q  N a N d 
kT Na kT Na Nd
V0 = ln 2 = ln
q ni / N d q ni2

Assume that V = VGD < 0, V0 << -VGD

1
 2 ( −VGD )  2
W ( x = L) =  
 qN d 
- Pinch-off occurs at the drain end of the channel when :
h (x = L) = a –W (x = L) = 0 → W (x=L) = a
-Pinch-off Voltage:
1 1

 2 ( −VGD )  2  2 (V p )  2

  =a   =a
 qN d   qN d 

qa 2 N d
Vp =
2
-If Vp = - VGD at pinch-off → Vp = -VGD (pinch-off) = -VG +VD
 I – V Characteristics
Based on Fig. 6-6, Channel length = L & Channel depth = Z :
* Differential Volume of the neutral channel regions = dV = Z 2h(x) dx &
dx
dR = 
Z 2h( x )
* Since ID is constant along the channel, ID is related to dVx (the differential
voltage change in the element) as follows:
dx Z 2h( x) dVx
dVx = I D dR = I D ID = (a)
Z 2h( x)  dx
* h(x) [half-width of the channel at point x] depends on –VGx [local reverse bias
between gate and channel]
1
1  2  1

 2 (−VGx ) 
2  (−VGx )    Vx − VG  
2
h( x ) = a − W ( x ) = a −   = a − a 2  = a 1 −   (b)

 qNd   ( qa N d )    Vp 

 2 
 I – V Characteristics

Z 2h( x) dVx
(a) I D =
 dx 1
1   2
 1

 2 (−VGx )  2  (−VGx )    Vx − VG  
2

(b) h( x) = a − W ( x) = a −   = a − a 2  = a 1 −   
 qN  ( qa N d  V
d
)   p  
 2 
Substitute (b) into (a)& Then integrate both sides !
VD L

2Za   Vx − VG 
1
2



0
dVx =
0
dx 
1− 
   V   dVx = I D dx
  p  
Valid only up to pinch-off point !!!
V 2  VG 
3/ 2
2  VD − VG 
3/ 2

I D = G0V p  +  −
D
 −    * ** G0 = 2aZ / L
 VP 3  VP  3  VP  
- At pinch-off, VD – VG =VP
- Saturation current remains constant at its value at pinch-off
V 2  VG 
3/ 2
2
I D ( sat.) = G0V p  +  −  − 
D

 VP 3  VP  3

VG 2  V 3 / 2 1 
= G0V p  +  − G  +  VD VG
where = 1+
VP 3  VP  3
 VP VP

- Mutual conductance (gm) at saturation :

I D ( sat.)   V 
1/ 2

g m ( sat.) = = G0 1 −  − G  
VG   VP  
2
 VG 
I D ( sat )  I DSS 1 +  , VG is negative
 VP 
 GaAs MESFET (Metal Semiconductor Field Effect Transistor)

Ohmic contacts for source & drain (Au-Ge)

Schottky contact for gate (Al)

(Epitaxially grown & Higher electron mobility)

Channel formation in n-GaAs

(non-conducting)
Etched area for isolation
Reverse-biasing the Schottky gate (barrier) result in the
depletion of the channel region (i.e., n-GaAs region)

Figure 6—7
GaAs MESFET formed on an n-type GaAs layer grown epitaxially on a semi-insulating substrate.
Common metals for the Schottky gate in GaAs are AI or alloys of Ti, W, and Au. The ohmic source and
drain contacts may be an alloy of Au and Ge (Au-Ge). In this example the device is isolated from
others on the same chip by etching through the n region to the semi-insulating substrate.
 High Electron Mobility Transistor (HEMT)
Issue: High transconductance is obtained from the high channel conductivity that can be increased by
increasing the impurity doping in the channel (i.e., carrier concentration). Unfortunately, the increased
doping causes increased scattering by the ionized impurities, leading to a degradation of mobility.

Solution: GaAs layer is spatially separated from the ionized impurities in AlGaAs providing the free
electrons. Electrons generated by the donors in AlGaAs diffuse into the GaAs layer. Ionized impurity
scattering is greatly reduced simply due to the separation of the electrons from ionized donors. This
results in a very high mobility, thus high device performance.

Figure 6—8
(a) Simplified view of modulation doping, showing only the conduction band. Electrons in the donor-doped AIGaAs fall
into the GaAs potential well and become trapped. As a result, the undoped GaAs becomes n-type, without the
scattering by ionized donors which is typical of bulk n-type material. (b) Use of a single AlGaAs/GaAs heterojunction to
trap electrons in the undoped GaAs. The thin sheet of charge due to free electrons at the interface forms a two-
dimensional electron gas (2-DEG), which can be exploited in HEMT devices. (MODFET)
 Effects of electron velocity saturation at high electric fields
(Short channel effects)

Piecewise-linear approximation !

(i) Constant mobility (µ) below critical field

(ii) Constant saturation velocity (Vs) above critical field

Figure 6—9
(a) approximations to the saturation of drift velocity with increasing field;
(b) drain current—voltage characteristics for the saturated velocity case, showing
almost equally spaced curves with increasing gate voltage.
Depletion-Enhancement type MOSFET (DE-MOSFET)

13
Depletion-Enhancement type MOSFET (DE-MOSFET) –
under biased condition

14
DE-MOSFET- Drain Characteristics

15
16
Enhancement type MOSFET

17
An enhancement-type n-channel MOSFET
(1) Threshold Voltage (VT ) : Minimum gate voltage required to induce the conducting channel
(2) Enhancement mode transistor : “normally off” with zero gate bias, operates by applying gate
voltage large enough to induce a conducting channel.
(3) Depletion mode transistor : “normally on” with zero gate bias, a negative gate voltage is required
to turn the device off (n- channel transistor case).
(4) Self-aligned structure/Process
(5) LOCOS (Local Oxidation of Silicon)
(6) Work function
n-channel MOSFET cross-sections under different operating conditions

(a) linear region for VG > VT and VD < (VG - VT);

(b) onset of saturation at pinch-off, VG > VT and VD = (VG - VT);
(c) strong saturation, VG > VT and VD > (VG - VT ).
Band Diagram for Ideal MOS Structure
p-type Si (a) equilibrium;
(b) negative voltage
causes hole
accumulation in the
p-type semiconductor;
(c) positive voltage
depletes holes from
the semiconductor
surface:
(d) a larger positive
voltage causes
inversion:
a “n-type” layer
at the semiconductor
surface.

1 dEi
 ( x) =
q dx

p = ni e ( Ei − EF ) / kT
kT N a
 s (inv.) = 2 F = 2 ln
q ni