VLSI Testing

積體電路測試

Memory Testing

Professor James Chien-Mo Li 李建模

Lab. of Dependable Systems
Graduate Institute of Electronics Engineering
National Taiwan University

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 Course Roadmap (Design Topics)

DFT Built-in Self Test

Test Compression Memory Testing

SOC Testing FunctionTests

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 Why Am I Learning This?
 Testing memory is important

Because many memories are needed in modern designs
 Memory testing is very different from logic testing

“The advantage of a bad memory is that

one enjoys several times the same good
things for the first time”

( Friedrich Nietzsche )
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 Outline
 Introduction
 Memory Fault Models
 Memory Test Algorithms
 Memory Fault Simulation (*not in exam)
 Memory Test Generation (*not in exam)
 Memory BIST (*not in exam)

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 Memory Testing
 Testing of memory is crucial for quality. Research started 1960’s
Memory accounts for ~30% of semiconductor market (2019)
 Popular memory test items
 Off-chip tests
 DC parametric test: e.g. leakage current, output voltage level
 AC parametric test: e.g. rise time, fall time
 Functional test: e.g. march test (see 16.3)
 Retention test: measure retention time of DRAM
 Reliability test (Burn-in)
 On-chip tests
 Error Detection and Correction (EDAC): on-line testing
 Built-in Self Test (BIST)
 Built-in Self Diagnosis & Repair (BISDR)
 BIST important for System-on-chip (SOC) with embedded memories

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 Typical Memory Test Flow

Laser
Wafer Wafer Sort Packaging
Repair

Burn-In
Final Test Post-BI Test Pre-BI Test
(BI)

Visual
Marking Shipping
Inspection
QA Sample
Test

Memory Diagnosis/Repair can Improve Yield

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 Types of Memories
type area speed retention application test
method
SRAM largest fastest as long embedded SRAM BIST
6T <1ns as power cache, registers
DRAM medium medium < sec. embedded DRAM BIST/
1T+1C ~10ns ATE
on-board memory ATE
Flash smallest slowest years SSD, USB drive ATE
1T ~100ms

Floating Gate Transistor

SRAM cell [wikipedia] DRAM cell [wikipedia]

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 DRAM Functional Model

(BA Fig. 9.4)

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 Outline
 Introduction
 Memory Fault Models (focus on RAM)
 Static faults
 Single cell fault, Double cell fault, Address-decoder fault
 Dynamic faults
 Recovery fault, Retention fault
 Memory Test Algorithms
 Memory Fault Simulation (*not in exam)
 Memory Test Generation (*not in exam)
 Memory BIST (*not in exam)

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 RAM Fault Models
 Functional testing is commonly used for memories

Scan testing for logic is not applicable to memory. (Why? FFT)
 Functional fault models are behavior model for faulty memories
 based on real defects, not imagination
 Popular RAM functional fault models
1. Static fault models: faulty behavior does NOT change with time
 single cell, double cell, address decoder
2. Dynamic fault models: faulty behavior changes with time
 recovery, data retention

 NOTE: many other RAM fault models (neighborhood pattern sensitive faults …)

Different Memories Need Different Fault Models

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 RAM Fault Models (1) – single cell
 Stuck-At Fault (SAF)

a cell is always 0, SA0
 a cell is always 1, SA1
 Stuck-Open Fault (SOF)
 a cell cannot be accessed due to broken wire
 Transition Fault (TF)
 a cell fails to
 Rise from 0 to 1 < / 0>
 Fall from 1 to 0 < / 1>

NOTATION: <S/F>: a fault in a cell [van de Goor 91]

 S is value or operation activating fault , S{0, 1, , , ↨ ,}
  is rising;  is falling; ↨ is either  or ;  means any condition
 F is faulty value of cell , F{0,1, ↨}
 ↨ is complement

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 RAM Fault Models (2) – double cell
 Coupling Fault (CF): Victim cell is affected by Aggressor cell
 1.State Coupling Fault (CFst)
 if aggressor cell is in given state, victim cell is forced to 0 or 1
 4 types: <0; 0/1> or <0; 1/0> or <1; 1/0> or <1; 0/1>
 2.Inversion Coupling Fault (CFin)
 if aggressor cell rise/fall, victim cell is complemented
 2 types: <↑ ; /↨ > or < ↓ ; /↨ >
 3.Idempotent Coupling Fault (CFid)
 if aggressor cell rise/fall, victim cell is forced to 0 or 1
 4 types: < ↑; 0/1> or < ↑; 1/0> or < ↓ ; 0/1 > or < ↓ ; 1/0 >

NOTATION: <S1; S2/F> faults in 2 cells

 S1 is value or operation activating fault in aggressor
 S2 is value or operation activating fault in victim
 F is faulty value of victim
A V

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 CF Examples
CFst<0,0/1> CFid<; 0/1> CFin<;  /↕ >
addr content*

A 0 A 0 A 0 A 0 A 0
V 0 V 0 V 1 V 0 V 1
do write 1 write 1 write 1 write 1
nothing to A to A to A to A
addr content

A 0 A 1 A 1 A 1 A 1

V 0/1 V 0/1 V 1 V 0/1 V 1/0

read V read V read V read V read V

detected detected not detected detected detected

*typically many bits in one address
but only one bit here for illustration

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 QUIZ
Q: Consider CFin<, ↕ >. Fill in values for two cases.
Can we detect faults in both cases?

ad content ad content
dr dr

ANS: A 1 V 1
V 1 A 1
write 0 write 0
to A to V
ad content ad content
dr dr

A 0 V 0
V ? A ?
read read
V=? A=?

Address Order Matters

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 RAM Fault Models (3) – AF
 Address-Decoder Fault (AF) Four faulty behavior:
1. Given a certain address, no cell will be accessed
2. A certain cell is never accessed by any address
3. A certain cell can be accessed by multiple addresses
4. Given a certain address, multiple cells are accessed
 AND-type
 OR-type AF between A1 and A2
addr* content

read A2 A2 0 output =?

… …
A1 1

*ascending address order denoted as . see 16.3

Only Consider #4 AF
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 AF Examples
OR-type AF AND-type AF
between A1 and A2 between A1 and A2

read read
A2 1 A2 1
A2 =1 A2 =1/0
… … … …
A1 0 read A1 0 read
A1 =0/1 A1 =0

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 QUIZ
Q1: Given OR-type AF between A1 and A2. Fault detected?

… … … … … …
read write 1 read
A2 0 A1 =? A2 0 to A1 A2 0 A2 =?

… … … … … …
A1 0 A1 0 A1 1

Q2: Given AND-type AF. Find a test to detect fault.

… … … … … …
read write ? read
A2 1 A1 =? A2 1 to A1 A2 1 A2 =?

… … … … … …
A1 1 A1 1 A1 ?

AND/OR AF Need OppositeVLSITest Data

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 RAM Fault Models (4) – dynamic faults
 Data Retention Fault (DRF): data changed after a certain time

DRAM
1. Charge leakage loose data in capacitor
2. Refresh logic fails to refresh correctly
 SRAM
 Defective pull-up device inducing excessive leakage current
which changes the state of cell
 Sense amplifier recovery fault
 Sense amp. saturated after reading/writing a long string of 0 or 1
 Write recovery fault
 A write followed by a read/write at a different location results in
reading or writing at the same location due to slow address
decoder

Time Consuming to Test Dynamic Faults

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 Summary
 Memory test important. Good diagnosis/repair can improve yield
 Popular RAM functional fault models

Static fault models
 Single cell: Stuck-at (SAF), Stuck-open (SOF), Transition (TF)
 Double cell coupling faults: CFin, CFid, CFst
 Address decoder fault (AF): AND-type OR-type
 Dynamic fault models
 Data retention faults (DRF). Recovery faults
 Fault model must be realistic
 Different memories need different fault models

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 FFT
 Q1: Scan testing for logic is not applicable to memory.
 Why no scan?

 Q2: AF has four faulty behavior.

 We only consider #4. The others are easy to test, why?
1. Given a certain address, no cell will be accessed
2. A certain cell is never accessed by any address
3. A certain cell can be accessed by multiple addresses
4. Given a certain address, multiple cells are accessed

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