5

CHAPTER
OBJECTIVES
Processor Basics

This chapter discusses about architecture, organization and functioning of

processors. Af
completion of this chapter, the reader would know about
registers, fiags
UFundamental architectural features of processors, e.g., bus structure,
and so on.
O Functions of program counters, stack and interrupts.
OInstruction fetch, decoding and execution details with timing diagrams.
OArchitectural details of Intel 8085 and 8086 microprocessors.
O Several architectural features of Intel 8051 microcontroller.
O Difference between RISC and CISC architectures.
OImportant features of more advanced processors like Intel 80386 and Pentium 4.

5.1 INTRODUCTION
We have already discussed in Chapter 1that processor or
the heart of any computer. This had been valid starting from microprocessor or central processing unit (CPU)=
the time of ISA machine by Von Neumann (S
tion 1.2.2). Modern processors are mostly single-chip devices
tasks assigned to them. However, depending upon the capable of overseeing and executing all relak
in their details. In this chapter, we shall manufacturer and the model. there is a wide variati
take a closer look at these processors in
about three popular and vintage processors (8085, general, and then diseu
advanced processors (80386 and Pentium 4). We are 8086 and 8051). Finally, we shall also consider two
are the products from Intel. restricting our discussions within those processosu
Details of afew more advanced
processors are presented in the appendices.
5.2
PROCESSOR
Externally, any processor is a ARCHITECTURE AND ORGANIZATIO
pins attached with this ceramic or plastic package several meeta
receive power supply
(integrated
package. These pins are provided to circuit or IC) with Signalsat
of these pins,
their requirements for the processor. communicate different types of ofen
well as time-wise signal names and Manufacturer' s the details
data sheets givecharacteristies)
(known as AC characteristics, both electrical (known as DC
characteristics).
 Processor Basics 95
62.1 InternalArchitecture
sgeneral internal
architecture of any proccssor is
logic unit (ALU), which performs all arithmetic and shown Figure 5.1. Apart from the arithmetic
in
general purpose registers for various storage and logical operations, cvery processor offers a set of
different arithmetic and logical operations, which opcrations, Its status register accommodates the status
program counter holds the address of next
might be necessary for conditional
branching Its
otack pointer indicates the address of the instruction word to be fetched from external rnernory. The
stack-top, which we shall discuss a little latet.

General purpose
registers Data bus

Control
ALU
unit Control bus bus
System
and
Oscillator
Timings
Status register

Program counter Address bus

Stack pointer
ProcesSor
Figure 5.1 General internal architecture of a
processor
Two more architectural features of any processor are indicated in Figure 5.1. They are
and, oscillator and timing module. The control control unit
unit is responsible for generating all control signals
general working of the processor. This is achieved by the and
which is maintained by the oscillator unit. instructions with the help of internal clock,

5.2.2 Basic Function

These architectural details of a processor are meant for
ber that hardware and software must be dealt executing a software. We should always remem
hardware or only software concurrently for any computer or any procesSor. Only
would not be able to achieve any
processor is to fetch, decode and execute instructions as long astangible
it is
outcome. The basic duty of any
a microcontroller (see Section 5.9 of this powered on (Figure 5.2). Unless it is
chapter for 8051 microcontroller), these instructions are avail
able outside the physical boundary of the processor, within
electrically connected with the processor through a bunch ofmemory chips (1Cs). These memory chips are
wires, designated as the bus.

Fetch instruction Decode instruction Execute instruction

Figure 5.2 Basic function of any
processor
96 Computer Architecture and Organization
necessary for the
Apart from fetching the opcode of executable instructions, sometimes it might be
memory, if indicated so by the ongoing instrucion.
processor to load or store operands in the external divertcd to another sequence
due to Con-
Generally, the operation of a processor is sequential, which is
venual
from subroutines,or to respondagainst any
ditional branching,subroutine calls and returning
external interrupt signal.
Communication
5.2.3 Peripheral Devices and External
proCeSsor to De runc
not the only category of peripheral devices necessary for a used to Suppon
Memory devices are large number of peripheral devices are
that a
uonal. Later in this chapter, we
shall see (non-memory devices) are, generally.
per the system requirements. These devices memory devices, these I/Odevices
duues, as
t /Odevices. Note that. iust like
rererred as lnputOutput devices or through the bus.
are also connected (or interfaced) with the processorThey are (Figure 5.1):
types of bus.
Every processor offers three major
Address bus
OData bus and
DControl bus.
of the processo.
data bus is bi-directional, as data must come in and also go out addres
Out of these three bus,
requirements. Address bus is always unidirectional and it carries
depending upon the specific devices around it, memory and I/O. Most of the control
signalk
signals from the processor to all external presented in
Schematically, a generic processor's external signals are
alsomove out of the processor.
Figure 5.3.

DC + V power in

Vcc
0R
Clock Address Address signals to memory and /Odevices
S
Reset S Data Data signals from/to memory and /Odevices
CE

Interrupt Mem read Get data from a memory device

O
PRMem write Store data within a memory device
Status
VO read Get data from an WO device
I/O write Store data within an /O device
GND

Reference ground multijp

Figure 5.3 External signals of a generic having
signals is shown by double lined arrow) processor (Note: the bus
 Processor Basics 97
5.2.4 Address Bus and
The width of address bus or number of
Addressing
address lines available from any
mum nemory size handling processor indicates its fnax1-
capability. The
might be) addressable by n address lines is 2".number
of memory
locations (hytes or
address 2o or 64K locations (1 K= 2" Therefore, if the processor offers 16 words as the case
= 1,024). If it is address lines then
address 220 or 1M locations and so on offering 20 addrecss lines then it can
Tn Chapter 2 (Section
2.3.2), we have already discussed how the
loeired data with any memory or O address bus heips in locat1ng any
A1 of Chapter 3) inside the device. These address signals are decoded by a decoder (Section
sions explaining these operationsmemory or I/O device to target the desired
are not repeated here. However, for location. Therefore. discus
these details are explained through Figure the purpose of ready reference.
chown, which would be illustrated in Figure5.4.5.5,Note that in this diagram data paths for data
in Section 5.2.5. flow are not

Memory Device
Data
Data
processor

lines Data
from Data
select
signals Data
Location Data
n to 2
Address Data
Decoder
gn Data
Data
-
n Data

Data
Data
Data

Figure 5.4 Addressing of memory location by

the processor
5.2.5 Data Bus and Data Flow
Control
The width of data bus of any processor
indicates its simultaneous handling capability of the
number of bits. Generally, a processor is designated by its data
maximum
Sor is capable of communicating 8-bit of data at bus width. For example, an 8-bit proces
the same time or having an 8-bit data bus.
10-bit prOcessor has 16parallel data lines for data Similarly, a
Ine iow of data is bi-directional, depending upon communications.
rom or writing into the device (memory or LVO). This whether the processor is interested in reading
S Control signals (read and write). Depending upon intension of the processor is expressed through
O UO) enables the appropriate 3-state buffer to this indication (read or write), the device (memory
allow
aready selected byaddress signals. The identical type ofthe flow of data signals from the data location
u nits data bus. This is illustrated through Figure 5.5, 3-state buffers is also present at the proceSsor
DO-D7 represents the data bus, interfaced with the using 1-byte (8-bits) of storage area. Note that
processor. Eight flip-flops are for storage of data
 98 Computer Architecture and Organization

(8-bits) and at the input and output of each flip-lop. tri-state buffers are provided, whose contro
are connected in parallel. The location-select signal from the decoder within the memorye ( in
The clock signal acts
Figure 5,4) along with memory read or memory write signal cnablc thesC buffers.
in conjunction with memory write and selectsignals for the storage operation.
DO
DO D O
FIF

D1
D1
F/F

D2
D2 DO
F/F

D3
D3 D
F/F

D4
DQ
D4
F/F

D5
D5 D Q
F/F

Location select line D Q D6

D6
(from decoder) F/F
Memory write
D Q D7
D7
F/F

Clock

Memory read

Figure 5.5 Dataflow mechanism between memory and processor

In Figure 5.5, the reader should note that although separate lines indicate input-to and output-from
the tri-state buffers, the designation for any pair of buffers is the same, i.e., either both are D0 or both
are DI.Externally, these data line pairs are connected together to form abus of 8data lines, i.e, D0-D.
5.2.6 Control Bus
Number and functions of control signals, constituting the control bus varies widely with the processoris
However, two of its important signals are READ and WRTE. Condition of these control signals inae
whether the present operation, intended by the processor is expecting the data in (READ) or sendingth
data out (WRITE). As the processor is to interact with two types of devices, memory and VO, in generd
th
four read/write signals are offered, as shown in Figure 5.3. Afew status signals are also available from
name
processor, apart from power input signals. Two more input signals are essential for all processors,
processos
clock and reset. Apart from these, afew external interrupt input all
The purpose of all these signals is to execute any signals are also pprovided in ofindivid1s
program. The programs are composed during
instructions. shall now discuss how this program execution is
We processor
its operational stage. implemented bythe
 Processor Basics 99
itr
6.3 PROCESSOR OPERATION
os mentioned in the Section 5.2, the job of the processor is to execute programs, which are
composed of multiple instructions. At this point, we should remember that instructions cxecutable by
eprocessor, are always in the machine code. Programs devcloped with high level Welanguage
instructions are first changed to this machine code, understandable by thc processor.
(HLL)
shall elaborate
his point further in Chapter l1, where we would discuss about operating system. At present, we should
knowthat, in general, these machine code instructions are extremely primitive and simple, cg.
nCopya data byte from external memory to internal register or vice versa.
n Add two numbers available within the processor registers.
nIfthe result of subtraction is zero, then skip next three (or three thousand three hundred thirty
three)instructions.
These instructions must be present in binary form within the memory of the system.
5.3.1 Instruction Cycle
To execute any type of instruction including those that are cited above, the processor should perform
the following steps
DFetch
ODecode
DExecute.
Combination of these three steps is known as an instruction cycle. A flowchart of simplified form of
instruction cycle for a generic processor is shown in Figure 5.6.

Instruction
fetch

Instruction
decode

Operand Yes Fetch

fetch operand
needed

No

Instruction
execute

Store
result

Figure 5.6 Flowchart for simplified instruction cycle

 100 Computer Architecture and Organization

It may be observed from the flowchart that after fetching the instruction in the forrm of its opcode and
decoding it, the processor checksfor any eventual operand fetch, which might be nccessary for some (not tor
all) instructions. If found necessary, then the operand is fetched from memory and then the instruction 1s exe
cuted. Finally, the result of the instruction is stored and the whole cycle is repeated. At this point, the reader
may ask aquestion why this is designated as asimplified instruction cycle? The answer is, we are avoding
many other details related with the instruction cycle, e.g.,checking for any interrupt signal or looking tor any
direct memory access (DMA) request and so on. At a later stage, we shall consider all these details of the
instruction cycle.We shall now discuSS about the details of these three stages and some more related aspects,.
5.3.2 Instruction Fetch
The first step, as indicated before,is to fetch the instruction byte(s) from external memory. lhis external
memory is avast area containing many bytes of instructions. Therefore, the processor must pin-poitE
the correct location of this large memory area to extract the target byte.
It was already indicated that every memory location (byte in majority of cases) has a unique binary
address (refer Figure 5.4). After receiving this address, the duty of the memory device is to decode the
address to locate the target byte and place it on the data bus, so that the content of that address is avai.
able for the processor (Figure 5.5).
Address from prOcessor
(multiple bits) Content of address bus
X
Memory READ signal from processor
(active low)
Data from memory device to processor
(multiple bits) Content of daa bus
Processor reads from data bus at this instant of time
Figure 5.7 Timing diagram for instruction fetch
Therefore, for the purpose of instruction fetch, the processor places an
binary information, on the address bus. address, composed of multiplebis
its control bus. When these signals reach Simultaneously, processor also sends a memory read signal thu
the
the memory device, the data are sent to the
bythe memory device.
Schematically, this transaction is depicted in Figure 5.7, processor automatacs
gram. Observe from Figure 5.7 that data must be which is
to high. Address signals, valid (stable) when the memory read known as timingt
generated by the signal goes fron
One question may arise here that processor, are stable at this stage to ensure a valid data trans
control bus,the correct device would pay how, out of so many devices
attention to the
interfaced with address, dat
would
<000,remain silent? The answer is, every device has a processor's demand and that the other
chip select input
(generally, designaleu as

KHOU
Generally, for active
low signals, the
to high. In the
case of active high transactions are carried out when it switches fromlow
signals, the process occurs at the time when the signal
switches from high to low. The reader
may verify these from
different timing diagrams.
 Processor Basics 101

Cand if this input is not activated, the device does not react with the system bus
communications.
Using a part of the address lines and a suitable decoder (we have studied this in Chapter 3), the proces-
ofivates only one device during any communication and that solves the problem. This technique is
nas address decoding and deviceselection. A processor is assisted with a memory decoder andan
Odecoder to target the correct device, which is of current interest.
5.3.3 Instruction Decode
Afer receiving the instruction code bytewithin itself, the processor becomes busy in understanding it
(what to do?). This part is known as instruction decode, carried out within the processor itself. After
the completion of instruction decoding, the processor knows whether to fetch operands from external
memory or to increment a register by one or tostore aregister content in external memory location.
This instruction decoding may be implemented through hardware, in somewhat a similar way as we
have implemented it in Solved Example 3.3 of Chapter 3 (ALUdesign problem). Instruction decoding
may also be implemented through software, known as micro-programming. This demands a miniature
processor within the processor itself, completely devoted for instruction decoding and its execution. We
shall discuss more about this aspect in Chapters 9 and 10.
5.3.4 Instruction Execute
This is the last and final phase of an instruction's execution. Depending upon the instruction, one or
several operations are implemented by the processor. Once this part is complete, the processor looks
forward for the next instruction fetch-decode-execute, and the process continues.
5.3.5 Machine Cycle and T-states
An instruction cycle has one or more machine cycles and every machine cycle is composed of several
T-states. These points need some elaboration.
A machine cycle is the step or time-slice during which l1-byte (or one word) of data are transacted
between the processor and some external device. Generally, this external device is the memory device.
However, in exceptional cases it might be an I/O device also. To transact 1-byte of information, one
machine cycle must be executed by the processor. In Figure 5.7, we have illustrated such a machine
cycle. Note, that instead of reading, it might be a writing operation also.
Each machine cycle is composed of several T-states. One complete oscillation of the processor clock is
designated as one T-state. Depending upon the processor, the number of T-states necessary tocomplete one
machine cycle must be known. For example, Intel 8085 processor needs four to six T-states to complete
one machine cycle. The correlation ofT-states, machine cycle and instruction cycle is shown in Figure 5.8.
For the sake of example, execution of an instruction increment a memory location by one is illustrated
through Figure 5.8.It is assumed that it is a 1-byte instruction, which is fetched by the first machine cycle.
As the data, to be incremented by one, are available in external memory location, the next machine cycle
eads this operand from memory (brings the data byte within the processor). The data are then incremented
Oy one by the processor and are stored back in the same memory location in the third machine cycle.
Two questions may arise after this explanation of Figure S.8, as follows
) When the instruction was decoded?
(1) When the data were incremented by one?
aswer the first question, it must be pointed out that the instruction must be decoded before the beginning of
G Second machine cycle, as the processor must know by that timne what to do. As a
rule, instruction deoaing
102 Computer Architecture and Organization

One ineteti cycla

(E xample instuction Inttement a momnty leatt ty e)
fet martine cyclo
1st. machine cycle 2nd machine cycle 3rd mahing cyle Fotryincction)
(Fetch instruction) (Get data and (Store tosut tak)
incremented by 1)

System clock

One
T-state

cycle and T-state Correlation

Figure 5.8 Example of instruction cycle, machine
Words
processor. In other
is carried out immediately after receivingthe instruction byte within the demand any extra tte
case, instruction decoding is done at the end of the first machine cycle. Does it not
Well hardware-based
it depends. If it isita would decodino then it does not need any extra time. howeveT, n case ge
micro-programming, consume one or two extra T-states. For example, Intel 8085spends four Tstater
forspends
fetching
only the firstT-states.
three instruction
As abyte during
matter is infirstitsmachine
of fact, cycle,cycle
first machine whilefirst
for three
subsequent
T-statesmaenine cyciesiort
are sufficient
Tetching the first byte of instruction. Next T-state ofthe first machine cycle is devoted for instruction decoding
As the answer of the secondquestion, we can say that the data would be incremented either at the d
of second machine cycle or at the beginning of the third machine cycle, depending upon the processor
Here also, the adopted technique plays an important role.
5.3.6 Timings, Control and Response
Through the above discussions, it must be clear to the reader that timing and control play very importa
roles in smooth and efficient functioning of any processor. To further explain this concept, we may tak:
up the example of interrupt.
Although we shall have adetailed discussions on interrupt in Section 5.6, it may be introduced here
as an external asynchronous signal, which forces the processor to carry
out
branching to a pre-defined address and, thus, exXecuting a special programsomething special for itby
rupt service routine (ISR). As this is an asynchronous signal, it segment, known as InE
the execution of any instruction by the procesSor. may be activated at any time durng
However, the processor cannot leave an instructteci
execution half-way start doing something else for the sake of such an
to
Tosolve this problem, processors reserve a interrupting signal.
rupt input signal during the execution of eachparticular time-slot for checking the existence of any n
had reserved the penultimate T-state of the and every instruction. For example, Intel 8O85 protts
last
checking. If it ispresent, then the next instructionmachine
would
cycle of any instruction for this
not be
interrupt S
would start executing from the executed immediately and the prv
the modified flowchart of the interrupts ISR. We shall discuss more about it in the Section 5.6. HoWe
instruction cycle is presented in Figure 5.9, where the
portion is shaded. The reader may compare it with Figure 5.6. previously expla
5.4 REGISTER SET
To perform internal
or some operations,
all processors offer some
information operands. Similar to internal registers, which can store
tempor
tion of several
flip-fiops. Most of these
read/write memory, these registers are nothing but a
combit
The number of user registers are user are no

accessi1ble (programmer)
registers varies from processor accessible
to processor.
and a few thatat
processors
Those
 Processor Basics 103

Instruction
fetch

Instruction
decode

Operand Yes
fetch Fetch
needed operand

No

Instruction
execute

Store
result

Any Yes
interrupt Load PC by
ISR address

No
Figure 5.9 Modified flowchart for simplified
instruction cycle
memory oriented (e.g., Motorola 6800) offers lesser number of internal
operands would mainly be stored and manipulated within the read/writeregisters as it expects the data or
On the other hand, some processors are register oriented (e.g., memory (RAM) of the system.
of internal registers for the user. It may be noted that the
Zilog Z80), which offers a larger number
be less if the data are available within itself rather than program execution time for a processor would
looking outside for them. However, more inter
nal registers means more complexity in instruction decoding as
each register would demand aseparate
instruction to be provided by the instruction set of the processor.
So far, we have been discussing about the general purpose
are also available within the processors. They are registers. However, other types of registers
accumulator or result register, status register, stack
pointer, program counter, interrupt register and so on. Most of these registers, in most
be user accessible.Apart from these, there aresome processors, would
registers that are purely for processor's own use, e.g.,
temporary registers. We shall now have a brief discussion about someof these special purpose
registers.
5.4.1 Status Register
EVery processor performs some arithmetic or logical operations generating some results.
upon whether the result is zero or negative or produced a carry or odd/even parity, some Depending
additional
dcions might have to be taken by the programmer. Status register solves this problem by offering the
esult status of the last performed arithmetic or logical operation through its pre-assigned bits. Gener
YCach bit of this status register is assigned for one particular indication, e.g.,carry, parity, zero,
Ovetiow and so on. These bits act as flags and their conditions (true or false) help the program to delde
urther course of actions and dictate the conditional program branching.
104 Computer Architecture and Organization

5.4.2 Accumulator
availahle ofnty in the
macke
In carlicr proccssots, fcsult of all atithmetic ot logical petatints weteregrstets 4v1lable wifhit fhe
accumulatot. In morc tecent rgister tn-rgister atchitecture, all relev ant
proccssor may contain thc result of similar opcrations
5.4.3 Program Counter responsible for hold1tg the
within any processot as it is proceNsor
This is onc of the most important registerS fetched hy the Afer
word to be
address of the memory location for next instruction byte to pont to the nEt byte The
by one
fetching every instruction byte, this is automatically incremented is in the case of program bratch1ng
counter
only exception for this auto-increment of the program initialized during systemreset so that the firs
when it is reloaded by a new value. This counter is always
location of the memory.
executable instruction byte is fetched from a pre-defined
5.4.4 Stack Pointer mtor
is earmarked by the programmer to accommodate inportant
System stack is a RAM area, which Stack pointer
mation, e.g., return address or register values, in last-in-first-out(LIFO) sequence. Section
in
alwzs
S.5.
about the system stack
points to the top of the stack area. We shall discuss more

5.4.5 General Purpose Registers

For at
for temporary data storage and manipulation.
These registers are available within the processor must be within these registers (the other one shoele
metic or logical operations, one of the two operands
registers vary, depending upon the processr
be in the accumulator). As already indicated, number of these
5.5 STACK ORGANIZATION
program or r.
Stack is an area within the system RAM earmarked for some special storage by the
grammer. In other words, the stack consists of several bytes of read-write memory where some speral
data may be stored in and restored from, as per the program'srequirements. Why this cannot be accom
plished by using the available registers within the processor? This is because, the number of registess
very limited and they have their other specific purpose rather than storing retum addresses.
Stack is, generally, used to store some important address and data sets. The particular location wtàa
the stack, where the next such information to be stored, is known as the stack-top. Generally, the sucs
of this stack-top is available in the register designated for this specific purpose and known as Saci
Pointer. Figure 5.10(a) illustrates a sample stack area within the address space between FFFOH
FFFFH (16-bytes) and the stack pointer. It is assumed that some stack locations are already ocruçd
(used for storage) and the stack pointer has the address of the next free location of stack, ie., FFF#
If any new data to be stored within the stack are included, it must be stored in the address pontu
the stackpointer, i.e., FFF9H, and in that case the stack pointer would show the next
available ree
tion for storage, i.e., FFF8H, as shown in Figure 5.10(6). Stack follows the last-in-first-out (LIro
movement technique. In other words, the data that is placed last on the stack-top must be retrievedix

5.5.1 Stack as Storage Area

In general, every processor offers two instructions to handle the stack directly. These two instructio
are PUSH and POP. PUSH instruction places the data on the stack-top and POP instruction takesit
 Processor Basics105

FFFOH
FFF1H FFFOH
FFF1H
FFF2H Free FFF2H
FFF3H
FFF4H FFF3H
Stack
area FFF4H
FFF5H FFF5H Stack
area
FFF6H
FFF6H
FFF7H
FFF7H
FFF8H
Stack-top FFF9H Stack-top FFF8H
FFFAH
kOccupied Data saved here FFF9H
+Occupied
FFFAH
FFFBH FFFBH
FFF9 FFFCH FFFCH
FFFDH FFF8
Stack pointer (SP) FFFDH
FFFEH Stack pointer (SP) FFFEH
FFFFH
(updated) FFFFH
(a) (b)
Eigure 5.10 Stack and its operation
from the stack-top. These data might be originally available within a general purpose register or some
other data. It is already mentioned that the register within the processor, which holds the curTent stack
top address, is designated as stack pointer (SP). Whenever any data are placed on the stack-top or taken
out from it, SP is also automatically changed by the processor itself. Here, we use the term 'changed
as, for some processorS, a PUSH operation increments the SP while for other processors the SP is dec
remented for aPUSH instruction.