CS/EE 260 – Digital Computers: Organization and Logical Design

Problem Set 6 Solutions

Jon Turner Quiz on 3/27/03

1. A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of
output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a
circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition
diagram, a state table and a schematic for your circuit. Design an alternate implementation
using just three flip flops and draw a state transition diagram, state table and a schematic
for your circuit. If your designs are extended to implement an n bit twisted ring counter,
how many flip flops are required using each of the two approaches. In what situations
would you prefer the first method? In what situations would you prefer the second?

present next 0000/0000 0001/0001

state state output
0000 1000 0000
1000 1100 1000 1000/1000 0011/0011
1100 1110 1100
1110 1111 1110
1111 0111 1111 1100/1100 0111/0111
0111 0011 0111
0011 0001 0011
0001 0000 0001 1110/1110 1111/1111

outputs

D Q D Q D Q D Q

>C Q′ >C Q′ >C Q′ >C Q′

Enable
Clk

-1-
If the designs are extended to n bits, the first will need n flip flops, while the second will need
1+log2n (assuming n is a power of 2). So for example, if n=64, this would be 64 vs. 7. On the other
hand, the second will need more gates to generate the output logic, which could more than
compensate for the savings in the number of flip flops. The first is preferable if speed is critical, but
the second might be better for large values of n if it is important to minimize the number of flip flops.

present next 000/0000 111/0001

state state output
000 001 0000
001 010 1000 001/1000 110/0011
010 011 1100
011 100 1110
100 101 1111 010/1100 101/0111
101 110 0111
110 111 0011
111 000 0001 011/1110 100/1111

outputs

D Q

>C Q′

D Q

>C Q′

D Q

>C Q′

Enable Clk

-2-
2. Write VHDL specifications for an eight bit twisted ring counter based on each of the
designs in the previous problem. Look at the synthesis report generated by the design tools
(use the Spartan 2 xc2s15-cs144-6 part for this). How many flip flops are required for each of
the designs? How many LUTs of all types? What is the maximum estimated clock
frequency?

The code for the first version is shown below. The synthesis report indicates that this uses 8 flip flops
and 2 LUTs. The maximum estimated clock frequency is 306 MHz.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity twistRing is
Port ( clk, enable : in std_logic;
count : out std_logic_vector(7 downto 0));
end twistRing;

architecture Behavioral of twistRing is

signal countReg: std_logic_vector(7 downto 0);
begin
process(clk) begin
if clk'event and clk = '1' then
if enable = '0' then
countReg <= x"00";
else
countReg <= (not countReg(0)) & countReg(7 downto 1);
end if;
end if;
end process;
count <= countReg;
end Behavioral;

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The code for the second version is shown below. The synthesis report indicates that this uses 4 flip
flops and 11 LUTs of various types. The maximum estimated clock frequency is 200 MHz. These
results are consistent with the observations made in the original problem. The first version is faster,
uses more flip flops, but requires relatively little logic.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity twistRing2 is
Port ( clk : in std_logic;
enable : in std_logic;
count : out std_logic_vector(7 downto 0));
end twistRing2;

architecture Behavioral of twistRing2 is

signal reg : std_logic_vector(3 downto 0);
begin
process(clk) begin
if clk'event and clk = '1' then
if enable = '0' then
reg <= x"0";
else
reg <= reg + x"1";
end if;
end if;
end process;
count(7) <= '1' when x"1" <= reg and reg <= x"8" else '0';
count(6) <= '1' when x"2" <= reg and reg <= x"9" else '0';
count(5) <= '1' when x"3" <= reg and reg <= x"a" else '0';
count(4) <= '1' when x"4" <= reg and reg <= x"b" else '0';
count(3) <= '1' when x"5" <= reg and reg <= x"c" else '0';
count(2) <= '1' when x"6" <= reg and reg <= x"d" else '0';
count(1) <= '1' when x"7" <= reg and reg <= x"e" else '0';
count(0) <= '1' when x"8" <= reg and reg <= x"f" else '0';
end Behavioral;

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3. Draw a schematic for a 4 bit grey code counter that has a load input, a count input and a
reset input. If reset is high, the circuit should reset to 0000, otherwise if load is high, it
should load a new value, otherwise if count is high it should advance by 1, otherwise, it
should retain its current value. When counting, your counter should produce the sequence
0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000
and should then wrap around to 0000. Show the Karnaugh maps and logic equations used
to produce the increment logic.

present next CD CD
state state 00 01 11 10 00 01 11 10

0000 0001 00 0 0 0 0 00 0 1 1 1
0001 0011 01 1 0 0 0 01 0 0 0 1
0010 0110 AB AB
11 1 1 1 1 11 0 1 1 1
0011 0010
0100 1100 10 0 1 1 1 10 0 0 0 1
0101 0100 DA= A(C + D) + BC′D′ DC= CD′ + D(A ⊕ B)′
0110 0111
0111 0101 CD CD
00 01 11 10 00 01 11 10
1000 0000
1001 1000 00 0 0 0 1 00 1 1 0 0
1010 1011 01 1 1 1 1 01 0 0 1 1
1011 1001 AB AB
11 1 1 1 0 11 1 1 0 0
1100 1101
1101 1111 10 0 0 0 0 10 0 0 1 1
1110 1010 DB= B(C′ + D)+ A′CD′ DD= A ⊕ B ⊕ C
1111 1110

-5-
-6-
4. In this problem, you are to design a serial multiply-by-5 circuit. Your circuit will have a
single data input D, a synchronous reset input R and a single output Q. Whenever R is high,
your circuit should output 0, but when R drops low, your circuit should treat input D as a
binary value, received with the least significant bit first. Your circuit should output a value
which is equal to the input value, multiplied by 5. So if you receive the values 0001101
(where the rightmost bit is received on the first clock tick following reset, then the second
bit from the right, etc.) your circuit will output 1000001. Note that for any value x, 5x = 4x +
x, and 4x is the same as x with two bits additional bits at the right. So you can perform the
multiplication by adding x to a delayed version of itself.

Create a block diagram for a circuit that implements the serial multiply-by-5 function,
assuming that you have two sub-circuits, one of which implements a delay of two clock
ticks and another which implements a serial adder (such a circuit takes two binary values,
starting with their least significant bit and outputs the sum).

Din A
Din Dout B
clk delay (2) clk adder A+B Dout
reset reset
clk
reset

Make logic diagrams of each of the two sub-circuits. For the serial adder, also show the state
transition diagram for the circuit, the state table, the next-state equations and the output
equations.

The state diagram for the serial adder is shown below. This is for a Mealy model circuit. The actual
implementation adds a flip flop on the output, converting it to a Moore model circuit and delaying
the output sum bit by one clock tick relative to the input bits.

S0 AB D0 Sum
11/0 0 00 0 0
00/0 10/0 01 1 1
01/1 0 1 01/0 10 0 1
10/1 11/1 11 1 0
00/1 1 00 0 1
01 1 0
D0 = AB + AS0 + BS0 Sum = A ⊕ B ⊕ S0 10 1 0
11 0 1

Schematics for both circuits appear below.

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Show how you could use the same idea to produce a serial multiply-by-13 circuit. Show
the block diagram of the resulting circuit.

Since 13 is 1101 in binary, a multiply by 13 will require two adders and two delays. The block
diagram that illustrates how this is done is shown below. The reason for using a second two stage
delay is to compensate for the one clock tick of delay that occurs in the first adder.

Din A
Din Dout B
clk delay (2) clk adder A+B
reset reset

A
Din Dout B
clk delay (2) clk adder A+B Dout
reset reset

clk
reset
Show how to generalize this idea to produce a general 4 bit serial multiplier. This circuit
has a reset input and two serial data inputs, A and B and has a single output, which is
equal to the product of A and B. Show a block diagram for such a circuit, using serial
adders as building blocks.

-8-
The block diagram appears below. When the reset signal drops, the Mreg block at the bottom
stores the bits of the multiplier, starting with the least significant bits. These bits are used to
control the addition of partial products in the adders at right. The delay blocks act to delay the
input value by appropriate amounts. The initial delay is needed because the Mreg block also has
a delay of one clock tick. Two stage delays are used in most of the delay blocks to compensate for
the one tick delay in the serial adder blocks.

multiplicand Din Dout

clk delay (1)
reset

A
Din Dout B
clk delay (1) clk adder A+B
reset reset

A
Din Dout B
clk delay (2) clk adder A+B
reset reset

A
Din Dout B
clk delay (2) clk adder A+B Dout
reset reset

clk
reset

multiplier Din 0123

clk Mreg
reset

-9-
5. Write a VHDL module to implement an eight bit serial multiplier based on the design
developed in the previous problem. There are two ways you can do this. One is to
implement the components of the serial multiplier and then instantiate them and “wire”
them together using structural VHDL (you may want to use a for-generate statement to
avoid having to specify each bit separately). There is a more concise way to write the
VHDL, using a shift register to hold the bits of the multiplicand, a second register to hold
the multiplier, a third register to hold the bits of the product and a fourth to hold the carry
bits from the serial additions.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity serMult is
Port ( clk, reset, multiplicand, multiplier : in std_logic;
product : out std_logic);
end serMult;

architecture Behavioral of serMult is

signal mc: std_logic_vector(13 downto 0); -- multiplicand register
signal mr: std_logic_vector(7 downto 0); -- multiplier register
signal p: std_logic_vector(7 downto 1); -- product register
signal c: std_logic_vector(7 downto 1); -- carry bit register
signal t: std_logic_vector(3 downto 0); -- time step
begin
process(clk) begin
if clk'event and clk = '1' then
if reset = '1' then
mc <= "00" & x"000"; mr <= x"00";
p <= "0000000"; c <= "0000000"; t <= "0000";
else
mc <= mc(12 downto 0) & multiplicand;
if t <= 7 then
mr(conv_integer(unsigned(t))) <= multiplier;
t <= t + "0001";
end if;
p(1) <= (mr(0) and mc(0)) xor (mr(1) and mc(1));
c(1) <= (mr(0) and mc(0)) and (mr(1) and mc(1));
for i in 2 to 7 loop
p(i) <= p(i-1) xor c(i) xor (mr(i) and mc(2*i-1));
c(i) <= (p(i-1) and c(i)) or
(p(i-1) and (mr(i) and mc(2*i-1))) or
(c(i) and (mr(i) and mc(2*i-1)));
end loop;
end if;
end if;
end process;
product <= p(7);
end Behavioral;

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6. The figure below is a block diagram of an 8 bit pipelined multiplier. This circuit produces
the product of two 8 bit numbers after a delay of several clock ticks. The use of registers
between the ranks of adders makes it possible to input a new multiplier and multiplicand
on every clock tick and get a product out on every clock tick. This kind of pipelined
operation is commonly used in high performance systems.

multiplier

multiplicand clk
load register (8)
reset
register (8)
reset
load
clk

and-8 and-8 and-8 and-8 and-8 and-8 and-8 and-8

adder-9 adder-9 adder-9 adder-9

clk register-10 clk register-10 clk register-10 clk register-10

reset reset reset reset

adder-12 adder-12

clk register-12 clk register-12

reset reset

adder-16

clk register-16
reset

product

Assuming that we start with no multiplication operations in progress, how many multiplies
can be completed in 30 ns, assuming that the clock period is 4 ns? How many can be
multiplies can be completed in 100 ns?

It takes 4 clock periods to produce the first product, so in the 7 clock periods available in 30 ns, 4
products can be produced. In 100 ns (25 clock periods) we get 22 products. The initial delay before
the first product is produced is called the pipeline delay.

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Assuming that the adders are implemented using a look-ahead circuit like the one
illustrated below what is the maximum gate delay we can tolerate and still have the circuit
operate correctly with a clock period of 4 ns? Assume that the flip flop setup time is 700 ps,
that the maximum propagation delay is 1 ns and that the maximum clock skew is 300 ps.

With a clock period of 4 ns, a setup time of 700 ps, a flip flop propagation delay of 1 ns and a clock

skew of 300 ps, there is 2 ns available for the combinational circuit delays. A 9 bit or 12 bit version of
the adder above has a maximum delay from inputs changing to sum outputs changing of 9 gate
delays. A 16 bit version has a maximum of 10 gate delays.. The registers will also have a
combinational circuit delay of perhaps 2 gates, meaning that we need a maximum gate delay of 167
ps.

- 12 -
7. Write a VHDL specification of a 16 bit multiplier, based on the design discussed in the
previous problem.

The VHDL code that implements the pipelined multiplier appears below.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pipeMult is
Port ( clk, reset, load : in std_logic;
multiplicand : in std_logic_vector(15 downto 0);
multiplier : in std_logic_vector(15 downto 0);
product : out std_logic_vector(31 downto 0));
end pipeMult;

architecture Behavioral of pipeMult is

signal mc: std_logic_vector(15 downto 0); -- multiplicand register
signal mr: std_logic_vector(15 downto 0); -- multiplier register
type pp_typ is array(0 to 31) of std_logic_vector(15 downto 0);
signal pp: pp_typ; -- array of partial products
type s1_typ is array(0 to 7) of STD_LOGIC_VECTOR(17 downto 0);
signal s1: s1_typ; -- array of stage 1 pipeline registers
type s2_typ is array(0 to 3) of STD_LOGIC_VECTOR(19 downto 0);
signal s2: s2_typ; -- array of stage 2 pipeline registers
type s3_typ is array(0 to 1) of STD_LOGIC_VECTOR(23 downto 0);
signal s3: s3_typ; -- array of stage 3 pipeline registers
signal s4: STD_LOGIC_VECTOR(31 downto 0); -- final stage
begin
process (mc,mr) begin -- comb. logic process for partial products
for i in 0 to 15 loop
if mr(i) = '1' then
pp(i) <= mc;
else
pp(i) <= x"0000";
end if;
end loop;
end process;

process (clk) begin

if clk'event and clk = '1' then
if reset = '1' then
mc <= x"0000"; mr <= x"0000";
for i in 0 to 7 loop
s1(i) <= "00" & x"0000";
end loop;
for i in 0 to 3 loop
s2(i) <= x"00000";
end loop;
for i in 0 to 1 loop
s3(i) <= x"000000";
end loop;
s4 <= x"00000000";
else
if load = '1' then
mc <= multiplicand; mr <= multiplier;
end if;
for i in 0 to 7 loop -- stage 1 of pipeline
s1(i) <= ("00" & pp(2*i)) + ("0" & pp(2*i+1) & "0");

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 end loop;
for i in 0 to 3 loop -- stage 2 of pipeline
s2(i) <= ("00" & s1(2*i)) + (s1(2*i+1) & "00");
end loop;
for i in 0 to 1 loop -- stage 3 of pipeline
s3(i) <= ("0000" & s2(2*i)) + (s2(2*i+1) & "0000");
end loop;
s4 <= ("00000000" & s3(0)) + (s3(1) & "00000000");
end if;
end if;
end process;
product <= s4;
end Behavioral;

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