Introduction to Silicon Process and VLSI

Propagation Delay
 Agenda
• Propagation delay
• Dynamic response
• Inverter Sizing
• Power Dissipation

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 Review - CMOS Inverter First-Order DC Analysis
V DD VOL = 0 V DD Properties
VOH = VDD 1) High and low outputs = VDD and Ground.
VM = f(Rn, Rp) Voltage swing= VDD. High Noise Margins.
Rp
2) Logic Levels are independent of device sizes (ratioless logic)

3) In steady state, a path exists from O/P to VDD or GND. Thus,

V out
V out low output impedance. Less sensitive to noise.

4) Input resistance is extremly high, since MOS

Rn gate draws no dc input current. Steady-state
input current ~ zero.

5) In steady-state, no direct path exists between supply and

ground rails. No static power (ignoring leakage)
V in 5 V DD V in 5 0

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 CMOS Inverter: Transient Response
• Transient response is the response of a system to a change from an equilibrium or
a steady state.
• There is a delay here for this inverter circuit given an input voltage of low to high
the change in the logic from high to low the output voltage.

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 4
 CMOS Inverter: Dynamic Behavior
The propagation delay of the CMOS
inverter is determined by the time it
takes to charge and discharge the
load capacitor CL through the PMOS
and NMOS transistors, respectively.

This observation suggests that

getting CL as small as possible is
crucial to the realization of high-
performance CMOS circuits.

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 Computing the Capacitances
M1 and M2 are either in cut-off or
in saturation mode during the first
half (up to 50%) of the output
transient.

The only contribution to Cgd12

are the overlap capacitances of both M1
and M2.

The channel capacitance is either

completely located between gate
and bulk (cut-off) or gate and source
(saturation).

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 6
 Computing the Capacitances
Gate Capacitance

M1 and M2 are either in cut-off or

in saturation mode during the first
half (up to 50%) of the output
transient.

The only contribution to Cgd12

are the overlap capacitances of both M1
and M2.

The channel capacitance is either

completely located between gate
and bulk (cut-off) or gate and source
(saturation).

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 7
 Miller Effect

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 Computing the Capacitances

Diffusion capacitances

Cdb1 and Cdb2 are due to

the reverse-biased pn-junction (same as we did
for diode & MOS case –

Ceq=KeqCj0

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 9
 Computing the Capacitances
Fan-Out Capacitance

Ignores Miller effect on the gate-drain

capacitance. This is acceptable since the
connecting gate would not switch before the
50% point is reached, and Vout2 remains
constant in the interval of interest.

Assume the channel capacitance of the

connecting gate is constant over the
interval of interest. In reality it varies from
2/3CoxWL in saturation to WLCox in linear
and cutoff.

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 10
 Propagation Delay
• to compute the propagation delay of the inverter we can integrate the capacitor (dis)charge
current.
• Both CL(v) and i(v) are nonlinear functions of v.

• Use simplified switch-model of the inverter to derive a reasonable approximation for manual
analysis.
• The voltage-dependencies of the on-resistance and the load capacitor are addressed by replacing
both by a constant linear element with a value averaged over the interval of interest.

It is desirable for a gate to have identical propagation delays

for both rising and falling inputs.
> Make the on-resistance of NMOS and PMOS equal.
>> Same requirement for a symmetrical VTC.

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 Transient Response
3

2.5
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
Vout(V)

tpHL tpLH
1

0.5

-0.5
0 0.5 1 1.5 2 2.5
t (sec) x 10
-10

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 Design Optimization Lecture 4,
slide 14
How designer can optimize the delay of a gate
Expanding Req

Assuming for the factor l is ignorable here.

If the supply voltage is chosen high enough so that VDD >> VTn +VDSATn/2. Observe that this is a first-order approximation
Increasing the supply voltage yields an
The delay becomes virtually independent of the supply voltage observable, improvement in performance due to
a non-zero channel-length modulation factor.

The delay is relative insensitive to supply variations for higher

values of VDD.
A sharp increase can be observed starting around 2VT.
This operation region should clearly be avoided if achieving
high performance is a premier design goal.
>> Dynamic VDD scaling?

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 Design for Performance - Reduce CL

• Reduce CL
• The internal diffusion capacitance Cdiff,
• the interconnect capacitance Cwire
• C fan-out.
• Careful layout helps to reduce the diffusion and interconnect
capacitances.
• Good design practice requires keeping the drain diffusion areas as
small as possible.

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 14
 Design for Performance – Increase W/L
• Increase the W/L ratio of the transistors.
• The most powerful and effective
performance optimization tool in the
hands of the designer.
• Be Careful
• Increasing the transistor size also raises the
diffusion capacitance and hence CL.
• When the intrinsic capacitance (i.e. the diffusion
capacitance) starts to dominate the extrinsic load
formed by wiring and fanout, increasing the gate
size does not longer help in reducing the delay,
and only makes the gate larger in area. >> This
effect is called “self-loading”.
• Also wide transistors have a larger gate
capacitance, which increases the fan-out factor of
the driving gate and adversely affects its speed.

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 15
 Design for Performance – Increase VDD

• The delay of a gate can be modulated by modifying the

supply voltage.

• Trade-off energy dissipation for performance.

• Be Careful

• Increasing the supply voltage above a certain

level yields only very minimal improvement

• It can cause reliability concerns (oxide breakdown,

hot-electron effects) in deep submicron

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 NMOS/PMOS ratio
• Widened the PMOS transistor so that its
resistance matches that of NMOS.
• This typically requires a ratio of 2.5 to 3
between PMOS and NMOS width.
• Symmetrical VTC
• Equal tpHL and tpLH
• What about the overall propagation delay?
• Widening the PMOS improves the tpLH of the
inverter by increasing the charging current
• It also degrades the tpHL be cause of a larger
parasitic capacitance.
• When two contradictory effects are present, there
must exist a transistor ratio that optimizes the Smaller devices yield faster
propagation delay of the inverter. designs at expense of
symmetry and noise margin

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Inverter Sizing
 Inverter Chain

In
Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.

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 Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
W
−1 −1
 W   W 
RP = Runit  P   Runit  N  = RN = RW
 Wunit   Wunit 
Define Wunit as the
Delay (D): smallest width of
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL transistor in the
technology

Load for the next stage: W

Cgin = 3 Cunit
Wunit

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 Inverter with Load

Delay

RW

CL

RW Load (CL)
tp = k RWCL

k is a constant, equal to 0.69

Assumptions: no load -> zero delay

Wunit = 1
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 Inverter with Load
CP = 2Cunit Delay
2W

W
Cint CL

CN = Cunit Load

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

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 Delay Formula
Delay ~ RW (Cint + CL )

t p = kRW Cint (1 + CL / Cint ) = t p 0 (1 + f /  )

f : effective fanout the ratio between external load capacitance and input capacitance
f = CL/Cgin

tp0 = 0.69RunitCunit: The intrinsic delay of the inverter tp0 is Cint = Cgin with   1
independent of the sizing of the gate, and is purely determined f = CL/Cgin - effective fanout
by technology and inverter layout. R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
 is a proportionality factor, which is only a function of
technology and is close to 1 for
most sub-micron processes.

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 Apply to Inverter Chain

In Out

The goal is to minimize the

delay through the inverter CL
1 2 N
chain, with the input
capacitance of the first
inverter Cg1—typically a tp = tp1 + tp2 + …+ tpN
minimally-sized device—
and the load capacitance CL
 C gin , j +1 
t pj ~ Runit Cunit 1 + 
fixed
 C 
 gin , j 
N N  C gin , j +1 
t p =  t p , j = t p 0  1 + , C gin , N +1 = C L
 C
i =1 

j =1 gin , j 

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 Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

- each stage has the same effective fanout (Cout/Cin) Cgin , j = Cgin , j −1Cgin , j +1
- each stage has the same delay

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 Optimum Delay and Number of Stages

When each stage is sized by f and has same eff. fanout f:

f N = F = CL / Cgin ,1
Effective fanout of each stage:

f =NF
Minimum path delay

(
t p = Nt p 0 1 + N F /  )
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 Example

In
Out

CL= 8 C1
C1 1 f f2

CL/C1 has to be evenly distributed across N = 3 stages:

f =38 =2

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 Optimum Number of Stages
When N is large, the first component dominates (intrinsic
delay).
If N is too small, the effective fanout of each stage
(
t p = Nt p 0 1 + N F /  )
becomes large, and second component is dominant.

For a given load, CL and given

input capacitance Cin ln F
Find optimal sizing f
C L = F  Cin = f Cin with N =
N

ln f

t p 0 ln F  f  
(
t p = Nt p 0 F /  + 1 =
1/ N
)
 +
  ln f ln f


t p t p 0 ln F ln f − 1 −  f
=  =0
f  ln f 2

For  = 0, f = e, N = lnF f = exp (1 +  f )

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 Optimum Effective Fanout f
Optimum f for given process defined by 

f = exp (1 +  f )
Optimum effective fopt = 3.6
fanout f (or inverter for =1
scaling factor) as a
function of the self-
loading
factor  in an inverter
chain.

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 Normalized delay function of F

(
t p = Nt p 0 1 + N F /  )

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 Buffer Design
N f tp
1 64 1 64 65

1 8 64
2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6

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Power Dissipation
 Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors

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 Dynamic Power Dissipation
Vdd
Each time the capacitor gets
charged through the PMOS
transistor, its voltage rises from 0 Vin Vout
to VDD, a certain amount of
energy is drawn from the power
supply. CL

Part of this energy is

dissipated in the PMOS device, Energy/transition = CL * Vdd2
while the remainder is stored on
the load capacitor. Power = Energy/transition * f = CL * Vdd2 * f
f represents the frequency of energy-consuming transitions (0 -> 1)
During the high-to-low transition,
this capacitor discharged, and Not a function of transistor sizes!
the stored energy is dissipated in Need to reduce CL, Vdd, and f to reduce power.
the NMOS
transistor.

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 Modification for Circuits with Reduced Swing
Vdd
Using NMOS as the pull up device Vdd

Vdd -Vt

CL

E 0 → 1 = CL • Vdd • ( Vdd – Vt )

Can exploit reduced sw ing to low er power

(e.g., reduced bit-line swing in memory)

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 Node Transition Activity and Power

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 Short Circuit Currents
Vd d

Vin Vout

CL

0.15

IVDD (mA) 0.10

0.05

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

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 Minimizing Short-Circuit Power
8

5
Vdd =3.3

Pnorm
4
Vdd =2.5
3

1
Vdd =1.5
0
0 1 2 3 4 5
t /t
sin sout

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 Leakage
Vd d

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-threshold current one of most compelling issues

in low-energy circuit design!Current Dominant Factor
Sub-Threshold

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 Subthreshold Leakage Component

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 Static Power Consumption
Vd d

Istat
Vo ut

CL
Vin =5V

Pstat = P(In=1).Vdd . Istat

• Dominates over dynamic consumption

Wasted energy …
• Not a function
Should of switching
be avoided in almostfrequency
all cases,

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 Principles for Power Reduction
• Prime choice: Reduce voltage!
• Recent years have seen an acceleration in supply
voltage reduction
• Design at very low voltages still open question (0.6 …
0.9 V by 2010!)
• Reduce switching activity

• Reduce physical capacitance

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Impact of Technology Scaling
 Goals of Technology Scaling
• Make things cheaper:
• Want to sell more functions (transistors) per chip for the same money
• Build same products cheaper, sell the same part for less money
• Price of a transistor has to be reduced
• But also want to be faster, smaller, lower power

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 Technology Scaling
• Goals of scaling the dimensions by 30%:
• Reduce gate delay by 30% (increase operating frequency by 43%)
• Double transistor density
• Reduce energy per transition by 65% (50% power savings @ 43% increase in
frequency
• Die size used to increase by 14% per generation
• Technology generation spans 2-3 years

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 Technology Generations

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 Technology Evolution (2000 data)

International Technology Roadmap for Semiconductors

Year of
1999 2000 2001 2004 2008 2011 2014
Introduction
Technology node
180 130 90 60 40 30
[nm]
Supply [V] 1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6
Wiring levels 6-7 6-7 7 8 9 9-10 10
Max frequency 14.9
1.2 1.6-1.4 2.1-1.6 3.5-2 7.1-2.5 11-3
[GHz],Local-Global -3.6
Max mP power [W] 90 106 130 160 171 177 186
Bat. power [W] 1.4 1.7 2.0 2.4 2.1 2.3 2.5

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

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 Technology Evolution (1999)

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 ITRS Technology Roadmap Acceleration Continues

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 Technology Scaling (1)
2
10

Minimum Feature Size (micron)

1
10

0
10

-1
10

-2
10
1960 1970 1980 1990 2000 2010
Year

Minimum Feature Size

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 Technology Scaling (2)

Number of components per chip

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Technology Scaling (3)

tp decreases by 13%/year
50% every 5 years!

Propagation Delay
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 Technology Scaling (4)

rs
x1.4 / 3 yea 
0.7
100 1000
Power Dissipation (W)

Power Density (mW/mm2 )

ears
3y 

3
10 /
x4 100


1

10
0.1
MPU
DSP
0.01 1
1 10
80 85 90 95 Scaling Factor
Year （normalized by 4mm design rule）
(a) Power dissipation vs. year. (b) Power density vs. s caling factor.

From Kuroda
CND121: INTRODUCTION TO SILICON PROCESS & VLSI
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 Technology Scaling Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S

• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant

• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors

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 Scaling Relationships for Long Channel Devices

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Transistor Scaling (velocity-saturated devices)

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 mProcessor Scaling

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 mProcessor Power

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 mProcessor Performance

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 2010 Outlook
• Performance 2X/16 months
• 1 TIP (terra instructions/s)
• 30 GHz clock
• Size
• No of transistors: 2 Billion
• Die: 40*40 mm
• Power
• 10kW!!
• Leakage: 1/3 active Power

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001

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 Some interesting questions
• What will cause this model to break?
• When will it break?
• Will the model gradually slow down?
• Power and power density
• Leakage
• Process Variation

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