MT7621 ProgrammingGuide Preliminary Platform
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DhimantthankiMT7621 ProgrammingGuide Preliminary Platform
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MT7621
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PROGRAMMING
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GUIDE
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[email protected],time=2014-09-19 10:42:07,ip=218.17.61.76,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=ASEC International (H.K.) Limited 亞矽(香港)_RLT
MT7621 PROGRAMMING GUIDE
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MT7621 Overview
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The MT7621 SoC includes a high performance 880 MHz MIPS1004Kc CPU core and high speed
USB3.0/PCIe/SDXC interfaces, which is designed to enable a multitude of high performance, cost-effective IEEE
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802.11n/ac applications with a MediaTek (Ralink) WiFi client card.
Functional Block Diagram
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EJTAG 16-Bit DDR2/DDR3 To CPU
INTC interrupts
MIPS 1004Kc DRAM Timer
Controller
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32/32 KB I/D- SPI SPI
Cache per Core OCP_IF
(880 MHz) OCP Bridge Arbiter NFI NAND
UARTLx3 UART
PBUS
RBUS GPIO
GPIO
/LED
I2C I2C
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USB 3.0/2.0 PCIe 1.1 Crypto Switch GDMA/ I2S I2S
SDXC
PHY PHY Engine (5GE) HSDMA
PCM x4 PCM
5-Port EPHY RGMII SPDIF SPDIF
SD Host PCIe x 3
RJ45 x5 TMII/MII x1
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Figure 1-1 MT7621 Block Diagram
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There are several masters (MIPS 1004KEc, USB, PCI Express, SDXC, FE) in the MT7621 SoC on a high
performance, low latency Rbus, (Ralink Bus). In addition, the MT7621 SoC supports lower speed peripherals
such as UART Lite, GPIO, NFI and SPI via a low speed peripheral bus (Pbus). The DDR2/DDR3 controller is the
only bus slave on the Rbus. It includes an Advanced Memory Scheduler to arbitrate the requests from bus
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masters, enhancing the performance of memory access intensive tasks.
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Table of Contents
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MT7621 OVERVIEW 2
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FUNCTIONAL BLOCK DIAGRAM 2
TABLE OF CONTENTS 3
1. MIPS 1004KC PROCESSOR 5
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1.1 FEATURES 5
1.2 MEMORY MAP SUMMARY 7
1.3 INTERUPT TABLE SUMMARY 9
2. REGISTERS 11
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2.1 NOMENCLATURE 11
2.2 SYSTEM CONTROL 12
2.2.1 FEATURES 12
2.2.2 BLOCK DIAGRAM 12
2.2.3 REGISTERS 13
2.3 TIMER 41
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2.3.1 FEATURES 41
2.3.2 BLOCK DIAGRAM 42
2.3.3 REGISTERS 43
2.4 SYSTEM TICK COUNTER 48
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2.4.1 REGISTERS 48
2.5 UART LITE 50
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2.5.1 FEATURES 50
2.5.2 REGISTERS 51
2.6 PROGRAMMABLE I/O 65
2.6.1 FEATURES 65
2.6.2 BLOCK DIAGRAM 65
2.6.3 GPIO PIN MAPPING 65
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2.6.4 REGISTERS 67
2
2.7 I C CONTROLLER 79
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2.7.1 FEATURES 79
2.7.2 LIST OF REGISTERS 80
2.8 NAND FLASH INTERFACE 87
2.8.1 FEATURES 87
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2.8.2 REGISTERS 88
2.8.3 PROGRAMMING GUIDE 106
2.9 NFI ECC CONTROLLER 115
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2.9.1 FEATURES 115
2.9.2 REGISTERS 116
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2.9.3 PROGRAMMING GUIDE 130
2.10 PCM CONTROLLER 134
2.10.1 FEATURES 134
2.10.2 BLOCK DIAGRAM 134
2.10.3 LIST OF REGISTERS 136
2.10.4 PCM CONFIGURATION 152
2.11 GENERIC DMA CONTROLLER 154
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MT7621 PROGRAMMING GUIDE
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2.11.1 FEATURES 154
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2.11.2 BLOCK DIAGRAM 154
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2.11.3 PERIPHERAL CHANNEL CONNECTION 155
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2.11.4 REGISTERS 156
2.12 SPI CONTROLLER 202
2.12.1 FEATURES 202
2.12.2 BLOCK DIAGRAM 202
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2.12.3 REGISTERS 203
2.13 I2S CONTROLLER 213
2.13.1 FEATURES 213
2.13.2 BLOCK DIAGRAM 213
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2.13.3 REGISTERS 215
2.14 SPDIF TX 220
2.14.1 REGISTERS 221
2.15 MEMORY CONTROLLER 235
2.15.1 FEATURES 235
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2.15.2 REGISTERS 236
2.16 RBUS MATRIX AND QOS ARBITER 319
2.16.1 FEATURES 319
2.16.2 BLOCK DIAGRAM 319
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2.16.3 REGISTERS OF QOS CONTROL 320
2.16.4 REGISTERS OF RBUS MATRIX 325
2.17 EXTERNAL MC ARBITER 329
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2.17.1 REGISTERS 330
2.18 ANALOG MACRO CONTROL 333
2.18.1 REGISTERS 334
3. LIST 346
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4. REVISION HISTORY 349
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1. MIPS 1004Kc Processor
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1.1 Features
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8-9-stage pipeline
32-bit Address Paths
64-bit Data Paths to Caches
MIPS32 Enhanced Architecture (Release 2) Features
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– Standardized Instruction Set Architecture
– Vectored interrupts and support for an external interrupt controller
– Programmable exception vector base
– Atomic interrupt enable/disable
–
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Bit field manipulation instructions
MIPS16e Application Specific Extension
– 16 bit encodings of 32-bit instructions to improve code density
– Special PC-relative instructions for efficient loading of addresses and constants
– Data type conversion instructions (ZEB, SEB, ZEH, SEH)
– Compact jumps (JRC, JALRC)
– Stack frame set-up and tear down “macro” instructions (SAVE and RESTORE)
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MIPS MT Application Specific Extension (ASE)
– Support for 2 Virtual Processing Elements (VPEs) per CORE
– One Thread Context (TC) per VPE
Programmable L1 Cache Sizes
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– Individually configurable instruction and data caches
– 32KB I/D cache
– 4-way set associative
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– Up to 9 non-blocking loads
– Data cache supports coherent and non-coherent Write-back with write-allocation
– 32-byte cache line size, doubleword sectored - suitable for standard single-port SRAM
– Cache line locking support
– Non-blocking prefetches
– Duplicate tag array in D-cache allows coherence requests to access the cache in parallel with normal
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load/store traffic
Standard Memory Management Unit
–
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32 dual-entry MIPS32-style JTLB per VPE with variable page sizes
– JTLBs are sharable under software control
– 4-5 entry instruction TLB
– 8-entry data TLB
OCP Bus Interface Unit (BIU)
To DI
– 32b address and 64b data
– Supports bursts of 4x64b
– 8 entry write buffer - handles eviction data, intervention response, uncached, and uncached
accelerated store data
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– Simple Byte enable mode allows easier bridging to other bus standards
– Extensions for management of front side L2 cache
–
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Intervention port supports memory coherency for use in a 1004K Coherent Processing System
Multiply-Divide Unit
– Maximum issue rate of one 32x32 multiply per clock
– Early-in divide control. Minimum 11, maximum 34 clock latency on divide
Power Control
– No minimum frequency
– Support for software-controlled clock divider
– Support for extensive use of fine-grain clock gating
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EJTAG Debug Support
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– Start, stop, and single stepping control
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– Software breakpoints via the SDBBP instruction
– Optional hardware breakpoints on virtual addresses; 0, 2, or 4 instruction and 0,1, or 2 data
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breakpoints per VPE
SOC-it L2 Cache Controller
– 7-stage pipeline. (Optional 8th stage for pipelined memory arrays.)
– 32-bit address paths, 256-bit internal data paths
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– 8-way set associativity
– Cache size: 256KB
– Line Size: 32 bytes (4 doublewords)
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1004K CPU Block Diagram
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1.2 Memory Map Summary
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Start End Size Description
0 1BFFFFFF 448M DRAM Direct Map
1C000000 1DFFFFFF 32M <<Reserved>>
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1E000000 1E0000FF 256 SYSCTL
1E000100 1E0001FF 256 TIMER
1E000200 1E0002FF 256 INTCTL
1E000300 1E0003FF 256 Flash Controller (NOR/SRAM/SDRAM)
1E000400 1E0004FF 256 Rbus Matrix CTRL
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1E000500 1E0005FF 256 MIPS CNT
1E000600 1E0006FF 256 GPIO
1E000700 1E0007FF 256 S/PDIF
1E000800 1E0008FF 256 DMA_CFG_ARB
1E000900 1E0009FF 256 I2C
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1E000A00 1E000AFF 256 I2S
1E000B00 1E000BFF 256 SPI CSR
1E000C00 1E000CFF 256 UARTLITE 1
1E000D00 1E000DFF 256 UARTLITE 2
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1E000E00 1E000EFF 256 UARTLITE 3
1E000F00 1E000FFF 256 ANACTL
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1E001000 1E0017FF 2K <<Reserved>>
1E001800 1E001FFF 2K <<Reserved>>
1E002000 1E0027FF 2K PCM (up to 16 channel)
1E002800 1E002FFF 2K Generic DMA (up to 64 channel)
1E003000 1E0037FF 2K NAND Controller *(actually 1K in Module)
1E003800 1E003FFF 2K NAND_ECC Controller *(actually 3K in module)
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1E004000 1E004FFF 4K Crypto Engine
1E005000 1E005FFF 4K MEM_CTRL (DDRII/DDRIII)
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1E006000 1E006FFF 4K EXT_MC_ARB
1E007000 1E007FFF 4K HS DMA
1E008000 1E00FFFF 32K <<Reserved>>
1E010000 1E0FFFFF 960K <<Reserved>>
To DI
1E100000 1E10DFFF 56K Frame Engine (FE SRAM: 0x1E108000~0x1E10DFFF)
1E10E000 1E10FFFF 8K PCIe SRAM
1E110000 1E117FFF 32K Ethernet GMAC
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1E118000 1E11FFFF 32K ROM
1E120000 1E12FFFF 64K <<Reserved>>
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1E130000 1E137FFF 32K SDXC
1E138000 1E13FFFF 32K <<Reserved>>
1E140000 1E17FFFF 256K PCI Express
1E180000 1E1BFFFF 256K <<Reserved>>
1E1C0000 1E1FFFFF 256K USB Host (U2+U3)
1E200000 1E23FFFF 256K <<Reserved>>
1E240000 1E24FFFF 64K <<Reserved>>
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1E250000 1E7FFFFF 5824K <<Reserved>>
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1E800000 1EBFFFFF 4M PCIE Direct Access for iNIC
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1EC00000 1FBBFFFF 16128K <<Reserved>>
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1FBC0000 1FBDFFFF 128 CM_GIC
1FBE0000 1FBEFFFF 64K <<Reserved>>
1FBF0000 1FBF7FFF 32K CM_CPC
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1FBF8000 1FBFFFFF 32K CM_GCR
1FC00000 1FFFFFFF 4M ROM/SPI FLASH Direct Access
20000000 23FFFFFF 64M DRAM Re-Map
24000000 5FFFFFFF 960M <<Reserved>>
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60000000 6FFFFFFF 256M PCIE Direct Access
70000000 7FFFFFFF 256M <<Reserved>>
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1.3 Interupt Table Summary
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MIPS1004Kc
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GIC Pin5 GIC
GIC GIC
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(Local) Pin4 (Local)
All the system GIC GIC
(Local) Pin3 (Local)
interrupts are n GIC GIC
(Local) Pin2 (Local)
connected to VPE0
here. (Shared) (Local) Pin1
(GIC INT0~63)
Pin0
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SI_FDCInt, SI_PCInt, SI_TimerInt, SI_SWInt[1:0]
MT7621 Interrupt architecture
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PS: the empty part means reserved.
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2. Registers
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2.1 Nomenclature
The following nomenclature is used for register types:
RO Read Only
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WO Write Only
RW Read or Write
RC Read Clear
W1C Write One Clear
- Reserved bit
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X Undefined binary value
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2.2 System Control
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2.2.1 Features
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Provides read-only chip revision registers
Provides a window to access boot-strapping signals
Supports memory remapping configurations
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Supports software reset to each platform building block
Provides registers to determine GPIO and other peripheral pin muxing schemes
Provides some power-on-reset only test registers for software programmers
Combines miscellaneous registers (such as clock skew control, status register, memo registers, etc)
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2.2.2 Block Diagram
System Control Block
Memory Remapping
CPU Rbus Wrapper
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Boot Strapping Signals
GPIO Pin Muxing Scheme
Pin Muxing Block
System Control
Registers Per Block S/W Reset
Platform Blocks
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Cache Hit/Miss Strobes
Miscellaneous Registers
PCIe, PCM, ...
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To/From MIPS
PalmBus Interface
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Figure 2-1 System Control Block Diagram
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2.2.3 Registers
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SYSCTL Changes LOG
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Revision Date Author Change Log
0.1 2012/7/11 James Hu Initialization
m. NT
Module name: SYSCTL Base address: (+1E000000h)
Address Name Widt Register Function
h
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1E000000 CHIPID0_3 32 CHIP ID ASCII Character 0-3
1E000004 CHIPID4_7 32 CHIP ID ASCII Character 4-7
1E00000C CHIP_REV_ID 32 Chip Revision Identification
1E000010 SYSCFG 32 System Configuration Register
1E000014 SYSCFG1 32 System Configuration Register 1
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1E000018 TESTSTAT 32 Firmware Test Status
1E00001C TESTSTAT2 32 Firmware Test Status 2
1E000020 BOOT_SRAM_BA 32 Boot from SRAM base Address
SE
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1E000024 BOOT_RELEASE 32 Release CPU's reset to let CPU boot in boot from SRAM mode
1E00002C CLKCFG0 32 Clock Configuration Register 0
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1E000030 CLKCFG1 32 Clock Configuration Register 1
1E000034 RSTCTL 32 Reset Control Register
1E000038 RSTSTAT 32 Reset Status Register
1E00003C MISR_GOLDEN 32 ROM BIST MISR Golden Value
1E000040 MISR_RESULT 32 ROM BIST MISR Result Value
32
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1E000044 CUR_CLK_STS Current clock status
1E000048 PAD_UART1_GPI 32 PAD configuration of UART1 and GPIO0 groups
O0_CFG
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1E00004C PAD_UART3_I2C_ 32 PAD configuration of UART3 and I2C groups
CFG
1E000050 PAD_UART2_JTA 32 PAD configuration of UART2 and JTAG groups
G_CFG
1E000054 PAD_PERST_WDT 32 PAD configuration of PICe RST and WDT RST groups
To DI
_CFG
1E000058 PAD_RGMII2_MDI 32 PAD configuration of RGMII2 and MDIO RST groups
O_CFG
1E00005C PAD_SDXC_SPI_C 32 PAD configuration of SDXC and SPI RST groups
R E
FG
1E000060 GPIO_MODE 32 GPIO purpose selection
M
1E000068 MEMO1 32 Memory1
1E00006C MEMO2 32 Memory2
1E000070 PAD_BOPT_ESWI 32 PAD configuration of Bonding OPT and ESW INT groups
NT_CFG
1E000074 PAD_RGMII1_CFG 32 PAD configuration of RGMII1 group
1E000078 CPE_ROSC_SEL0 32
1E00007C CPE_ROSC_SEL1 32
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1E000080 CPU_CPE_CNT0 32 CPU CPE counter 0
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1E000084 CPU_CPE_CNT1 32 CPU CPE counter 1
EO
1E000088 CPU_CFG 32 CPU configuration
cn IA
1E00008C CPU_MEM_CFG 32 CPU memory delay, power down and sleep control
1E000090 FMTR_CFG0 32 Frequency meter configuration 0
1E000094 FMTR_CNT_MAX 32 Frequency meter count maximum
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1E000098 FMTR_CNT_MIN 32 Frequency meter count minimum
1E00009C FMTR_CNT_VAL 32 Frequency meter counter value
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1E000000 CHIPID0_3 CHIP ID ASCII Character 0-3 3637544
D
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CHIP_ID3 CHIP_ID2
Type RO RO
Reset 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Name CHIP_ID1 CHIP_ID0
Type RO RO
Reset 0 1 0 1 0 1 0 0 0 1 0 0 1 1 0 1
Bit(s) Name Description
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31:24 CHIP_ID3 ASCII CHIP Name Identification Character 3
23:16 CHIP_ID2 ASCII CHIP Name Identification Character 2
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15:8 CHIP_ID1 ASCII CHIP Name Identification Character 1
7:0 CHIP_ID0 ASCII CHIP Name Identification Character 0
1E000004 CHIPID4_7 CHIP ID ASCII Character 4-7 2020313
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2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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Name CHIP_ID7 CHIP_ID6
Type RO RO
Reset 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CHIP_ID5 CHIP_ID4
Type RO RO
To DI
Reset 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0
Bit(s) Name Description
31:24 CHIP_ID7 ASCII CHIP Name Identification Character 3
R E
23:16 CHIP_ID6 ASCII CHIP Name Identification Character 2
15:8 CHIP_ID5 ASCII CHIP Name Identification Character 1
M
7:0 CHIP_ID4 ASCII CHIP Name Identification Character 0
1E00000C CHIP_REV_ID Chip Revision Identification 0002010
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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Name DU
PK
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MM
G_I
EO
Y_I
D
D
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Type RO RO
Reset 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VER_ID ECO_ID
Type RO RO
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Reset 0 0 0 1 0 0 0 1
Bit(s) Name Description
17 DUMMY_ID DUMMY ID
1: Reserved
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0: Reserved
16 PKG_ID Package ID
1: A
0: N
11:8 VER_ID Chip Version ID
3:0 ECO_ID Chip ECO ID
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1E000010 SYSCFG System Configuration Register 0000000
0
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Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TEST_CODE BS_SHADOW[9:4]
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Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DR
OC DR
AM
XTAL_MODE_SE P_R AM
BS_SHADOW[3:0] _FR CHIP_MODE
L ATI _TY
OM
O PE
_EE
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Type RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit(s) Name Description
31:24 TEST_CODE Default value is from bootstrap and can be modified by software.
21:12 BS_SHADOW BS shadow register for last boot-up value
Displays a backup copy of the last bootup value
To DI
9 DRAM_FROM_EE DRAM configuration source
1: Auto detection
0: from EEPROM
8:6 XTAL_MODE_SEL XTAL mode selection
R E
0: 20 MHz, Self Oscillation mode
1: 20 MHz, Single end input
2: 20 MHz, differential input
M
3: 40 MHz, Self Oscillation mode
4: 40 MHz, Single end input
5: 40 MHz, differential input
6: 25 MHz, Self Oscillation mode
7: 25 MHz, Single end input
5 OCP_RATIO 0: 1/3
1: 1/4
4 DRAM_TYPE DDR type
1: DDR2
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0: DDR3
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3:0 CHIP_MODE A vector to set chip function/test/debug modes in non-test/debug operation.
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For more information see the Bootstrapping Pins Description in the datasheet for this
chip.
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1E000014 SYSCFG1 System Configuration Register 1 0000C10
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0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI
CP
U_
E_R
GE2_MOD GE1_MOD CT
C_
E E RL_
MO
UTI
DE
F
Type RW RW RW RW
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Reset 1 1 0 0 1 0
Bit(s) Name Description
15:14 GE2_MODE Gigabit Port #2 Mode
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Sets the interface mode on Gigabit port 2
3: RJ-45 Mode
2: Reverse MII Mode (10/100 Mbps)
1: MII Mode (10/100 Mbps)
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0: RGMII Mode (10/100/1000 Mbps)
13:12 GE1_MODE Gigabit Port #1 Mode
Sets the interface mode on Gigabit port 1.
0: RGMII Mode (10/100/1000 Mbps)
1: MII Mode (10/100 Mbps)
2: Reverse MII Mode (10/100 Mbps)
31: Reserved
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8 PCIE_RC_MODE PCIe Mode
1: Root Complex mode
ny AT
0: End Point mode
4 CPU_CTRL_UTIF CPU control and monitor UTIF interface enable
1: Enable
0: Disable
To DI
1E000018 TESTSTAT Firmware Test Status 0000000
0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TESTSTAT[31:16]
Type
M
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TESTSTAT[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 TESTSTAT Firmware Test Status register
FO
PGMT7621_V.1.0_130607 Page 16 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
NOTE: This register is reset only by a power-on reset.
US L
EO
cn IA
1E00001C TESTSTAT2 Firmware Test Status 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TESTSTAT2[31:16]
m. NT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TESTSTAT2[15:0]
Type RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 TESTSTAT2 Firmware Test Status Register 2
ccn NF NOTE: This register is reset only by a power-on reset.
1E000020 BOOT_SRAM Boot from SRAM base Address 1E18000
_BASE 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name BOOTSRAMBASE[31:16]
Type RW
Reset 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BOOTSRAMBASE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:0 BOOTSRAMBASE Boot from SRAM base address (Test mode only)
Addr_tuned =
bootsram[31:0] | oc_maddr[15:0]
ny AT
1E000024 BOOT_RELEA Release CPU's reset to let CPU boot in boot from 0000000
SE SRAM mode 0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BO
OT_
M
RE
LE
AS
E
Type RW
Reset 0
Bit(s) Name Description
FO
PGMT7621_V.1.0_130607 Page 17 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
0 BOOT_RELEASE Release CPU's command to access DRAM or CR.
US L
1: Release CPU command
EO
0: Block CPU command
cn IA
1E000028 RESERVED_C Reserved CR1 0000000
R 0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED_CR1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name RESERVED_CR1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
ccn NF Description
1E00002C CLKCFG0 Clock Configuration Register 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name RE
MP
PCI FCL
LL_
CPU_CLK_ E_C K_F
OSC_1US_DIV CF REFCLK_FDIV
@ KC
SEL LK_ FR
G_
SEL AC[
SEL
4:4]
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PE
RI_
xia E
TRGMII_C
REFCLK_FFRAC[3:0] REFCLK0_RATE CL
LK_SEL
K_S
EL
ny AT
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:30 CPU_CLK_SEL CPU clock selection.
To DI
CPU PLL is programmable.
3: XTAL clock
2: XTAL clock
1: CPU PLL
R E
0: 500MHz
29:24 OSC_1US_DIV Oscillator 1 usec Divider
Sets the maximum for the reference clock counter for either a 20 MHz or 40 MHz
M
external XTAL input. The count increments each 1usec (indicating 1 MHz), up to the
maximum, before resetting to zero. This counts the frequency of an external XTAL.
This count is used to output a 32 KHz frequency to the REFCLK0 pin.
0: Automatically generates a 1 usec system tick regardless of whether XTAL frequency
is 20 MHz or 40 MHz.
39: Default value for an external 40 MHz XTAL.
19: Default value for an external 20 MHz XTAL.
Others: Manual mode for tick generation.
23 MPLL_CFG_SEL MEMPLL parameter configuration selection
FO
PGMT7621_V.1.0_130607 Page 18 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: from CR configuration
0: follow XTAL frequncy boot strapping
US L
EO
22:18 REFCLK_FDIV Internal Clock Frequency Divider
The frequency divider used to generate the Fraction-N clock frequency.
cn IA
Valid values range from 1 to 31.
Fraction-N clock frequency = (INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
17 PCIE_CLK_SEL PCIe clock selection.
1: from GPLL 125MHz
m. NT
0: from PCIe PHY
16:12 REFCLK_FFRAC Internal Clock Fraction-N Frequency
A parameter used in conjunction with INT_CLK_FDIV to generate the Fraction-N clock
frequency.
Valid values range from 0 to 31.
Fraction-N clock Frequency = (INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
.co IDE
11:9 REFCLK0_RATE Output clock rate of reference Clock 0
7: CPU clock/8
6: Reserved
5: Internal Fraction-N_CLK/2
4: Internal Fraction-N_CLK/4
3: Reserved
2: 25 MHz
ccn NF 1: 12.5 MHz
0: Xtal clock(20/25/40 MHz by boot strap)
6:5 TRGMII_CLK_SEL TRGMII Tx clock selection
2: APLL
1: DDR PLL to DRAMC
ase O
0: 250MHz
4 PERI_CLK_SEL Peripheral Clock Source Select
1: XTAL input
@ KC
0: 50 MHz from EPLL
1E000030 CLKCFG1 Clock Configuration Register 1 67BFEF
E0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CR
SH PCI PCI PCI ET UA UA UA
YPT SPI I2S I2C
ny AT
XC_ E2_ E1_ E0_ H_ RT3 RT2 RT1
O_ _CL _CL _CL
CL CL CL CL CL _CL _CL _CL
CL K_E K_E K_E
K_E K_E K_E K_E K_E K_E K_E K_E
K_E N N N
N N N N N N N N
N
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NA GD PC TIM
SP HS
PIO MC INT DIF FE_ DM
ND MA M_ ER_
_CL _CL _CL TX_ CL A_
_CL _CL CL CL
K_E K_E K_E CL K_E CL
R E
K_E K_E K_E K_E
N N N K_E N K_E
N N N N
N N
Type RW RW RW RW RW RW RW RW RW RW
M
Reset 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
30 SHXC_CLK_EN SHXC clock control
1: Clock Enable
0: Clock Disable
29 CRYPTO_CLK_EN AUX system tick counter clock control
1: Clock Enable
FO
PGMT7621_V.1.0_130607 Page 19 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
0: Clock Disable
US L
26 PCIE2_CLK_EN PCIE2 clock control
EO
1: Clock Enable
0: Clock Disable
cn IA
25 PCIE1_CLK_EN PCIE1 clock control
1: Clock Enable
0: Clock Disable
24 PCIE0_CLK_EN PCIE0 clock control
m. NT
1: Clock Enable
0: Clock Disable
23 ETH_CLK_EN ETH clock control
1: Clock Enable
0: Clock Disable
.co IDE
21 UART3_CLK_EN UART3 clock control
1: Clock Enable
0: Clock Disable
20 UART2_CLK_EN UART2 clock control
1: Clock Enable
0: Clock Disable
19
ccn NF
UART1_CLK_EN UART1 clock control
1: Clock Enable
0: Clock Disable
18 SPI_CLK_EN SPI clock control
1: Clock Enable
ase O
0: Clock Disable
17 I2S_CLK_EN I2S clock control
1: Clock Enable
@ KC
0: Clock Disable
16 I2C_CLK_EN I2C clock control
1: Clock Enable
0: Clock Disable
15 NAND_CLK_EN NAND clock control
1: Clock Enable
0: Clock Disable
xia E
14 GDMA_CLK_EN GDMA clock control
1: Clock Enable
ny AT
0: Clock Disable
13 PIO_CLK_EN PIO clock control
1: Clock Enable
0: Clock Disable
11 PCM_CLK_EN PCM clock control
To DI
1: Clock Enable
0: Clock Disable
10 MC_CLK_EN MC clock control
1: Clock Enable
R E
0: Clock Disable
9 INT_CLK_EN INT clock control
M
1: Clock Enable
0: Clock Disable
8 TIMER_CLK_EN TIMER clock control
1: Clock Enable
0: Clock Disable
7 SPDIFTX_CLK_EN SPDIFTX clock control
1: Clock Enable
0: Clock Disable
6 FE_CLK_EN FE clock control
FO
PGMT7621_V.1.0_130607 Page 20 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: Clock Enable
0: Clock Disable
US L
EO
5 HSDMA_CLK_EN HSDMA clock control
1: Clock Enable
cn IA
0: Clock Disable
m. NT
1E000034 RSTCTL Reset Control Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name AU
CR
SD X_S PCI PCI PCI ET UA UA UA
PP YPT SPI I2S I2C
.co IDE
XC_ TC E2_ E1_ E0_ H_ RT3 RT2 RT1
E_R O_ _RS _RS _RS
RS K_ RS RS RS RS _RS _RS _RS
ST RS T T T
T RS T T T T T T T
T
T
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SP HS
ccn NF
GD PC TIM
NFI PIO MC INT DIF FE_ DM MC SY
MA M_ ER_
_RS _RS _RS _RS TX_ RS A_ M_ S_R
_RS RS RS
T T T T RS T RS RST ST
T T T
T T
Type RW RW RW RW RW RW RW RW RW RW RW
W1
C
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31 PPE_RST PPE reset control
1: Reset Assert
0: Reset Deassert
30 SDXC_RST SHXC reset control
1: Reset Assert
0: Reset Deassert
xia E
29 CRYPTO_RST Crypto engine reset control
1: Reset Assert
ny AT
0: Reset Deassert
28 AUX_STCK_RST AUX system tick counter clock control
1: Reset Assert
0: Reset Deassert
26 PCIE2_RST PCIE2 reset control
To DI
1: Reset Assert
0: Reset Deassert
25 PCIE1_RST PCIE1 reset control
1: Reset Assert
R E
0: Reset Deassert
24 PCIE0_RST PCIE0 reset control
M
1: Reset Assert
0: Reset Deassert
23 ETH_RST ETH reset control
1: Reset Assert
0: Reset Deassert
21 UART3_RST UART3 reset control
1: Reset Assert
0: Reset Deassert
20 UART2_RST UART2 reset control
FO
PGMT7621_V.1.0_130607 Page 21 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: Reset Assert
0: Reset Deassert
US L
EO
19 UART1_RST UART1 reset control
1: Reset Assert
cn IA
0: Reset Deassert
18 SPI_RST SPI reset control
1: Reset Assert
0: Reset Deassert
m. NT
17 I2S_RST I2S reset control
1: Reset Assert
0: Reset Deassert
16 I2C_RST I2C reset control
1: Reset Assert
.co IDE
0: Reset Deassert
15 NFI_RST NFI reset control
1: Reset Assert
0: Reset Deassert
14 GDMA_RST GDMA reset control
1: Reset Assert
0: Reset Deassert
ccn NF
13 PIO_RST PIO reset control
1: Reset Assert
0: Reset Deassert
11 PCM_RST PCM reset control
ase O
1: Reset Assert
0: Reset Deassert
10 MC_RST MC reset control
@ KC
1: Reset Assert
0: Reset Deassert
9 INT_RST INT reset control
1: Reset Assert
0: Reset Deassert
8 TIMER_RST TIMER reset control
1: Reset Assert
xia E
0: Reset Deassert
7 SPDIFTX_RST SPDIFTX reset control
ny AT
1: Reset Assert
0: Reset Deassert
6 FE_RST FE reset control
1: Reset Assert
0: Reset Deassert
To DI
5 HSDMA_RST HSDMA reset control
1: Reset Assert
0: Reset Deassert
2 MCM_RST MCM(MT7530) reset control
R E
1: Reset Assert
0: Reset Deassert
0 SYS_RST Whole System Reset Control
M
1: Whole System Reset
0: NA
1E000038 RSTSTAT Reset Status Register C003000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO
PGMT7621_V.1.0_130607 Page 22 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Name WD
WD
US L
T2S
T2R
EO
YS
ST WDTRSTPD
RS
O_
cn IA
T_E
EN
N
Type RW RW RW
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name SW WD
SYS RS
RST T
Type W1 W1
C C
Reset 0 0
.co IDE
Bit(s) Name Description
31 WDT2SYSRST_EN WDT reset apply to System Reset
Enables watchdog timeout to trigger a system reset.
1: Enable
0: Disable
30
ccn NF
WDT2RSTO_EN WDT reset apply to watch dog reset pin out.
1: Enable
0: Disable
29:16 WDTRSTPD Watchdog Reset Output Low Period
Controls the WDT reset output low period. For example:
ase O
If the pin share mode was set correctly and WDT2RSTO_EN=1,
When WDTRSTPD= 0, you can see duration of 1 usec low on the WDT reset output
pin.
When WDTRSTPD= 3, you can see duration of 4 usec low on the WDT reset output
@ KC
pin.
(unit: 1 usec)
2 SWSYSRST Software System Reset
Indicates when software has reset the chip by writing to the RSTSYS bit in RSTCTL.
NOTE: This register is reset only by a power on reset.
0: Has no effect.
1: Clears this bit.
xia E
1 WDRST Watchdog Reset
Indicates when the watchdog timer has reset the chip.
ny AT
NOTE: This register is reset only by power-on reset.
0: Has no effect.
1: Clears this bit.
To DI
1E00003C MISR_GOLDE ROM BIST MISR Golden Value 0000000
N 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name MISR_GOLDEN[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MISR_GOLDEN[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 MISR_GOLDEN ROM BIST golden value
FO
PGMT7621_V.1.0_130607 Page 23 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E000040 MISR_RESUL ROM BIST MISR Result Value 0000000
T 0
cn IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MISR_RESULT[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MISR_RESULT[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:0 MISR_RESULT ROM BIST result
1E000044 CUR_CLK_ST Current clock status 00030A0
S 1
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SA
ME
CUR_OCP_RATIO
_FR
EQ
ase O
Type RO RO
Reset 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name CUR_CPU_FDIV CUR_CPU_FFRAC
Type RO RO
Reset 0 1 0 1 0 0 0 0 0 1
Bit(s) Name Description
20 SAME_FREQ SYS_CLK and DRAM_clk are same frequency.
xia E
18:16 CUR_OCP_RATIO Current CPU_OCP_RATIO(SYS:CPU)
4: 1:4
ny AT
3: 1:3
12:8 CUR_CPU_FDIV Current divider number of CPU frequency
4:0 CUR_CPU_FFRAC Current fraction number of CPU frequency.
To DI
1E000048 PAD_UART1_ PAD configuration of UART1 and GPIO0 groups 0A180A1
GPIO0_CFG 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name UA UA
UA
UA
UART1_R UART1_E4 RT1
UART1_TDSEL RT1 RT1 RT1
DSEL _E2 _S
M
_PU _PD _SR
MT
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPI
GPI GPI GPI
GPIO0_RD GPIO0_E4 O0_
GPIO0_TDSEL O0_ O0_ O0_
SEL _E2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
FO
PGMT7621_V.1.0_130607 Page 24 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Reset 0 0 1 0 1 0 0 1 1 0 0 0
US L
EO
Bit(s) Name Description
cn IA
29:28 UART1_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
m. NT
27:24 UART1_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
.co IDE
21:20 UART1_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
1: 4mA
0: 2mA
19 UART1_PU 75K pull-up resistor control.
1: Enable
ccn NF 0: Disable
18 UART1_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 UART1_SMT RX input buffer schmit trigger hysteresis control enable.
ase O
1: Enable
0: Disable
16 UART1_SR Output Slew Rate Control.
@ KC
1: Slower slew.
0: No slew rate controlled.
13:12 GPIO0_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
xia E
11:8 GPIO0_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
ny AT
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
5:4 GPIO0_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
To DI
1: 4mA
0: 2mA
3 GPIO0_PU 75K pull-up resistor control.
1: Enable
R E
0: Disable
2 GPIO0_PD 75K pull-down resistor control.
M
1: Enable
0: Disable
1 GPIO0_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
0 GPIO0_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
FO
PGMT7621_V.1.0_130607 Page 25 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E00004C PAD_UART3_I PAD configuration of UART3 and I2C groups 0A140A1
cn IA
2C_CFG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name UA UA
UA
UA
UART3_R UART3_E4 RT3
m. NT
UART3_TDSEL RT3 RT3 RT3
DSEL _E2 _S
_PU _PD _SR
MT
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I2C
.co IDE
I2C_RDSE I2C I2C I2C
I2C_TDSEL I2C_E4_E2 _S
L _PU _PD _SR
MT
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 0 0 0 0
Bit(s) Name Description
29:28
ccn NF
UART3_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 UART3_TDSEL TX duty select
ase O
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
@ KC
0: For 1.8V
21:20 UART3_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
1: 4mA
0: 2mA
19 UART3_PU 75K pull-up resistor control.
xia E
1: Enable
0: Disable
ny AT
18 UART3_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 UART3_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
To DI
0: Disable
16 UART3_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
R E
13:12 I2C_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
M
3: For 1.8V
0: For 3.3V
11:8 I2C_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
5:4 I2C_E4_E2 TX Driving Strength Control.
3: 8mA
FO
PGMT7621_V.1.0_130607 Page 26 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
2: 6mA
1: 4mA
US L
EO
0: 2mA
3 I2C_PU 75K pull-up resistor control.
cn IA
1: Enable
0: Disable
2 I2C_PD 75K pull-down resistor control.
1: Enable
m. NT
0: Disable
1 I2C_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
0 I2C_SR Output Slew Rate Control.
.co IDE
1: Slower slew.
0: No slew rate controlled.
1E000050 PAD_UART2_ PAD configuration of UART2 and JTAG groups 0A140A1
JTAG_CFG 4
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name JTA
JTA JTA JTA
JTAG_RD JTAG_E4_ G_
JTAG_TDSEL G_ G_ G_
SEL E2 SM
PU PD SR
T
ase O
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name UA UA
UA
UA
UART2_R UART2_E4 RT2
UART2_TDSEL RT2 RT2 RT2
DSEL _E2 _S
_PU _PD _SR
MT
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 0 1 0 0
xia E
Bit(s) Name Description
29:28 JTAG_RDSEL RX duty select
ny AT
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 JTAG_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
To DI
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
21:20 JTAG_E4_E2 TX Driving Strength Control.
R E
3: 8mA
2: 6mA
1: 4mA
M
0: 2mA
19 JTAG_PU 75K pull-up resistor control.
1: Enable
0: Disable
18 JTAG_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 JTAG_SMT RX input buffer schmit trigger hysteresis control enable.
FO
PGMT7621_V.1.0_130607 Page 27 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: Enable
0: Disable
US L
EO
16 JTAG_SR Output Slew Rate Control.
1: Slower slew.
cn IA
0: No slew rate controlled.
13:12 UART2_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
m. NT
3: For 1.8V
0: For 3.3V
11:8 UART2_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
.co IDE
0: For 1.8V
5:4 UART2_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
1: 4mA
0: 2mA
3 UART2_PU 75K pull-up resistor control.
ccn NF
1: Enable
0: Disable
2 UART2_PD 75K pull-down resistor control.
1: Enable
0: Disable
ase O
1 UART2_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
@ KC
0: Disable
0 UART2_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
xia E
1E000054 PAD_PERST_ PAD configuration of PICe RST and WDT RST groups 0A180A1
WDT_CFG 8
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PE PE PE PE
PERST_R PERST_E4 RS RS RS RS
PERST_TDSEL
DSEL _E2 T_P T_P T_S T_S
U D MT R
Type RW RW RW RW RW RW RW
To DI
Reset 0 0 1 0 1 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WDT_RDS WDT_E4_E
WD WD WD WD
WDT_TDSEL T_P T_P T_S T_S
EL 2
R E
U D MT R
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 1 0 0 0
M
Bit(s) Name Description
29:28 PERST_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 PERST_TDSEL TX duty select
FO
PGMT7621_V.1.0_130607 Page 28 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
US L
EO
10: For3.3V
0: For 1.8V
cn IA
21:20 PERST_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
1: 4mA
0: 2mA
m. NT
19 PERST_PU 75K pull-up resistor control.
1: Enable
0: Disable
18 PERST_PD 75K pull-down resistor control.
1: Enable
.co IDE
0: Disable
17 PERST_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
16 PERST_SR Output Slew Rate Control.
1: Slower slew.
ccn NF 0: No slew rate controlled.
13:12 WDT_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
ase O
11:8 WDT_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
@ KC
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
5:4 WDT_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
1: 4mA
0: 2mA
xia E
3 WDT_PU 75K pull-up resistor control.
1: Enable
ny AT
0: Disable
2 WDT_PD 75K pull-down resistor control.
1: Enable
0: Disable
1 WDT_SMT RX input buffer schmit trigger hysteresis control enable.
To DI
1: Enable
0: Disable
0 WDT_SR Output Slew Rate Control.
1: Slower slew.
R E
0: No slew rate controlled.
M
1E000058 PAD_RGMII2_ PAD configuration of RGMII2 and MDIO RST groups 0A210A2
MDIO_CFG 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
RG RG RG
RGMII2_R RGMII2_E4 MII2
RGMII2_TDSEL MII2 MII2 MII2
DSEL _E2 _S
_PU _PD _SR
MT
FO
PGMT7621_V.1.0_130607 Page 29 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW RW RW RW RW RW RW
Reset
US L
0 0 1 0 1 0 1 0 0 0 0 1
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MDI MDI
MDI
MDI
cn IA
MDIO_RDS MDIO_E4_ O_
MDIO_TDSEL O_ O_ O_
EL E2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 1 0 0 0 0 1
m. NT
Bit(s) Name Description
29:28 RGMII2_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
.co IDE
3: For 1.8V
0: For 3.3V
27:24 RGMII2_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
ccn NF
21:20 RGMII2_E4_E2 TX Driving Strength Control. (CID)
3: 16mA
2: 12mA
1: 8mA
0: 4mA
ase O
19 RGMII2_PU 75K pull-up resistor control.
1: Enable
0: Disable
@ KC
18 RGMII2_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 RGMII2_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
xia E
16 RGMII2_SR Output Slew Rate Control. (CID)
1: Slower slew.
0: No slew rate controlled.
ny AT
13:12 MDIO_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
To DI
11:8 MDIO_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
R E
5:4 MDIO_E4_E2 TX Driving Strength Control.
3: 8mA
M
2: 6mA
1: 4mA
0: 2mA
3 MDIO_PU 75K pull-up resistor control.
1: Enable
0: Disable
2 MDIO_PD 75K pull-down resistor control.
1: Enable
0: Disable
FO
PGMT7621_V.1.0_130607 Page 30 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1 MDIO_SMT RX input buffer schmit trigger hysteresis control enable.
US L
1: Enable
EO
0: Disable
0 MDIO_SR Output Slew Rate Control.
cn IA
1: Slower slew.
0: No slew rate controlled.
m. NT
1E00005C PAD_SDXC_S PAD configuration of SDXC and SPI RST groups 0A210A1
PI_CFG 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SD
.co IDE
SD SD SD
SDXC_RD SDXC_E4_ XC_
SDXC_TDSEL XC_ XC_ XC_
SEL E2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 1 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPI
SPI_RDSE SPI SPI SPI
ccn NF SPI_TDSEL SPI_E4_E2 _S
L _PU _PD _SR
MT
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 1 0 0 0
ase O
Bit(s) Name Description
29:28 SDXC_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
@ KC
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 SDXC_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
xia E
0: For 1.8V
21:20 SDXC_E4_E2 TX Driving Strength Control.
3: 8mA
ny AT
2: 6mA
1: 4mA
0: 2mA
19 SDXC_PU 75K pull-up resistor control.
1: Enable
To DI
0: Disable
18 SDXC_PD 75K pull-down resistor control.
1: Enable
0: Disable
R E
17 SDXC_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
M
16 SDXC_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
13:12 SPI_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
FO
PGMT7621_V.1.0_130607 Page 31 of 349
[email protected],time=2014-09-19 10:42:07,ip=218.17.61.76,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=ASEC International (H.K.) Limited 亞矽(香港)_RLT
MT7621 PROGRAMMING GUIDE
Y
NL
11:8 SPI_TDSEL TX duty select
US L
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
EO
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
cn IA
0: For 1.8V
5:4 SPI_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
m. NT
1: 4mA
0: 2mA
3 SPI_PU 75K pull-up resistor control.
1: Enable
0: Disable
2 SPI_PD 75K pull-down resistor control.
.co IDE
1: Enable
0: Disable
1 SPI_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
0 SPI_SR Output Slew Rate Control.
ccn NF
1: Slower slew.
0: No slew rate controlled.
ase O
1E000060 GPIO_MODE GPIO purpose selection 0004D42
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Name ES
WIN
SDXC_MO
T_ SPI_MODE
DE
MO
DE
Type RW RW RW
Reset 0 0 1 0 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG UA
JTA I2C
MII2 MII1 RT1
ny AT
MDIO_MO PERST_M WDT_MOD G_ UART2_M UART3_M _M
_M _M _M
DE ODE E MO ODE ODE OD
OD OD OD
DE E
E E E
Type RW RW RW RW RW RW RW RW RW RW
Reset 1 1 0 1 0 1 0 0 0 0 1 0 1 1 0
To DI
Bit(s) Name Description
20 ESWINT_MODE Ether switch interrupt GPIO mode
1: GPIO
R E
0: Ether switch interrupt
19:18 SDXC_MODE SDXC GPIO mode
3: NAND
M
2: NAND
1: GPIO
0: SDXC
17:16 SPI_MODE SPI GPIO mode
3: NAND
2: NAND
1: GPIO
0: SPI
15 RGMII2_MODE RGMII2 GPIO mode
FO
PGMT7621_V.1.0_130607 Page 32 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: GPIO
0: RGMII2
US L
EO
14 RGMII1_MODE RGMII1 GPIO mode
1: GPIO
cn IA
0: RGMII1
13:12 MDIO_MODE MDC/MDIO GPIO mode
3: GPIO
2: GPIO
m. NT
1: GPIO
0: MDIO
11:10 PERST_MODE PCIe reset GPIO mode
3: Reference clock
2: Reference clock
1: GPIO
.co IDE
0: PCIe reset
9:8 WDT_MODE Watch dog timeout GPIO mode
3: Reference clock
2: Reference clock
1: GPIO
0: Watch dog
7 JTAG_MODE JTAG GPIO mode
ccn NF
1: GPIO
0: JTAG
6:5 UART2_MODE UART2 GPIO mode
3: GPIO
2: PCM
ase O
1: GPIO
0: UART2
4:3 UART3_MODE UART3 GPIO mode
@ KC
3: SPDIF
2: I2S
1: GPIO
0: UART3
2 I2C_MODE I2C GPIO mode
1: GPIO
0: I2C
xia E
1 UART1_MODE UART1 GPIO mode
1: GPIO
ny AT
0: UART1
1E000068 MEMO1 Memory1 0000000
To DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MEMO1[31:16]
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO1[15:0]
M
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 MEMO1 Memory1
FO
PGMT7621_V.1.0_130607 Page 33 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E00006C MEMO2 Memory2 0000000
US L
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name MEMO2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name MEMO2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:0 MEMO2 Memory2
1E000070 PAD_BOPT_E PAD configuration of Bonding OPT and ESW INT 0A000A0
SWINT_CFG groups 0
Bit 31
ccn NF
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BO
BO BO BO
BOPT_RD BOPT_E4_ PT_
BOPT_TDSEL PT_ PT_ PT_
SEL E2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
ase O
Reset 0 0 1 0 1 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ES
@ KC
ES ES ES
ESW_RDS ESW_E4_E W_
ESW_TDSEL W_ W_ W_
EL 2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
29:28 BOPT_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
ny AT
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 BOPT_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
To DI
10: For3.3V
0: For 1.8V
21:20 BOPT_E4_E2 TX Driving Strength Control.
3: 8mA
R E
2: 6mA
1: 4mA
0: 2mA
M
19 BOPT_PU 75K pull-up resistor control.
1: Enable
0: Disable
18 BOPT_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 BOPT_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
FO
PGMT7621_V.1.0_130607 Page 34 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
0: Disable
US L
16 BOPT_SR Output Slew Rate Control.
EO
1: Slower slew.
0: No slew rate controlled.
cn IA
13:12 ESW_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
m. NT
0: For 3.3V
11:8 ESW_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
.co IDE
5:4 ESW_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
1: 4mA
0: 2mA
3 ESW_PU 75K pull-up resistor control.
ccn NF 1: Enable
0: Disable
2 ESW_PD 75K pull-down resistor control.
1: Enable
0: Disable
ase O
1 ESW_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
@ KC
0 ESW_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
1E000074 PAD_RGMII1_ PAD configuration of RGMII1 group 0000000
xia E
CFG 5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ny AT
Name RGMII1_RDSEL RGMII1_TDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RMI RG
To DI
MII1
RGMII1_DRVP RGMII1_DRVN RGMII1_RTT I1_ MII1
_PD
PD _SR
B
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1
R E
Bit(s) Name Description
M
25:20 RGMII1_RDSEL RX duty select
RDSEL[1:0]: Input buffer duty high when asserted (high pulse width adjustment)
RDSEL[3:2]: Input buffer duty low when asserted(low pulse width adjustment)
RDSEL4: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL5: Level shifter duty low when asserted (low pulse width adjustment)
DDR3:
RDSEL[5:0]=[000000]
DDR2:
RDSEL[5:0]=[000001]
FO
PGMT7621_V.1.0_130607 Page 35 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
19:16 RGMII1_TDSEL TX duty select
US L
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
EO
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
15:12 RGMII1_DRVP GDDR3/DDR2 Pull-Up Driving Strength Control.
cn IA
00000: weakest. 11111: strongest.
Default(Typical):
GDDR3/POD18:DRVP[3:0]=[0100] (90 Ohm)
DDR2/SSTL18: DRVP[3:0]=[1110] (40 Ohm)
m. NT
DDR3/SSTL15: DRVP[3:0]=[1111] (40 Ohm)
3: Strongest.
0: Weakest.
11:8 RGMII1_DRVN GDDR3/DDR2 Pull-Down Driving Strength Control.
00000: weakest. 11111: strongest.
Default(Typical):
.co IDE
GDDR3/POD18:DRVN[3:0]=[1110] (40 Ohm)
DDR2/SSTL18: DRVN[3:0]=[1110] (40 Ohm)
DDR3/SSTL15: DRVN[3:0]=[1111] (40 Ohm)
3: Strongest.
0: Weakest.
6:4 RGMII1_RTT GDDR3(POD18)/DDR2(SSTL18) On-Die-Termination.
*Suggest to turn-off RTT[2:0] when not in read mode for power saving.
ccn NF GDDR3(POD18)
1.Comply to JESD8-19(POD18) for ODT pull-up 60/120/240 ohm requirement
2.Comply to GDDR3-SDRAM requirement
DDR2(SSTL18)
Follow JESD79-2B EMRS(1) Programming for Address Field [A6,A2]
ase O
Supported all range [A6,A2] ODT setting.
GDDR3 mode:
RTT[2:0]=[110], GDDR3 ODT pull-up 60ohm (or [100])
@ KC
RTT[2:0]=[001], GDDR3 ODT pull-up 120ohm
RTT[2:0]=[010], GDDR3 ODT pull-up 240ohm
DDR2 mode:
RTT[2:0]=[000], ODT disable,Default for DDR/LVTTL mode.
RTT[2:0]=[001], DDR2 ODT 75ohm
RTT[2:0]=[010], DDR2 ODT 150ohm
xia E
RTT[2:0]=[011], DDR2 ODT 50ohm
ny AT
DDR3 mode:
RTT[2:0]=[000], ODT disable,Default for DDR/LVTTL mode.
RTT[2:0]=[001], DDR2 ODT 60ohm
RTT[2:0]=[010], DDR2 ODT 120ohm
RTT[2:0]=[100], DDR2 ODT 40ohm
2 RGMII1_PDB 75K pull-down resistor control. Low activiate.
To DI
GDDR3/DDR2/DDR1 mode, PDB=1 to disable 75K pull-down resistors.
1: Disable
0: Enable
1 RMII1_PD GDDR3/DDR2/DDR input buffer Power Down mode.High asserted. PD=1, O=0.
R E
At LVTTL mode, set IE=0,PD=1
At GDDR3/DDR2/DDR1 power down mode, set IE=0, PD=1
1: Enable
M
0: Disable
0 RGMII1_SR Output Slew Rate Control. High asserted.
1: Slower slew.
0: No slew rate controlled.
1E000078 CPE_ROSC_S 0000000
FO
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MT7621 PROGRAMMING GUIDE
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EL0 0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name CPE_ROSC_SEL0[31:16]
Type RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CPE_ROSC_SEL0[15:0]
Type RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CPE_ROSC_SEL0 CPE ROSC cell selection bit 31 ~ 0
.co IDE
1E00007C CPE_ROSC_S 0000000
EL1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CPE_ROSC_SEL1[31:16]
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CPE_ROSC_SEL1[15:0]
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
31:0 CPE_ROSC_SEL1 CPE ROSC cell selection bit 63 ~ 32
1E000080 CPU_CPE_CN CPU CPE counter 0 0000000
T0 0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CPU_DFD_CNT0[31:16]
ny AT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CPU_DFD_CNT0[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:0 CPU_DFD_CNT0 CPU DFD counter value bit 31 ~ 0
R E
M
1E000084 CPU_CPE_CN CPU CPE counter 1 0000000
T1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CPU_DFD_CNT1
FO
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MT7621 PROGRAMMING GUIDE
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Type RO
Reset
US L
0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
cn IA
7:0 CPU_DFD_CNT1 CPU DFD counter value bit 39 ~ 32
m. NT
1E000088 CPU_CFG CPU configuration 55AA002
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MBIST_BKGND
Type
.co IDE
RW
Reset 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
SI_
_R
IT_ SY
CM_DFT_T W_
TOI NC
ARGET SW
TU TX_
_TG
ccn NF EN
R
Type RW RW RW RW
Reset 1 0 0 0 1
Bit(s) Name Description
ase O
31:16 MBIST_BKGND CPU MBISTA background pattern
5:4 CM_DFT_TARGET CM default target
@ KC
2: IOCU
0: Memory
2 RG_RW_SW_TGR SW trigger DFD counter to start
1: Enable
0: Disable
1 IT_TOITU CM arbitraction
1: DRAM access priority - favor CPU cores, but RRB between two cores
xia E
0: DRAM access priority - CPU core and IOCU master port RRB
0 SI_SYNCTX_EN Bus support OCP SYNC command or not
ny AT
1: Enable
0: Disable
1E00008C CPU_MEM_CF CPU memory delay, power down and sleep control 0000000
To DI
G A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CP
R E
E_R
CPE_ROS
OS CPE_ROSC_OUT
C_SEL2
C_E
M
N
Type RW RW RO
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CP
CP
U_
U_
RA CPU_L2_D CPU_L1_D
RA
M_ EL_SEL EL_SEL
M_
SLE
PD
EP
FO
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MT7621 PROGRAMMING GUIDE
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Type RW RW RW RW
Reset
US L
0 0 1 0 1 0
EO
Bit(s) Name Description
cn IA
31 CPE_ROSC_EN CPE ROSC enable
1: Enable
0: Disable
30:29 CPE_ROSC_SEL2 CPE ROSC cell selection bit 65 ~ 64
m. NT
27:24 CPE_ROSC_OUT CPE ROSC output
15 CPU_RAM_PD CPU RAM power down enable
1: Enable
0: Disable
.co IDE
14 CPU_RAM_SLEEP CPU RAM sleep enable
1: Enable
0: Disable
3:2 CPU_L2_DEL_SEL CPU L2 cache RAM delay selection
1:0 CPU_L1_DEL_SEL
ccn NF CPU L1 cache RAM delay selection
1E000090 FMTR_CFG0 Frequency meter configuration 0 0000000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name FMTR_CNT_LMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FM
FM
TR_
FMTR_CK TR_
FMTR_CK_SEL CN
_DIV RS
T_E
T
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 1
xia E
Bit(s) Name Description
ny AT
31:16 FMTR_CNT_LMT Freq. meter counter limitation
15:12 FMTR_CK_SEL Freq. meter DUT clock selection
10: CPLL monitor clock
9: DDRPLL4 monitor clock
8: DDRPLL3 monitor clock
To DI
7: DDRPLL2 monitor clock
6: DDRPLL1 monitor clock
5: PCIe1 clock
4: PCIe clock
3: CPU clock
R E
2: GMPLL clock
1: APLL clock
0: XTAL clock
M
9:8 FMTR_CK_DIV Freq. meter clock divider selection
3: divided by 40
2: divided by 40
1: divided by 10
0: no divided
4 FMTR_RST Reset freq. meter
1: Reset
0: Not reset
FO
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MT7621 PROGRAMMING GUIDE
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0 FMTR_CNT_EN Freq. meter counter enable
US L
1: Enable
EO
0: Disable
cn IA
1E000094 FMTR_CNT_M Frequency meter count maximum 0000000
AX 0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FMTR_CNT_MAX[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name FMTR_CNT_MAX[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 FMTR_CNT_MAX Freq. meter counter maximum value
ccn NF
1E000098 FMTR_CNT_M Frequency meter count minimum 0000000
IN 0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FMTR_CNT_MAX[31:16]
Type RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FMTR_CNT_MAX[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:0 FMTR_CNT_MAX Freq. meter counter minimum value
ny AT
1E00009C FMTR_CNT_V Frequency meter counter value 0000000
AL 0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FMTR_CNT_VAL[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name FMTR_CNT_VAL[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 FMTR_CNT_VAL Freq. meter counter final value
FO
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MT7621 PROGRAMMING GUIDE
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2.3 Timer
EO
2.3.1 Features
cn IA
Independent 1usec tick pre-scale for each timer.
Independent interrupts for each timer.
Two general-purpose timers and a watchdog timer. Watchdog timer resets system on time-out.
m. NT
Timer Modes
Periodic
In periodic mode, the timer counts down to zero from the limited value. An interrupt is generated when
the count is zero. After reaching zero, the limited value is reloaded into the timer and the timer counts
.co IDE
down again. A limited value of zero disables the timer.
Timeout
In timeout mode, the timer counts down to zero from the limited value. An interrupt is generated when
the count is zero. In this mode, the ENABLE bit is reset when the timer reaches zero, stopping the
counter.
Watchdog
ccn NF
In watchdog mode, the timer counts down to zero from the limited value. If the load value is not reloaded
or the timer is not disabled before the count is zero, the chip will be reset. When this occurs, every
register in the chip is reset except the watchdog reset status bit WDRST in the RSTSTAT register in the
ase O
system control block; it remains set to alert firmware of the timeout event when it re-executes its
bootstrap.
@ KC
xia E
ny AT
To DI
R E
M
FO
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MT7621 PROGRAMMING GUIDE
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2.3.2 Block Diagram
EO
Timer 0
cn IA
Limited Value Prescale
m. NT
Counter Mode Control
Timer 0 Interrupt
Timer 1 Interrupt
Watchdog Timer (Timer 1)
Interrupt
Control
.co IDE
Limited Value Prescale
Counter Mode Control
Timer 2
ccn NF Watchdog Timeout
Limited Value Prescale
APBus Signals
Counter Mode Control
ase O
@ KC
Figure 2-2 Timer Block Diagram
xia E
ny AT
To DI
R E
M
FO
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MT7621 PROGRAMMING GUIDE
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2.3.3 Registers
EO
cn IA
Address Name Widt Register Function
h
1E000100 TGLB_REG 32 RISC Global Control Register
m. NT
1E000110 T0CTL_REG 32 RISC Timer 0 Control Register
1E000114 T0LMT_REG 32 RISC Timer 0 Limit Register
1E000118 T0_REG 32 RISC Timer 0 Register
1E000120 WDTCTL_REG 32 Watch Dog Timer Control Register
1E000124 WDTLMT_REG 32 Watch Dog Timer Limit Register
.co IDE
1E000128 WDT_REG 32 Watch Dog Timer Register
1E000130 T1CTL_REG 32 RISC Timer 1 Control Register
1E000134 T1LMT_REG 32 RISC Timer 1 Limit Register
1E000138 ccn NF T1_REG 32 RISC Timer 1 Register
1E000100 TGLB_REG RISC Global Control Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name RESV1[20:5]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WD WD
T1R T0R T1I T0I
RESV1[4:0] TR RESV0 TIN
ST ST NT NT
ST T
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
31:11 RESV1 Reserved
ny AT
10 T1RST Timer 1 reset
1: to reset timer 1 to T1LMT value
9 WDTRST Watch dog timer reset
1: to reset watch dog timer to WDTLMT value
8 T0RST Timer 0 reset
To DI
1: to reset timer 0 to T0LMT value
7:3 RESV0 Reserved
2 T1INT Timer 1 interrupt status
R E
1 WDTINT Watch dog timer interrupt status
0 T0INT Timer 0 interrupt status
M
1E000110 T0CTL_REG RISC Timer 0 Control Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name T0PRES
Type RW
FO
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MT7621 PROGRAMMING GUIDE
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Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name T0E T0A
RESV2 RESV1 RESV0
N L
cn IA
Type RW RW RW RW DC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
31:16 T0PRES Timer 0 count down tick pre-scale. Unit is 1u second.
15:8 RESV2 Reserved
7 T0EN Timer 0 count down enable
6:5 RESV1 Reserved
.co IDE
4 T0AL Timer 0 auto load enable
1: Enable
0: Disable
3:0 RESV0 Reserved
ccn NF
1E000114 T0LMT_REG RISC Timer 0 Limit Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type
ase O
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0LMT
@ KC
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 T0LMT Timer 0 Limit.
xia E
When T0AL is set to 1, T0LMT will be loaded into timer 0 when timer 0 is enabled or
when count down to 0.
ny AT
1E000118 T0_REG RISC Timer 0 Register 0000000
0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0
Type RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 T0 RISC down-count timer 0
FO
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MT7621 PROGRAMMING GUIDE
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1E000120 WDTCTL_RE Watch Dog Timer Control Register 0000000
US L
EO
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name WDTPRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name WD
WD
RESV2 TE RESV1 RESV0
TAL
N
Type RW RW RW RW DC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:16 WDTPRES Watch dog timer count down tick pre-scale. Unit is 1u second.
15:8 RESV2 Reserved
7 WDTEN Watch dog timer count down enable
6:5 RESV1 Reserved
4
ccn NF
WDTAL Watch dog timer auto load enable
1: Enable
0: Disable
3:0 RESV0 Reserved
ase O
1E000124 WDTLMT_RE Watch Dog Timer Limit Register 0000000
@ KC
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
xia E
Name WDTLMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 WDTLMT Watch dog timer Limit.
When WDTAL is set to 1, WDTLMT will be loaded into watch dog timer when watch
To DI
dog timer is enabled or when count down to 0.
R E
1E000128 WDT_REG Watch Dog Timer Register 0000000
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WDT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
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Bit(s) Name Description
US L
31:16 RESV0 Reserved
EO
15:0 WDT watch dog timer.
cn IA
1E000130 T1CTL_REG RISC Timer 1 Control Register 0000000
m. NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name T1PRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T1E T1A
RESV2 RESV1 RESV0
N L
Type RW RW RW RW DC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
31:16 T1PRES Timer 1 count down tick pre-scale. Unit is 1u second.
15:8 RESV2 Reserved
7 T1EN Timer 1 count down enable
6:5 RESV1 Reserved
ase O
4 T1AL Timer 1 auto load enable
3:0 RESV0 Reserved
@ KC
1E000134 T1LMT_REG RISC Timer 1 Limit Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
xia E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Name T1LMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
31:16 RESV0 Reserved
15:0 T1LMT Timer 1 Limit.
When T1AL is set to 1, T1LMT will be loaded into timer 1 when timer 1 is enabled or
when count down to 0.
R E
M
1E000138 T1_REG RISC Timer 1 Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO
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MT7621 PROGRAMMING GUIDE
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Name T1
US L
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 T1 RISC down-count timer 1
m. NT
.co IDE
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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MT7621 PROGRAMMING GUIDE
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US L
2.4 System Tick Counter
EO
2.4.1 Registers
cn IA
Address Name Width Register Function
m. NT
1E000500 STCK_CNT_CFG 32 MIPS Configuration
1E000504 CMP_CNT 32 MIPS Compare
Sets the cutoff point for the free run counter (MIPS counter). If the free run
counter equals the compare counter, then the timer circuit generates an interrupt.
The interrupt remains active until the compare counter is written again.
.co IDE
1E000508 CNT 32 MIPS Counter
The MIPS counter (free run counter) increases by 1 every 20 us (50 KHz). The
counter continues to count until it reaches the value loaded into CMP_CNT.
1E000500 STCK_CNT_CFG MIPS Configuration 00000000
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[29:14]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name RESV[13:0]
EXT_ST CNT_E
K_EN N
Type RW RW RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:2 RESV
1 EXT_STK_EN External System Tick Enable - Selects the system tick source.
0: Use the MIPS internal timer interrupts.
xia E
1: Use the external timer interrupt from an external MIPS counter.
0 CNT_EN Counter Enable - Enable the free run counter (MIPS counter).
ny AT
0: Disable
1: Enable
1E000504 CMP_CNT MIPS Compare 00000000
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMP_CNT
M
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV
15:0 CMP_CNT Compare Count
FO
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MT7621 PROGRAMMING GUIDE
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EO
1E000508 CNT MIPS Counter 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name RESV
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:16 RESV
15:0 CNT MIPS Counter
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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MT7621 PROGRAMMING GUIDE
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2.5 UART Lite
EO
2.5.1 Features
cn IA
2-pin UART
16550-compatible register set, except for Divisor Latch register
5-8 data bits
m. NT
1-2 stop bits (1 or 2 stop bits are supported with 5 data bits)
Even, odd, stick or no parity
All standard baud rates up to 345600 b/s
16-byte receive buffer
16-byte transmit buffer
.co IDE
Receive buffer threshold interrupt
Transmit buffer threshold interrupt
False start bit detection in asynchronous mode
Internal diagnostic capabilities
Break simulation
ccn NF
Loop-back control for communications link fault isolation
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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MT7621 PROGRAMMING GUIDE
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2.5.2 Registers
EO
n = 1; for uart1 only.
cn IA
UARTn+0000h RX Buffer Register UARTn_RBR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RBR[7:0]
m. NT
Type RO
RBR RX Buffer Register. Read-only register. The received data can be read by accessing this register.
Modified when LCR[7] = 0.
.co IDE
UARTn+0000h TX Holding Register UARTn_THR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name THR[7:0]
Type WO
THR TX Holding Register. Write-only register. The data to be transmitted is written to this register, and
ccn NF
then sent to the PC via serial communication.
Modified when LCR[7] = 0.
UARTn+0004h Interrupt Enable Register UARTn_IER
ase O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CTSI RTSI XOFFI X EDSSI ELSI ETBEI ERBFI
Type R/W
@ KC
Reset 0
IER By storing a ‘1’ to a specific bit position, the interrupt associated with that bit is enabled. Otherwise,
the interrupt is disabled.
IER[3:0] are modified when LCR[7] = 0.
xia E
IER[7:4] are modified when LCR[7] = 0 & EFR[4] = 1.
CTSI Masks an interrupt that is generated when a rising edge is detected on the CTS modem control line.
ny AT
Note: This interrupt is only enabled when hardware flow control is enabled.
0 Unmask an interrupt that is generated when a rising edge is detected on the CTS modem control
line.
1 Mask an interrupt that is generated when a rising edge is detected on the CTS modem control line.
To DI
RTSI Masks an interrupt that is generated when a rising edge is detected on the RTS modem control line.
Note: This interrupt is only enabled when hardware flow control is enabled.
0 Unmask an interrupt that is generated when a rising edge is detected on the RTS modem control
R E
line.
1 Mask an interrupt that is generated when a rising edge is detected on the RTS modem control line.
M
XOFFI Masks an interrupt that is generated when an XOFF character is received.
Note: This interrupt is only enabled when software flow control is enabled.
0 Unmask an interrupt that is generated when an XOFF character is received.
1 Mask an interrupt that is generated when an XOFF character is received.
EDSSI When set ("1"), an interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
0 No interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
FO
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MT7621 PROGRAMMING GUIDE
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NL
1 An interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
US L
ELSI When set ("1"), an interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
EO
0 No interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
cn IA
1 An interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
ETBEI When set ("1"), an interrupt is generated if the TX Holding Register is empty or the contents of the TX
FIFO
m. NT
have been reduced to its Trigger Level.
0 No interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have
been reduced to its Trigger Level.
1 An interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have
.co IDE
been reduced to its Trigger Level
ERBFI When set ("1"), an interrupt is generated if the RX Buffer contains data.
0 No interrupt is generated if the RX Buffer contains data.
1 An interrupt is generated if the RX Buffer contains data.
ccn NF
UARTn+0008h Interrupt Identification Register UARTn_IIR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIFOE ID4 ID3 ID2 ID1 ID0 NINT
Type RO
Reset 0 0 0 0 0 0 0 1
ase O
IIR Identify if there are pending interrupts; ID4 and ID3 are presented only when EFR[4] = 1.
@ KC
The following table gives the IIR[5:0] codes associated with the possible interrupts:
IIR[5:0] Priority Interrupt Source
Level
000001 - No interrupt pending
000110 1 Line Status Interrupt BI, FE, PE or OE set in LSR
xia E
000100 2 RX Data Received RX Data received or RX Trigger Level reached.
001100 2 RX Data Timeout Timeout on character in RX FIFO.
ny AT
000010 3 TX Holding Register TX Holding Register empty or TX FIFO Trigger Level
Empty reached.
000000 4 Modem Status change DDCD, TERI, DDSR or DCTS set in MSR
010000 5 Software Flow Control XOFF Character received
To DI
100000 6 Hardware Flow Control CTS or RTS Rising Edge
Table 1 The IIR[5:0] codes associated with the possible interrupts
R E
Line Status Interrupt: A RX Line Status Interrupt (IIR[5:0`] == 000110b) is generated if ELSI (IER[2]) is set and
any of BI, FE, PE or OE (LSR[4:1]) becomes set. The interrupt is cleared by reading the Line Status Register.
M
RX Data Received Interrupt: A RX Received interrupt (IER[5:0] == 000100b) is generated if EFRBI (IER[0]) is set
and either RX Data is placed in the RX Buffer Register or the RX Trigger Level is reached. The interrupt is
cleared by reading the RX Buffer Register or the RX FIFO (if enabled).
RX Data Timeout Interrupt:
When virtual FIFO mode is disabled, RX Data Timeout Interrupt is generated if all of the following apply:
1. FIFO contains at least one character;
FO
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MT7621 PROGRAMMING GUIDE
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NL
2. The most recent character was received longer than four character periods ago (including all start, parity
US L
and stop bits);
EO
cn IA
3. The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register, or on a CPU read from the
RX FIFO.
m. NT
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1, and is cleared by reading RX FIFO.
When virtual FIFO mode is enabled, RX Data Timeout Interrupt is generated if all of the following apply:
1. FIFO is empty;
2. The most recent character was received longer than four character periods ago (including all start, parity
.co IDE
and stop bits);
3. The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register.
RX Holding Register Empty Interrupt: A TX Holding Register Empty Interrupt (IIR[5:0] = 000010b) is generated if
ccn NF
ETRBI (IER[1]) is set and either the TX Holding Register or, if FIFOs are enabled, the TX FIFO becomes empty.
The interrupt is cleared by writing to the TX Holding Register or TX FIFO if FIFO enabled.
Modem Status Change Interrupt: A Modem Status Change Interrupt (IIR[5:0] = 000000b) is generated if EDSSI
(IER[3]) is set and either DDCD, TERI, DDSR or DCTS (MSR[3:0]) becomes set. The interrupt is cleared by
reading the Modem Status Register.
ase O
Software Flow Control Interrupt: A Software Flow Control Interrupt (IIR[5:0] = 010000b) is generated if
Software Flow Control is enabled and XOFFI (IER[5]) becomes set, indicating that an XOFF character has been
@ KC
received. The interrupt is cleared by reading the Interrupt Identification Register.
Hardware Flow Control Interrupt: A Hardware Flow Control Interrupt (IER[5:0] = 100000b) is generated if
Hardware Flow Control is enabled and either RTSI (IER[6]) or CTSI (IER[7]) becomes set indicating that a
rising edge has been detected on either the RTS/CTS Modem Control line. The interrupt is cleared by reading
the Interrupt Identification Register.
xia E
UARTn+0008h FIFO Control Register UARTn_FCR
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RFTL1 RFTL0 TFTL1 TFTL0 DMA1 CLRT CLRR FIFOE
Type WO
FCR FCR is used to control the trigger levels of the FIFOs, or flush the FIFOs.
To DI
FCR[7:6] is modified when LCR != BFh
FCR[5:4] is modified when LCR != BFh & EFR[4] = 1
FCR[4:0] is modified when LCR != BFh
R E
FCR[7:6] RX FIFO trigger threshold
0 1
M
1 6
2 12
3 RXTRIG
FCR[5:4] TX FIFO trigger threshold
0 1
1 4
FO
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MT7621 PROGRAMMING GUIDE
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NL
2 8
US L
3 14 (FIFOSIZE - 2)
EO
DMA1 This bit determines the DMA mode, which the TXRDY and RXRDY pins support. TXRDY and
cn IA
RXRDY act to support single-byte transfers between the UART and memory (DMA mode 0) or
multiple byte transfers (DMA mode1). Note that this bit has no effect unless the FIFOE bit is set as
well
m. NT
0 The device operates in DMA Mode 0.
1 The device operates in DMA Mode 1.
TXRDY – mode0: Goes active (low) when the TX FIFO or the TX Holding Register is empty.
Becomes inactive when a byte is written to the Transmit channel.
.co IDE
TXRDY – mode1: Goes active (low) when there are no characters in the TX FIFO. Becomes inactive
when the TX FIFO is full.
RXRDY – mode0: Becomes active (low) when at least one character is in the RX FIFO or the RX
Buffer Register is full. Becomes inactive when there are no more characters in the RX FIFO or
RX Buffer register.
ccn NF
RXRDY – mode1: Becomes active (low) when the RX FIFO Trigger Level is reached or an RX FIFO
Character Timeout occurs. Goes inactive when the RX FIFO is empty.
CLRT Clear Transmit FIFO. This bit is self-clearing.
0 Leave TX FIFO intact.
ase O
1 Clear all the bytes in the TX FIFO.
CLRR Clear Receive FIFO. This bit is self-clearing.
@ KC
0 Leave RX FIFO intact.
1 Clear all the bytes in the RX FIFO.
FIFOE FIFO Enabled. This bit must be set to 1 for any of the other bits in the registers to have any effect.
0 Disable both the RX and TX FIFOs.
1 Enable both the RX and TX FIFOs.
xia E
UARTn+000Ch Line Control Register UARTn_LCR
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLAB SB SP EPS PEN STB WLS1 WLS0
Type R/W
Reset 0 0 0 0 0 0 0 0
To DI
LCR Line Control Register. Determines characteristics of serial communication signals.
Modified when LCR[7] = 0.
DLAB Divisor Latch Access Bit.
R E
0 The RX and TX Registers are read/written at Address 0 and the IER register is read/written at
Address 4.
M
1 The Divisor Latch LS is read/written at Address 0 and the Divisor Latch MS is read/written at
Address 4.
SB Set Break
0 No effect
1 SOUT signal is forced into the “0” state.
SP Stick Parity
FO
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MT7621 PROGRAMMING GUIDE
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NL
0 No effect.
US L
1 The Parity bit is forced into a defined state, depending on the states of EPS and PEN:
EO
If EPS=1 & PEN=1, the Parity bit is set and checked = 0.
cn IA
If EPS=0 & PEN=1, the Parity bit is set and checked = 1.
EPS Even Parity Select
0 When EPS=0, an odd number of ones is sent and checked.
m. NT
1 When EPS=1, an even number of ones is sent and checked.
PEN Parity Enable
0 The Parity is neither transmitted nor checked.
1 The Parity is transmitted and checked.
.co IDE
STB Number of STOP bits
0 One STOP bit is always added.
1 Two STOP bits are added after each character is sent; unless the character length is 5 when 1 STOP
bit is added.
WLS1, 0 Word Length Select.
ccn NF
0 5 bits
1 6 bits
2 7 bits
3 8 bits
ase O
UARTn+0010h Modem Control Register UARTn_MCR
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XOFF
DCM_
Name STATU X OUT2 OUT1 RTS DTR
EN
S
Type R/W
Reset 0 0 0 0 0 0 0
xia E
MCR Modem Control Register. Control interface signals of the UART.
MCR[4:0] are modified when LCR[7] = 0,
ny AT
MCR[7:6] are modified when LCR[7] = 0 & EFR[4] = 1.
XOFF Status This is a read-only bit.
0 When an XON character is received.
1 When an XOFF character is received.
To DI
DCM_EN UART DCM function enable bit
0 UART DCM is disabled.
1 UART DCM is enabled.
R E
OUT2 Controls the state of the output NOUT2, even in loop mode.
M
0 NOUT2=1.
1 NOUT2=0.
OUT1 Controls the state of the output NOUT1, even in loop mode.
0 NOUT1=1.
1 NOUT1=0.
RTS Controls the state of the output NRTS, even in loop mode.
0 NRTS=1.
FO
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MT7621 PROGRAMMING GUIDE
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NL
1 NRTS=0.
US L
DTR Control the state of the output NDTR, even in loop mode.
EO
0 NDTR=1.
cn IA
1 NDTR=0.
UARTn+0014h Line Status Register UARTn_LSR
m. NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
Name TEMT THRE BI FE PE OE DR
RR
Type R/W
Reset 0 1 1 0 0 0 0 0
.co IDE
LSR Line Status Register.
Modified when LCR[7] = 0.
FIFOERR RX FIFO Error Indicator.
0 No PE, FE, BI set in the RX FIFO.
1 Set to 1 when there is at least one PE, FE or BI in the RX FIFO.
ccn NF
TEMT TX Holding Register (or TX FIFO) and the TX Shift Register are empty.
0 Empty conditions below are not met.
1 If FIFOs are enabled, the bit is set whenever the TX FIFO and the TX Shift Register are empty. If
ase O
FIFOs are disabled, the bit is set whenever TX Holding Register and TX Shift Register are empty.
THRE Indicates if there is room for TX Holding Register or TX FIFO is reduced to its Trigger Level.
0 Reset whenever the contents of the TX FIFO are more than its Trigger Level (FIFOs are
@ KC
enabled), or whenever TX Holding Register is not empty(FIFOs are disabled).
1 Set whenever the contents of the TX FIFO are reduced to its Trigger Level (FIFOs are enabled), or
whenever TX Holding Register is empty and ready to accept new data (FIFOs are disabled).
BI Break Interrupt.
xia E
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set whenever the SIN is held in the 0 state for more than one
ny AT
transmission time (START bit + DATA bits + PARITY + STOP bits).
If the FIFOs are enabled, this error is associated with a corresponding character in the FIFO and is
flagged when this byte is at the top of the FIFO. When a break occurs, only one zero character is
loaded into the FIFO: the next character transfer is enabled when SIN goes into the marking state
To DI
and receives the next valid start bit.
FE Framing Error.
0 Reset by the CPU reading this register
R E
1 If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP bit. If the
FIFOs are enabled, the state of this bit is revealed when the byte it refers to is the next to be read.
M
PE Parity Error
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set if the received data did not have a valid parity bit. If the
FIFOs are enabled, the state of this bit is revealed when the referred byte is the next to be read.
OE Overrun Error.
0 Reset by the CPU reading this register.
FO
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MT7621 PROGRAMMING GUIDE
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NL
1 If the FIFOs are disabled, this bit is set if the RX Buffer was not read by the CPU before new data
US L
from the RX Shift Register overwrote the previous contents.
EO
If the FIFOs are enabled, an overrun error occurs when the RX FIFO is full and the RX Shift
cn IA
Register becomes full. OE is set as soon as this happens. The character in the Shift Register is
then overwritten, but not transferred to the FIFO.
DR Data Ready.
m. NT
0 Cleared by the CPU reading the RX Buffer or by reading all the FIFO bytes.
1 Set by the RX Buffer becoming full or by a byte being transferred into the FIFO.
.co IDE
UARTn+0018h Modem Status Register UARTn_MSR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DCD RI DSR CTS DDCD TERI DDSR DCTS
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset Input Input Input Input 0 0 0 0
ccn NF
Note: After a reset, D4-D7 are inputs. A modem status interrupt can be cleared by writing ‘0’ or set by writing
‘1’ to this register. D0-D3 can be written to.
Modified when LCR[7] = 0.
MSR Modem Status Register
ase O
DCD Data Carry Detect.
When Loop = "0", this value is the complement of the NDCD input signal.
@ KC
When Loop = "1", this value is equal to the OUT2 bit in the Modem Control Register.
RI Ring Indicator.
When Loop = "0", this value is the complement of the NRI input signal.
When Loop = "1", this value is equal to the OUT1 bit in the Modem Control Register.
DSR Data Set Ready
xia E
When Loop = "0", this value is the complement of the NDSR input signal.
When Loop = "1", this value is equal to the DTR bit in the Modem Control Register.
ny AT
CTS Clear To Send.
When Loop = "0", this value is the complement of the NCTS input signal.
When Loop = "1", this value is equal to the RTS bit in the Modem Control Register.
DDCD Delta Data Carry Detect.
To DI
0 The state of DCD has not changed since the Modem Status Register was last read
1 Set if the state of DCD has changed since the Modem Status Register was last read.
TERI Trailing Edge Ring Indicator
R E
0 The NRI input does not change since this register was last read.
1 Set if the NRI input changes from “0” to “1” since this register was last read.
M
DDSR Delta Data Set Ready
0 Cleared if the state of DSR has not changed since this register was last read.
1 Set if the state of DSR has changed since this register was last read.
DCTS Delta Clear To Send
0 Cleared if the state of CTS has not changed since this register was last read.
1 Set if the state of CTS has changed since this register was last read.
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
UARTn+001Ch Scratch Register UARTn_SCR
US L
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name SCR[7:0]
Type R/W
A general purpose read/write register. After reset, its value is un-defined.
m. NT
Modified when LCR[7] = 0.
UARTn+0000h Divisor Latch (LS) UARTn_DLL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLL[7:0]
.co IDE
Type R/W
Reset 1
UARTn+0004h Divisor Latch (MS) UARTn_DLM
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ccn NF DLL[7:0]
Type R/W
Reset 0
Note: DLL & DLM can only be updated if DLAB is set (“1”).. Note too that division by 1 generates a BAUD signal
ase O
that is constantly high.
Modified when LCR[7] = 1.
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13, 26 MHz and
@ KC
52 MHz. The effective clock enable generated is 16 x the required baud rate.
BAUD 13MHz 26MHz 52MHz
110 7386 14773 29545
300 2708 5417 10833
1200 677 1354 2708
xia E
2400 338 677 1354
ny AT
4800 169 339 677
9600 85 169 339
19200 42 85 169
38400 21 42 85
To DI
57600 14 28 56
115200 6 14 28
Table 2 Divisor needed to generate a given baud rate
R E
UARTn+0008h Enhanced Feature Register UARTn_EFR
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTO AUTO ENABLE
Name D5 SW FLOW CONT[3:0]
CTS RTS -E
Type R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
*NOTE: Only when LCR=BF’h
FO
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MT7621 PROGRAMMING GUIDE
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NL
Auto CTS Enables hardware transmission flow control
US L
0 Disabled.
EO
1 Enabled.
cn IA
Auto RTS Enables hardware reception flow control
0 Disabled.
1 Enabled.
m. NT
Enable-E Enable enhancement features.
0 Disabled.
1 Enabled.
CONT[3:0] Software flow control bits.
.co IDE
00xx No TX Flow Control
10xx Transmit XON1/XOFF1 as flow control bytes
01xx Transmit XON2/XOFF2 as flow control bytes
11xx Transmit XON1 & XON2 and XOFF1 & XOFF2 as flow control words
xx00 No RX Flow Control
ccn NF
xx10 Receive XON1/XOFF1 as flow control bytes
xx01 Receive XON2/XOFF2 as flow control bytes
xx11 Receive XON1 & XON2 and XOFF1 & XOFF2 as flow control words
ase O
UARTn+0010h XON1 UARTn_XON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name XON1[7:0]
Type R/W
Reset 0
UARTn+0014h XON2 UARTn_XON2
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Name XON2[7:0]
Type R/W
Reset 0
UARTn+0018h XOFF1 UARTn_XOFF1
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF1[7:0]
Type R/W
R E
Reset 0
M
UARTn+001Ch XOFF2 UARTn_XOFF2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF2[7:0]
Type R/W
Reset 0
*Note: XON1, XON2, XOFF1, XOFF2 are valid only when LCR=BFh.
FO
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MT7621 PROGRAMMING GUIDE
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NL
US L
EO
UARTn+0024h HIGH SPEED UART UARTn_HIGHSPEED
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPEED [1:0]
Type R/W
Reset 0
m. NT
SPEED UART sample counter base
0 based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLH, DLL}
1 based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLH, DLL}
.co IDE
2 based on 4*baud_pulse, baud_rate = system clock frequency/4/{DLH, DLL}
3 based on sampe_count * baud_pulse, baud_rate = system clock frequency / sampe_count
When HIGHSPEED=3, the value (A * B) means ({DLM, DLL} * SAMPLE_COUNT).
When the Baudrate is more than 115200, it will be more accurate if we set HIGHSPEED=3.
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13M Hz based on
different HIGHSPEED value.
ccn NF
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 7386 14773 29545 7386 * 16
300 2708 7386 14773 2708 * 16
ase O
1200 677 2708 7386 677 * 16
2400 338 677 2708 338 * 16
@ KC
4800 169 338 677 169 * 16
9600 85 169 338 85 * 16
19200 42 85 169 9 * 75
38400 21 42 85 13 * 26
xia E
57600 14 21 42 8 * 28
115200 7 14 21 4 * 28
ny AT
230400 * 7 14 2 * 28
460800 * * 7 1 * 28
921600 * * * 1 * 14
To DI
Table 3 Divisor needed to generate a given baud rate from 13MHz based on different HIGHSPEED value
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 26 MHz based on
R E
different HIGHSPEED value.
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
M
110 14773 29545 59091 7386 * 32
300 5417 14773 29545 2708 * 32
1200 1354 5417 14773 677 * 32
2400 677 1354 5417 338 * 32
4800 339 677 1354 169 * 32
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
9600 169 339 667 85 * 32
US L
EO
19200 85 169 339 18 * 75
38400 42 85 169 26 * 26
cn IA
57600 28 42 85 16 * 28
115200 14 28 42 8 * 28
m. NT
230400 7 14 28 4 * 28
460800 * 7 14 2 * 28
921600 * * 7 1 * 28
.co IDE
Table 4 Divisor needed to generate a given baud rate from 26 MHz based on different HIGHSPEED value
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 52MHz based on
different HIGHSPEED value.
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 29545 59091 118182 14773 * 32
ccn NF
300 10833 29545 59091 5417 * 32
1200 2708 10833 29545 1354 * 32
2400 1354 2708 10833 667 * 32
ase O
4800 677 1354 2708 339 * 32
@ KC
9600 339 677 1354 169 * 32
19200 169 339 677 36 * 75
38400 85 169 339 52 * 26
57600 56 85 169 32 * 28
115200 28 56 85 16 * 28
xia E
230400 14 28 56 8 * 28
ny AT
460800 7 14 28 4 * 28
921600 * 7 14 2 * 28
Table 5 Divisor needed to generate a given baud rate from 52 MHz based on different HIGHSPEED value
To DI
UARTn+0028h SAMPLE_COUNT UARTn_SAMPLE_COUNT
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLECOUNT [7:0]
M
Type R/W
Reset 0
When HIGHSPEED=3, the sample_count is the threshold value for UART sample counter (sample_num).
Count from 0 to sample_count.
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
UARTn+002Ch SAMPLE_POINT UARTn_SAMPLE_POINT
US L
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name SAMPLEPOINT [7:0]
Type R/W
Reset Ffh
When HIGHSPEED=3, UART gets the input data when sample_count=sample_num.
m. NT
e.g. system clock = 13MHz, 921600 = 13000000 / 14
sample_count = 14 and sample point = 7 (sample the central point to decrease the inaccuracy)
The SAMPLE_POINT is usually (SAMPLE_COUNT/2).
.co IDE
UARTn+0034h Rate Fix Address UARTn_RATEFIX_AD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTE_FIX
Type R/W
Reset
ccn NF 0
rate_fix When you set "rate_fix"(34H[0]), you can transmit and receive data only if
the input f16m_en is enable.
ase O
@ KC
UARTn+003Ch Guard time added register UARTn_GUARD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUARD_EN GUARD_CNT[3:0]
Type R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
xia E
GUARD_CNT Guard interval count value. Guard interval = (1/(system clock / div_step / div )) *
GUARD_CNT.
ny AT
GUARD_EN Guard interval add enable signal.
0 No guard interval added.
1 Add guard interval after stop bit.
To DI
UARTn+0040h Escape character register UARTn_ESCAPE_DAT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ESCAPE_DAT[7:0]
Type WO
R E
Reset FFh
M
ESCAPE_DAT Escape character added before software flow control data and escape character, i.e. if tx data is
xon (31h), with esc_en =1, uart transmits data as esc + CEh (~xon).
UARTn+0044h Escape enable register UARTn_ESCAPE_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ESC_EN
Type R/W
FO
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MT7621 PROGRAMMING GUIDE
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NL
Reset 0
US L
EO
ESC_EN Add escape character in transmitter and remove escape character in receiver by UART.
0 Do not deal with the escape character.
cn IA
1 Add escape character in transmitter and remove escape character in receiver.
UARTn+0048h Sleep enable register UARTn_SLEEP_EN
m. NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SELLP_EN
Type R/W
Reset 0
.co IDE
SLEEP_EN For sleep mode issue
0 Do not deal with sleep mode indicate signal
1 To activate hardware flow control or software control according to software initial setting when
chip enters sleep mode. Releasing hardware flow when chip wakes up; but for software control,
uart sends xon when awaken and when FIFO does not reach threshold level.
ccn NF
UARTn+004Ch Virtual FIFO enable register UARTn_VFIFO_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VFIFO_EN
ase O
Type R/W
Reset 0
@ KC
VFIFO_EN Virtual FIFO mechanism enable signal.
0 Disable VFIFO mode.
1 Enable VFIFO mode. When virtual mode is enabled, the flow control is based on the DMA
threshold, and generates a timeout interrupt for DMA.
UARTn+0050h Rx Trigger Address UARTn_RXTRI_AD
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Name RXTRIG[3:0]
Type R/W
Reset 0
RXTRIG When {rtm,rtl}=2’b11, The Rx FIFO threshold will be Rxtrig.
To DI
UARTn+0054h Fractional Divider LSB Address UARTn_FRACDIV_L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name FRACDIV_L
Type R/W
M
Reset 0 0 0 0 0 0 0 0
FRACDIV_L Add sampling count (+1) from state data7 to state data0, in order to contribute fractional
divisor.
FO
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MT7621 PROGRAMMING GUIDE
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UARTn+0058h Fractional Divider MSB Address UARTn_FRACDIV_M
US L
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name FRACDIV_M
Type R/W
Reset 0 0
FRACDIV_M Add sampling count in state stop and state parity, in order to contribute fractional divisor.
m. NT
FRACDIV_L / FRACDIV_L Add one sampling period to each symbol, in order to increase the baud rate
accuracy.
.co IDE
bit_extend register = FRACDIV_L[7:0]
FRACDIV_M[1:0]
ccn NF
Start d0 d1 d2 d3 d4 d5 d6 d7 Parity Stop
n n + L[0] n + L[1] n + L[2] n + L[3] n + L[4] n + L[5] n + L[6] n + L[7] n + M[0] n + M[1]
ase O
m
@ KC
UARTn+005Ch FIFO Control Register UARTn_FCR_RD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RFTL1 RFTL0 TFTL1 TFTL0 DMA1 FIFOE
xia E
Type RO RO
ny AT
Read out UARTn_FCR register.
UARTn+0060h TX Active Enable Address UARTn_TX_ACTIVE_EN
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PU_EN TX_OE_EN
Type R/W R/W
R E
Reset 0 0
TX_OE_EN Enable UART_TX_OE switching function. TX_OE is to control UART_TX output enable.
M
TX_PU_EN Enable UART_TX_PU switching function. TX_PU is to control UART_TX pull up enable.
FO
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MT7621 PROGRAMMING GUIDE
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NL
US L
2.6 Programmable I/O
EO
2.6.1 Features
cn IA
Parameterized numbers of independent inputs, outputs, and inouts
Independent polarity controls for each pin
Independently masked edge detect interrupt on any input transition
m. NT
2.6.2 Block Diagram
gpio_top cfg_ctrl[95:0] gpio_oe[95:0]
.co IDE
x96
gpio_reg cfg_data[95:0] gpio_control gpio_out[95:0]
PBus signals
Configuration
gpio_in[95:0]
ccn NF Registers
gpio_interrupt
gpio_int I/O PAD
ase O
Figure 2-3 Programmable I/O Block Diagram
@ KC
2.6.3 GPIO pin mapping
PAD Name Function 0 Function 1 Function 2 Function 3 strap pmux_group GPIO
PAD_GPIO0 gpio (I/O) 0 gpio_psel[0] 0
PAD_RXD1 rxd1 (I) gpio (I/O) 1
uartl_psel[0]
xia E
PAD_TXD1 txd1 (O) gpio (I/O) 1 2
PAD_I2C_SD i2c_sd (I/O) gpio (I/O) 3
ny AT
i2c_psel[0]
PAD_I2C_SCLK i2c_sclk (I/O) gpio (I/O) 4
PAD_RTS3_N rts3_n (O) gpio (I/O) i2s_sdo (O) spdif_tx (O) 2 5
PAD_CTS3_N cts3_n (I) gpio (I/O) i2s_clk (I/O) gpio (I/O) 6
uart3_psel[1:0]
PAD_TXD3 txd3 (O) gpio (I/O) i2s_ws (I/O) gpio (I/O) 7
To DI
PAD_RXD3 rxd3 (I) gpio (I/O) i2s_sdi (I) gpio (I/O) 8
PAD_RTS2_N rts2_n (O) gpio (I/O) pcm_dtx (I/O) gpio (I/O) 3 9
PAD_CTS2_N cts2_n (I) gpio (I/O) pcm_drx (I) gpio (I/O) 10
uart2_psel[1:0]
R E
PAD_TXD2 txd2 (O) gpio (I/O) pcm_clk (O) spdif_tx (O) 4 11
PAD_RXD2 rxd2 (I) gpio (I/O) pcm_fs (I/O) gpio (I/O) 12
M
PAD_JTDO jtdo (I/O) gpio (I/O) 13
PAD_JTDI jtdi (I) gpio (I/O) 14
PAD_JTMS jtms (I) gpio (I/O) jtag_psel[0] 15
PAD_JTCLK jtclk (I) gpio (I/O) 16
PAD_JTRST_N jtrst_n (I) gpio (I/O) 17
PAD_WDT_RST_N wdt_rst_n (I/O) gpio (I/O) ref_clk0_out (O) wdt_psel[1:0] 18
PAD_PERST_N perst_n (O) gpio (I/O) ref_clk0_out (O) 5 perst_psel[1:0] 19
FO
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MT7621 PROGRAMMING GUIDE
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PAD_MDIO mdio (I/O) gpio (I/O) gpio (I/O) 20
mdio_psel[1:0]
US L
PAD_MDC 21
EO
mdc (O) gpio (I/O) ref_clk0_out (O) 6
PAD_G1_TXD0 g1_txd[0] (I/O) gpio (I/O) 49
cn IA
PAD_G1_TXD1 g1_txd[1] (I/O) gpio (I/O) 50
PAD_G1_TXD2 g1_txd[2] (I/O) gpio (I/O) 51
PAD_G1_TXD3 g1_txd[3] (I/O) gpio (I/O) 52
m. NT
PAD_G1_TXEN g1_txen (I/O) gpio (I/O) 53
PAD_G1_TXC g1_txc (I/O) gpio (I/O) 54
rgmii1_psel[0]
PAD_G1_RXD0 g1_rxd[0] (I/O) gpio (I/O) 55
PAD_G1_RXD1 g1_rxd[1] (I/O) gpio (I/O) 56
.co IDE
PAD_G1_RXD2 g1_rxd[2] (I/O) gpio (I/O) 57
PAD_G1_RXD3 g1_rxd[3] (I/O) gpio (I/O) 58
PAD_G1_RXDV g1_rxdv (I/O) gpio (I/O) 59
PAD_G1_RXC g1_rxc (I/O) gpio (I/O) 60
PAD_G2_TXD0 g2_txd[0] (I/O) gpio (I/O) 22
ccn NF
PAD_G2_TXD1 g2_txd[1] (I/O) gpio (I/O) 23
PAD_G2_TXD2 g2_txd[2] (I/O) gpio (I/O) 24
PAD_G2_TXD3 g2_txd[3] (I/O) gpio (I/O) 25
PAD_G2_TXEN 26
ase O
g2_txen (I/O) gpio (I/O)
PAD_G2_TXC g2_txc (I/O) gpio (I/O) 27
rgmii2_psel[0]
PAD_G2_RXD0 g2_rxd[0] (I/O) gpio (I/O) 28
@ KC
PAD_G2_RXD1 g2_rxd[1] (I/O) gpio (I/O) 29
PAD_G2_RXD2 g2_rxd[2] (I/O) gpio (I/O) 30
PAD_G2_RXD3 g2_rxd[3] (I/O) gpio (I/O) 31
PAD_G2_RXDV g2_rxdv (I/O) gpio (I/O) 32
PAD_G2_RXC 33
xia E
g2_rxc (I/O) gpio (I/O)
PAD_SPI_CS0_N spi_cs0 (I/O) gpio (I/O) nd_cs_n (O) 7 34
ny AT
PAD_SPI_CS1_N spi_cs1 (I/O) gpio (I/O) nd_we_n (O) 8 35
PAD_SPI_SCLK spi_clk (I/O) gpio (I/O) nd_re_n (O) 9 36
PAD_SPI_MISO spi_miso (I/O) gpio (I/O) nd_d[4] (I/O) spi_psel[1:0] 37
PAD_SPI_MOSI spi_mosi (I/O) gpio (I/O) nd_d[5] (I/O) 38
To DI
PAD_SPI_WP_N spi_wp (I/O) gpio (I/O) nd_d[6] (I/O) 39
PAD_SPI_HOLD_N spi_hold (I/O) gpio (I/O) nd_d[7] (I/O) 40
PAD_SD_WP sd_wp (I) gpio (I/O) nd_wp (O) 41
R E
PAD_SD_CLK sd_clk (I/O) gpio (I/O) nd_rb_n (I) 42
PAD_SD_CD sd_cd (I) gpio (I/O) nd_cle (O) 43
M
PAD_SD_CMD sd_cmd (I/O) gpio (I/O) nd_ale (O) 44
sd_psel[1:0]
PAD_SD_D0 sd_data[0] (I/O) gpio (I/O) nd_d[0] (I/O) 45
PAD_SD_D1 sd_data[1] (I/O) gpio (I/O) nd_d[1] (I/O) 46
PAD_SD_D2 sd_data[2] (I/O) gpio (I/O) nd_d[2] (I/O) 47
PAD_SD_D3 sd_data[3] (I/O) gpio (I/O) nd_d[3] (I/O) 48
PAD_ESW_INT esw_int(I) gpio (I/O) esw_psel[0] 61
FO
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MT7621 PROGRAMMING GUIDE
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NL
US L
EO
2.6.4 Registers
Module name: GPIO Base address: (+1E000600h)
cn IA
Address Name Width Register Function
1E000600 GPIO_CTRL_0 32 GPIO0 to GPIO31 direction control register
m. NT
These direction control registers are used to select the data direction of the GPIO
pin.
The value driven onto the GPIO pins, are controlled by the GPIO_POL_x, and
GPIO_DATA_x registers.
1E000604 GPIO_CTRL_1 32 GPIO32 to GPIO63 direction control register
These direction control registers are used to select the data direction of the GPIO
.co IDE
pin.
The value driven onto the GPIO pins, are controlled by the GPIO_POL_x, and
GPIO_DATA_x registers.
1E000608 GPIO_CTRL_2 32 GPIO64 to GPIO95 direction control register
These direction control registers are used to select the data direction of the GPIO
pin.
The value driven onto the GPIO pins, are controlled by the GPIO_POL_x, and
ccn NF GPIO_DATA_x registers.
1E000610 GPIO_POL_0 32 GPIO0 to GPIO31 polarity control register
These polarity control registers are used to control the polarity of the data is
driven on or read from the GPIO pin.
1E000614 GPIO_POL_1 32 GPIO32 to GPIO63 polarity control register
ase O
These polarity control registers are used to control the polarity of the data is
driven on or read from the GPIO pin.
1E000618 GPIO_POL_2 32 GPIO64 to GPIO95 polarity control register
@ KC
These polarity control registers are used to control the polarity of the data is
driven on or read from the GPIO pin.
1E000620 GPIO_DATA_0 32 GPIO0 to GPIO31 data register
These data registers store current GPIO data value for GPIO input mode, or output
driven value for GPIO output mode.
Bit position stand for correspondent GPIO pin.
xia E
1E000624 GPIO_DATA_1 32 GPIO32 to GPIO63 data register
These data registers store current GPIO data value for GPIO input mode, or output
driven value for GPIO output mode.
ny AT
Bit position stand for correspondent GPIO pin.
1E000628 GPIO_DATA_2 32 GPIO64 to GPIO95 data register
These data registers store current GPIO data value for GPIO input mode, or output
driven value for GPIO output mode.
Bit position stand for correspondent GPIO pin.
To DI
1E000630 GPIO_DSET_0 32 GPIO0 to GPIO31 data set register
These data set registers are used to set bits in the GPIO_DATA_x registers.
1E000634 GPIO_DSET_1 32 GPIO32 to GPIO63 data set register
These data set registers are used to set bits in the GPIO_DATA_x registers.
R E
1E000638 GPIO_DSET_2 32 GPIO64 to GPIO95 data set register
These data set registers are used to set bits in the GPIO_DATA_x registers.
M
1E000640 GPIO_DCLR_0 32 GPIO0 to GPIO31 data clear register
These data set registers are used to clear bits in the GPIO_DATA_x registers.
1E000644 GPIO_DCLR_1 32 GPIO32 to GPIO63 data clear register
These data set registers are used to clear bits in the GPIO_DATA_x registers.
1E000648 GPIO_DCLR_2 32 GPIO64 to GPIO95 data clear register
These data set registers are used to clear bits in the GPIO_DATA_x registers.
1E000650 GINT_REDGE_0 32 GPIO0 to GPIO31 rising edge interrupt enable register
FO
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These registers are used to enable the condition of rising edge triggered interrupt.
US L
1E000654 GINT_REDGE_1 32 GPIO32 to GPIO63 rising edge interrupt enable register
EO
These registers are used to enable the condition of rising edge triggered interrupt.
cn IA
1E000658 GINT_REDGE_2 32 GPIO64 to GPIO95 rising edge interrupt enable register
These registers are used to enable the condition of rising edge triggered interrupt.
1E000660 GINT_FEDGE_0 32 GPIO0 to GPIO31 falling edge interrupt enable register
These registers are used to enable the condition of falling edge triggered interrupt.
m. NT
1E000664 GINT_FEDGE_1 32 GPIO32 to GPIO63 falling edge interrupt enable register
These registers are used to enable the condition for falling edge triggered
interrupt.
1E000668 GINT_FEDGE_2 32 GPIO64 to GPIO95 falling edge interrupt enable register
These registers are used to enable the condition of falling edge triggered interrupt.
.co IDE
1E000670 GINT_HLVL_0 32 GPIO0 to GPIO31 high level interrupt enable register
These registers are used to enable the condition of high level triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_0 cannot be set to 1
at the same time.
1E000674 GINT_HLVL_1 32 GPIO32 to GPIO63 high level interrupt enable register
These registers are used to enable the condition of high level triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_1 cannot be set to 1
ccn NF
at the same time.
1E000678 GINT_HLVL_2 32 GPIO64 to GPIO95 high level interrupt enable register
These registers are used to enable the condition of high level triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_2 cannot be set to 1
at the same time.
ase O
1E000680 GINT_LLVL_0 32 GPIO0 to GPIO31 low level interrupt enable register
These registers are used to enable the condition of low level triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_0 cannot be set to 1
@ KC
at the same time.
1E000684 GINT_LLVL_1 32 GPIO32 to GPIO63 low level interrupt enable register
These registers are used to enable the condition of low level triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_1 cannot be set to 1
at the same time.
1E000688 GINT_LLVL_2 32 GPIO64 to GPIO95 low level interrupt enable register
xia E
These registers are used to enable the condition of low level triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_2 cannot be set to 1
at the same time.
ny AT
1E000690 GINT_STAT_0 32 GPIO0 to GPIO31 interrupt status register
These registers are used to record the GPIO current interrupt status.
1E000694 GINT_STAT_1 32 GPIO32 to GPIO63 interrupt status register
These registers are used to record the GPIO current interrupt status.
To DI
1E000698 GINT_STAT_2 32 GPIO64 to GPIO95 interrupt status register
These registers are used to record the GPIO current interrupt status.
1E0006A0 GINT_EDGE_0 32 GPIO0 to GPIO31 edge status register
These registers are used to record the GPIO current interrupt's edge status.
R E
These registers are useful only in edge triggered interrupt.
1E0006A4 GINT_EDGE_1 32 GPIO32 to GPIO63 edge status register
These registers are used to record the GPIO current interrupt's edge status.
M
These registers are useful only in edge triggered interrupt.
1E0006A8 GINT_EDGE_2 32 GPIO64 to GPIO95 edge status register
These registers are used to record the GPIO current interrupt's edge status.
These registers are useful only in edge triggered interrupt.
FO
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NL
US L
EO
1E000600 GPIO_CTRL_0 GPIO0 to GPIO31 direction control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name GPIOCTRL0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name GPIOCTRL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:0 GPIOCTRL0 GPIO Pin Direction
0: GPIO input mode
1: GPIO output mode
1E000604 GPIO_CTRL_1 GPIO32 to GPIO63 direction control register 00000000
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOCTRL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name GPIOCTRL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:0 GPIOCTRL1 GPIO Pin Direction
0: GPIO input mode
1: GPIO output mode
xia E
1E000608 GPIO_CTRL_2 GPIO64 to GPIO95 direction control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ny AT
Name GPIOCTRL2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOCTRL2[15:0]
Type RW
To DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
31:0 GPIOCTRL2 GPIO Pin Direction
0: GPIO input mode
1: GPIO output mode
M
1E000610 GPIO_POL_0 GPIO0 to GPIO31 polarity control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO
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NL
Name GPIOPOL0[15:0]
Type
US L
RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31:0 GPIOPOL0 GPIO Data Polarity
0: Data is non-inverted
m. NT
1: Data is inverted
1E000614 GPIO_POL_1 GPIO32 to GPIO63 polarity control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.co IDE
Name GPIOPOL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOPOL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
31:0 GPIOPOL1 GPIO Data Polarity
0: Data is non-inverted
1: Data is inverted
ase O
@ KC
1E000618 GPIO_POL_2 GPIO64 to GPIO95 polarity control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOPOL2[15:0]
xia E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:0 GPIOPOL2 GPIO Data Polarity
0: Data is non-inverted
1: Data is inverted
To DI
1E000620 GPIO_DATA_0 GPIO0 to GPIO31 data register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name GPIODATA0[31:16]
Type RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODATA0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODATA0 GPIO Data
FO
PGMT7621_V.1.0_130607 Page 70 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E000624 GPIO_DATA_1 GPIO32 to GPIO63 data register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name GPIODATA1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name GPIODATA1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:0 GPIODATA1 GPIO Data
1E000628 GPIO_DATA_2 GPIO64 to GPIO95 data register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODATA2[31:16]
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODATA2[15:0]
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:0 GPIODATA2 GPIO Data
1E000630 GPIO_DSET_0 GPIO0 to GPIO31 data set register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
xia E
Name GPIODSET0[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET0[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:0 GPIODSET0 GPIO Data Set
1: Set the GPIO_DATA_0 register
0: No effect
R E
M
1E000634 GPIO_DSET_1 GPIO32 to GPIO63 data set register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODSET1[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET1[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
PGMT7621_V.1.0_130607 Page 71 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
Bit(s) Name Description
EO
31:0 GPIODSET1 GPIO Data Set
cn IA
1: Set the GPIO_DATA_1 register
0: No effect
m. NT
1E000638 GPIO_DSET_2 GPIO64 to GPIO95 data set register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODSET2[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET2[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0
ccn NF
GPIODSET2 GPIO Data Set
1: Set the GPIO_DATA_2 register
0: No effect
ase O
1E000640 GPIO_DCLR_0 GPIO0 to GPIO31 data clear register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR0[31:16]
@ KC
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODCLR0[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
31:0 GPIODCLR0 GPIO Data Clear
1: Clear the GPIO_DATA_0 register
0: No effect
1E000644 GPIO_DCLR_1 GPIO32 to GPIO63 data clear register 00000000
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR1[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODCLR1[15:0]
M
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODCLR1 GPIO Data Clear
1: Clear the GPIO_DATA_1 register
0: No effect
FO
PGMT7621_V.1.0_130607 Page 72 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E000648 GPIO_DCLR_2 GPIO64 to GPIO95 data clear register 00000000
US L
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR2[31:16]
cn IA
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODCLR2[15:0]
Type
m. NT
WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODCLR2 GPIO Data Clear
.co IDE
1: Clear the GPIO_DATA_2 register
0: No effect
1E000650 GINT_REDGE_0 GPIO0 to GPIO31 rising edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ccn NF
Name GINTREDGE0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTREDGE0[15:0]
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:0 GINTREDGE0 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
0: Disable rising edge triggered
xia E
1E000654 GINT_REDGE_1 GPIO32 to GPIO63 rising edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ny AT
Name GINTREDGE1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTREDGE1[15:0]
Type RW
To DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
31:0 GINTREDGE1 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
0: Disable rising edge triggered
M
1E000658 GINT_REDGE_2 GPIO64 to GPIO95 rising edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTREDGE2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO
PGMT7621_V.1.0_130607 Page 73 of 349
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MT7621 PROGRAMMING GUIDE
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NL
Name GINTREDGE2[15:0]
Type
US L
RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31:0 GINTREDGE2 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
m. NT
0: Disable rising edge triggered
1E000660 GINT_FEDGE_0 GPIO0 to GPIO31 falling edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.co IDE
Name GINTFEDGE0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
31:0 GINTFEDGE0 GPIO Falling Edge Interrupt Enable
1: Enable falling edge triggered
0: Disable falling edge triggered
ase O
@ KC
1E000664 GINT_FEDGE_1 GPIO32 to GPIO63 falling edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTFEDGE1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE1[15:0]
xia E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:0 GINTFEDGE1 GPIO Falling Edge Interrupt Enable
1: Enable falling edge triggered
0: Disable falling edge triggered
To DI
1E000668 GINT_FEDGE_2 GPIO64 to GPIO95 falling edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name GINTFEDGE2[31:16]
Type RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTFEDGE2 GPIO Falling Edge Interrupt Enable
FO
PGMT7621_V.1.0_130607 Page 74 of 349
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MT7621 PROGRAMMING GUIDE
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1: Enable falling edge triggered
0: Disable falling edge triggered
US L
EO
cn IA
1E000670 GINT_HLVL_0 GPIO0 to GPIO31 high level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTHLVL0[31:16]
Type RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:0 GINTHLVL0 GPIO High Level Interrupt Enable
1: Enable high level triggered
ccn NF 0: Disable high level triggered
1E000674 GINT_HLVL_1 GPIO32 to GPIO63 high level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTHLVL1[31:16]
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL1[15:0]
@ KC
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTHLVL1 GPIO High Level Interrupt Enable
1: Enable high level triggered
xia E
0: Disable high level triggered
ny AT
1E000678 GINT_HLVL_2 GPIO64 to GPIO95 high level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTHLVL2[31:16]
Type RW
Reset
To DI
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
M
31:0 GINTHLVL2 GPIO High Level Interrupt Enable
1: Enable high level triggered
0: Disable high level triggered
1E000680 GINT_LLVL_0 GPIO0 to GPIO31 low level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTLLVL0[31:16]
FO
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MT7621 PROGRAMMING GUIDE
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NL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTLLVL0[15:0]
cn IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
31:0 GINTLLVL0 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
.co IDE
1E000684 GINT_LLVL_1 GPIO32 to GPIO63 low level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTLLVL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ccn NF GINTLLVL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
31:0 GINTLLVL1 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
@ KC
1E000688 GINT_LLVL_2 GPIO64 to GPIO95 low level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTLLVL2[31:16]
Type RW
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ny AT
GINTLLVL2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
31:0 GINTLLVL2 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
R E
1E000690 GINT_STAT_0 GPIO0 to GPIO31 interrupt status register 00000000
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTSTAT0[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT0[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
PGMT7621_V.1.0_130607 Page 76 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit(s) Name Description
US L
31:0 GINTSTAT0 GPIO Interrupt Status
EO
1: Interrupt is detected
0: Interrupt is not detected
cn IA
1E000694 GINT_STAT_1 GPIO32 to GPIO63 interrupt status register 00000000
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTSTAT1[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT1[15:0]
.co IDE
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTSTAT1 GPIO Interrupt Status
1: Interrupt is detected
ccn NF
0: Interrupt is not detected
1E000698 GINT_STAT_2 GPIO64 to GPIO95 interrupt status register 00000000
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTSTAT2[31:16]
Type W1C
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT2[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:0 GINTSTAT2 GPIO Interrupt Status
1: Interrupt is detected
ny AT
0: Interrupt is not detected
1E0006A0 GINT_EDGE_0 GPIO0 to GPIO31 edge status register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTEDGE0[31:16]
To DI
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE0[15:0]
Type W1C
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 GINTEDGE0 GPIO Interrupt Edge Status
1: Rising edge
0: Falling edge
1E0006A4 GINT_EDGE_1 GPIO32 to GPIO63 edge status register 00000000
FO
PGMT7621_V.1.0_130607 Page 77 of 349
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MT7621 PROGRAMMING GUIDE
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NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name GINTEDGE1[31:16]
EO
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE1[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:0 GINTEDGE1 GPIO Interrupt Edge Status
1: Rising edge
0: Falling edge
.co IDE
1E0006A8 GINT_EDGE_2 GPIO64 to GPIO95 edge status register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTEDGE2[31:16]
Type W1C
Reset
ccn NF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE2[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
31:0 GINTEDGE2 GPIO Interrupt Edge Status
@ KC
1: Rising edge
0: Falling edge
xia E
ny AT
To DI
R E
M
FO
PGMT7621_V.1.0_130607 Page 78 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
2
2.7 I C Controller
EO
2.7.1 Features
cn IA
2
Programmable I C bus clock rate
2
Supports the Synchronous Inter-Integrated Circuits (I C) serial protocol
Bi-directional data transfer
m. NT
Programmable address width up to 8 bits
Sequential byte read or write capability
Device address and data address can be transmitted for device, page and address selection
Supports Standard mode and Fast mode
.co IDE
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
PGMT7621_V.1.0_130607 Page 79 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
2.7.2 List of Registers
EO
cn IA
Address Name Widt Register Function
h
1E000908 SM0CFG0 32 SERIAL INTERFACE MASTER 0 CONFIG 0 REGISTER
m. NT
1E000910 SM0DOUT 32 SERIAL INTERFACE MASTER 0 DATAOUT REGISTER
1E000914 SM0DIN 32 SERIAL INTERFACE MASTER 0 DATAIN REGISTER
1E000918 SM0ST 32 SERIAL INTERFACE MASTER 0 STATUS REGISTER
1E00091C SM0AUTO 32 SERIAL INTERFACE MASTER 0 AUTO-MODE REGISTER
1E000920 SM0CFG1 32 SERIAL INTERFACE MASTER 0 CONFIG 1 REGISTER
.co IDE
1E000928 SM0CFG2 32 SERIAL INTERFACE MASTER 0 CONFIG 2 REGISTER
1E000940 SM0CTL0 32 Serial interface master 0 control 0 register
1E000944 SM0CTL1 32 Serial interface master 0 control 1 register
1E000950 SM0D0 32 Serial interface master 0 data 0 register
1E000954 SM0D1 32 Serial interface master 0 data 1 register
ccn NF
1E00095C PINTEN 32 Peripheral interrupt enable register
1E000960 PINTST 32 Peripheral interrupt status register
1E000964 PINTCL 32 Peripheral interrupt clear register
ase O
1E000908 SM0CFG0 SERIAL INTERFACE MASTER 0 CONFIG 0 REGISTER 0000000
@ KC
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[24:9]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
xia E
Name RSV0[8:0] SM0_DEVADDR
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:7 RSV0 Reserved
6:0 SM0_DEVADDR Device address for transmission
To DI
1E000910 SM0DOUT SERIAL INTERFACE MASTER 0 DATAOUT 0000000
REGISTER 0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
M
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[7:0] SM0_DATAOUT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
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MT7621 PROGRAMMING GUIDE
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NL
31:8 RSV0 Reserved
US L
7:0 SM0_DATAOUT Data out register for auto mode
EO
cn IA
1E000914 SM0DIN SERIAL INTERFACE MASTER 0 DATAIN REGISTER 0000000
0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[7:0] SM0_DATAIN
.co IDE
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:8 RSV0 Reserved
7:0 SM0_DATAIN Data in register for auto mode
ccn NF
1E000918 SM0ST SERIAL INTERFACE MASTER 0 STATUS REGISTER 0000000
2
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[28:13]
@ KC
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
SM
0_
0_R SM
WD
DA 0_B
RSV0[12:0] AT
TA_ US
A_E
xia E
RD Y
MP
Y
TY
Type RO RW RW RW
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit(s) Name Description
31:3 RSV0 Reserved
To DI
2 SM0_RDATA_RDY I2C read data is ready
1 SM0_WDATA_EMPTY I2C data output register is empty
0 SM0_BUSY State machine is busy
R E
M
1E00091C SM0AUTO SERIAL INTERFACE MASTER 0 AUTO-MODE 0000000
REGISTER 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
RSV0[14:0]
0_S
FO
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MT7621 PROGRAMMING GUIDE
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NL
TA
US L
RT_
EO
RW
Type RO RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:1 RSV0 Reserved
m. NT
0 SM0_START_RW Written with 1 to start a read transaction, and 0 to start a write transaction. This
bit is only valid at auto mode.
.co IDE
1E000920 SM0CFG1 SERIAL INTERFACE MASTER 0 CONFIG 1 REGISTER 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[25:10]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name RSV0[9:0] SM0_BYTECNT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
31:6 RSV0 Reserved
5:0 SM0_BYTECNT The value + 1 indicateds the number of data bytes for sequential reads/writes.
@ KC
(word address is included in data bytes)
1E000928 SM0CFG2 SERIAL INTERFACE MASTER 0 CONFIG 2 REGISTER 0000000
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
0_I
S_A
RSV0[14:0] UT
To DI
OM
OD
E
Type RO RW
Reset
R E
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
M
31:1 RSV0 Reserved
0 SM0_IS_AUTOMODE Set 1 to configure auto mode
1E000940 SM0CTL0 Serial interface master 0 control 0 register 0000034
C
FO
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Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name SM
EO
0_O RS SM0_VSY
SM0_CLK_DIV
DR V0 NC_MODE
cn IA
AIN
Type RW RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM SM SM SM
m. NT
SM
0_ SM 0_S 0_S 0_S
0_C SM
RS WAI 0_D CL_ DA CL_
SM0_DEG_CNT S_S 0_E
V1 T_L EG ST _ST ST
TAT N
EV _EN AT AT RE
US
EL E E CH
Type RW RO RW RW RO RO RO RW RW
.co IDE
Reset 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0
Bit(s) Name Description
31 SM0_ODRAIN Open-drain output configuration
0: When SIF output is logic 1, the output is pulled high by outer devices. SIF output is
open-drained.
ccn NF 1: When SIF output is logic 1, the output is pulled high by SIF master 0.
30 RSV0 Reserved
29:28 SM0_VSYNC_MODE Restrict SIF master 0 trigger within VSYNC pulse
00: Disable
01: Allow triggered in VSYNC pulse
ase O
10: Allow triggered at VSYNC rising edge
27:16 SM0_CLK_DIV SIF master 0 clock divide value
This is used to set the divider to generate expected SCL.
@ KC
15:8 SM0_DEG_CNT SIF master 0 de-glitch value
This is used to set the de-glitch number of SDA and SCL input.
7 RSV1 Reserved
6 SM0_WAIT_LEVEL SIF master 0 wait level configuration
0: output L when SIF master 0 is in WAIT state
1: output H when SIF master 0 is in WAIT state
xia E
5 SM0_DEG_EN SIF master 0 de-glitch enable bit
0: Disable SIF master de-glitch.
ny AT
1: Enable SIF master de-glitch.
4 SM0_CS_STATUS Clock stretching status
0: no clock stretching
1: clock stretching
3 SM0_SCL_STATE SCL value on the bus
To DI
2 SM0_SDA_STATE SDA value on the bus
1 SM0_EN SIF master 0 enable bit
0: Disable SIF master 0.
1: Enable SIF master 0.
R E
0 SM0_SCL_STRECH Clock stretching enable
0: Not allow slaves hold SCL
1: Allow slaves hold SCL
M
1E000944 SM0CTL1 Serial interface master 0 control 1 register 0000008
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV3 SM0_ACK
Type RO RO
FO
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Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name SM
RS
RSV2 SM0_PGLEN SM0_MODE RSV0 0_T
V1
cn IA
RI
Type RO RW RO RW RO RW
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:24 RSV3 Reserved
23:16 SM0_ACK Acknowledge bits
ACK[7:0] is acknowledge of 8 bytes of data
15:11 RSV2 Reserved
.co IDE
10:8 SM0_PGLEN Page length
Page length of sequential read/write. The maximum is 8 bytes. Set 0 as 1 byte.
7 RSV1 Reserved
6:4 SM0_MODE SIF master mode
001: Start
010: Write data
ccn NF 011: Stop
100: Read data with no ack for final byte
101: Read data with ack
3:1 RSV0 Reserved
0 SM0_TRI Trigger serial interface
ase O
0: Read back as serial interface is idle.
1: Set 1 to trigger this serial interface. Read back as serial interface is busy.
@ KC
1E000950 SM0D0 Serial interface master 0 data 0 register FFFFFF
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SM0_DATA3 SM0_DATA2
xia E
Type RW RW
Reset x x x x x x x x x x x x x x x x
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Name SM0_DATA1 SM0_DATA0
Type RW RW
Reset x x x x x x x x x x x x x x x x
Bit(s) Name Description
To DI
31:24 SM0_DATA3 Serial interface data byte 3
23:16 SM0_DATA2 Serial interface data byte 2
15:8 SM0_DATA1 Serial interface data byte 1
R E
7:0 SM0_DATA0 Serial interface data byte 0
M
1E000954 SM0D1 Serial interface master 0 data 1 register FFFFFF
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SM0_DATA7 SM0_DATA6
Type RW RW
Reset x x x x x x x x x x x x x x x x
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO
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MT7621 PROGRAMMING GUIDE
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Name SM0_DATA5 SM0_DATA4
US L
Type RW RW
EO
Reset x x x x x x x x x x x x x x x x
cn IA
Bit(s) Name Description
31:24 SM0_DATA7 Serial interface data byte 7
23:16 SM0_DATA6 Serial interface data byte 6
m. NT
15:8 SM0_DATA5 Serial interface data byte 5
7:0 SM0_DATA4 Serial interface data byte 4
.co IDE
1E00095C PINTEN Peripheral interrupt enable register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name SM
0_I
RSV0[14:0]
NT_
EN
Type RO RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
31:1 RSV0 Reserved
0 SM0_INT_EN Serial interface master 0 interrupt enable
1E000960 PINTST Peripheral interrupt status register 0000000
xia E
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ny AT
Name RSV0[30:15]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
0_I
To DI
RSV0[14:0]
NT_
ST
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
M
31:1 RSV0 Reserved
0 SM0_INT_ST Serial interface master 0 interrupt status
1E000964 PINTCL Peripheral interrupt clear register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO
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Name RSV0[30:15]
US L
Type RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name SM
0_I
RSV0[14:0]
NT_
CL
Type RO RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:1 RSV0 Reserved
.co IDE
0 SM0_INT_CL Serial interface master 0 interrupt clear
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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US L
2.8 NAND Flash Interface
EO
2.8.1 Features
cn IA
ECC (BCH code) acceleration capable of 4/6/8 error correction. (with ECC engine)
Programmable page size and spare size
m. NT
Programmable FDM data size and protected FDM data size.
Word/byte access through APB bus.
DMA for massive data transfer.
.co IDE
Latch sensitive interrupt to indicate ready state for read, program, erase operation.
Programmable wait states, command/address setup and hold time, read enable hold time, and
write enable recovery time.
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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US L
2.8.2 Registers
EO
cn IA
Address Name Width Register Function
1E003000 NFI_CNFG 16 NFI Configuration
The register controls the NFI functions.
For all enable fields, Setting to be logic-1 represents enabled, while 0 represents
m. NT
disabled.
1E003004 NFI_PAGEFMT 16 NFI Page Format Control Register
This register manages the page format of the device. It includes the bus width
selection, the page size, the associated address format, and the spare format.
1E003008 NFI_CON 16 NFI Operation Control Register
.co IDE
This is recommended to reset the state machine, data FIFO and flush the data
FIFO before starting a new command
1E00300C NFI_ACCCON 32 NAND Flash Access Timing Control register
This is the timing access control register for the NAND FLASH interface. In order
to accommodate operations for different system clock frequency ranges from
13MHz to 61.44MHz, wait states and setup/hold time margin can be configured
in this register.
ccn NF
1E003010 NFI_INTR_EN 16 NFI Interrupt Enable Register
This register controls the activity for the interrupt sources. These enable should
be turned on only while SW expects the corresponding interrupt will occur.
1E003014 NFI_INTR 16 NFI Interrupt Status Register
ase O
The register indicates the status of all the interrupt sources. Read this register will
clear all interrupts.
1E003020 NFI_CMD 16 NFI Command register
@ KC
This is the command input register. The user should write this register to issue a
command. Please refer to device datasheet for the command set. Before write
the command, please check out the settings for register NFI_CON.
1E003030 NFI_ADDRNOB 16 NFI Address Length Register
This register represents the number of bytes corresponding to current command.
The each valid number of bytes ranges from 0 to 4. The address format depends
on what device to be used and what commands to be applied. The NFI core is
xia E
made transparent to those different situations except that the user has to define
the number of bytes.
The user should write the target address to the address register NFI_COLADDR
ny AT
and NFI_ROWADDR before programming this register.
1E003034 NFI_COLADDR 32 NFI Column Address Register
This defines the 4 bytes of the column address field to be applied to the device.
Since the device bus width is 1 byte, the NFI core arranges the order of address
data to be least significant byte first. The user should put the first address byte in
the field ADDR0, the second byte in the field ADDR1, and so on.
To DI
1E003038 NFI_ROWADDR 32 NFI Row Address Register
This defines the 4 bytes of the row address field to be applied to the device. Since
the device bus width is 1 byte, the NFI core arranges the order of address data to
be least significant byte first. The user should put the first address byte in the
R E
field ADDR0, the second byte in the field ADDR1, and so on.
1E003040 NFI_STRDATA 16 NFI Data Transfer Start Trigger Register
M
This register controls the activity for the interrupt sources.
1E003044 NFI_CNRNB 16 NFI Check NAND Ready/Busy Register
This register controls the activity for the interrupt sources.
1E003050 NFI_DATAW 32 NFI Write Data Buffer
This is the write port of the data FIFO. It supports word access. The least
significant byte DW0 is to be programmed to the device first, then DW1, and so
on.
1E003054 NFI_DATAR 32 NFI Read Data Buffer
FO
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This is the read port of the data FIFO. It supports word access. The least
significant byte DR0 is the first byte read from the device, then DR1, and so on.
US L
EO
1E003058 NFI_PIO_DIRDY 16 PIO_mode Data Ready Register
This register indicates the data is ready for input
cn IA
1E003060 NFI_STA 32 NFI Status
This register represents the NFI core control status including command mode,
address mode, data program and read mode. The user should poll this register for
the end of those operations.
m. NT
1E003064 NFI_FIFOSTA 16 NFI FIFO Status
The register represents the status of the data FIFO. The FIFO top and bottom
pointer of read & write will be reset when issue "command" to NAND Flash
1E003068 NFI_LOCKSTA 16 NFI Lock Status
This register represents the lock status for each lock range.
.co IDE
If any access_lockxx happens, the nfi core will automatic issue a reset (0xFF)
command to NAND device.
1E003070 NFI_ADDRCNTR 16 NFI Page Address Counter Register
The register represents the current read/write address with respect to initial
address input. It counts in unit of byte. In page read and page program operation,
the address should be the same as that in the state machine in the target device.
1E003080 NFI_STRADDR 32 NFI AHB Start Address Register
ccn NF
The register represents the start address for DMA to access EMI. These memory
from the start address is used to put read data from NAND or write data to NAND
in DMA mode
1E003084 NFI_BYTELEN 16 NFI DMA Byte Length Register
The register represents the current transfer length for DMA to access EMI.
ase O
1E003090 NFI_CSEL 16 NFI device select register
The register is used to select the target device. It decides which CEB pin to be
@ KC
functional. This is useful while using the high-density device.
1E003094 NFI_IOCON 16 NFI IO Control register
Data bus pull down when no use.
1E0030A0 NFI_FDM0L 32 NFI Least FDM Data for Sector 0 Register
This register represents the Least FDM data for the sector 0. Since the device bus
width is 1 byte, the NFI core arranges the order of address data to be least
significant byte first. The user should put the first address byte in the field
xia E
FDM0_0, the second byte in the field FDM0_1, and so on. It will be reset to 0xFF
when issue NFI_Reset.
ny AT
1E0030A4 NFI_FDM0M 32 NFI Most FDM Data for Sector 0 Register
This register represents the Most FDM data for the sector 0. Since the device bus
width is 1 byte, the NFI core arranges the order of address data to be least
significant byte first. The user should put the first address byte in the field
1E003100 NFI_LOCK 16 NFI Lock Enable Register
To DI
This register enable the lock function of NFI .
These setting can only be set once after reset chip.
1E003104 NFI_LOCKCON 32 NFI Lock Control Register
This register control the lock function of NFI .
These setting can only be set once after reset chip.
R E
1E003108 NFI_LOCKANOB 16 NFI Address Format for Lock Register
This register represents the number of bytes corresponding to erase and program
M
command. The each valid number of bytes ranges from 0 to 4. The address
format depends on what device to be used and what commands to be applied.
The NFI core will force these setting during some command operation(8X or 6X).
These setting can only be set once after reset chip.
1E003110 NFI_LOCK00ADD 32 NFI Row Start Address for Lock Set00 Register
This defines the 4 bytes of the row start address field to be locked range for the
device.
These setting can only be set once after reset chip.
1E003114 NFI_LOCK00FMT 32 NFI Row Address Format for Lock Set00 Register
FO
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This defines the 4 bytes format of the row address field to be locked range for the
device.
US L
EO
These setting can only be set once after reset chip.
The MSB unused range must be set to 0 for LOCKxxFMT.
cn IA
1E003190 NFI_FIFODATA0 32 NFI FIFO Content Data 0
This register represents the content data 0 of fifo.
1E003194 NFI_FIFODATA1 32 NFI FIFO Content Data 1
This register represents the content data 1 of fifo.
m. NT
1E003198 NFI_FIFODATA2 32 NFI FIFO Content Data 2
This register represents the content data 2 of fifo.
1E00319C NFI_FIFODATA3 32 NFI FIFO Content Data 3
This register represents the content data 3 of fifo.
.co IDE
1E003200 NFI_MCON 16 NFI LCD Monitor Control Register
1E003204 NFI_TOTALCNT 32 NFI LCD Monitor Total Cycle Count
1E003208 NFI_RQCNT 32 NFI LCD Monitor Request Cycle Count
1E00320C NFI_ACCNT 32 NFI LCD Monitor Access Cycle Count
1E003210 NFI_MASTERSTA 16 NFI Master Status
The four indicator represents MASTER status in the BUS access. There are three
ccn NF channels for AHB master. The MSB(Bit 2) to LSB(bit0) repesent ECC, Auto-
Correction and NFI channel respectively. Each bit represents the channel is active
or inactive. 0 is inactive, 1 is active. After NFI reset, the NFI_MASTERSTA should
be checked to guarantee the master is stopped.
For example:
ase O
MAS_XX[0] The NFI channel is in the XX status.
MAS_XX[1] The Auto-Correction channel is in the XX status.
MAS_XX[2] The ECC channel is in the XX status.
@ KC
1E003000 NFI_CNFG NFI Configuration 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne OP_MODE AUT HW BYT DM REA DM
O_F _EC E_R A_B D_ A_M
xia E
MT_ C_E W URS MO ODE
EN N T_E DE
N
ny AT
Type R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
14:12 OP_MODE The field control the operating process flow of FSM for NFI.
To DI
000b: Idle state.
001b: Read Process. Recommend for basic read operation.
010b: Single Read Process. Recommend for read id and read status.
011b: Program Process. Recommend for basic program operation.
R E
100b: Erase Process. Recommend for basic erase operation.
101b: Reset Process. Recommend for basic reset operation.
110b: Custom Process. Recommend for all advance operation.
M
Others: Reserved
9 AUTO_FMT_EN Automatic HW ECC encode or decode enable.
If enabled, the ECC parity from HW ECC engine and FDM data from Register are written
automatically to the spare area. If disable, the spare data all comes from PIO register, like
DATAR, DATAW, (PIO Mode) or the memory(DMA Mode) as main area data.
8 HW_ECC_EN This field is used to enable encoding or decoding operation of HW ECC engine. If the bit is
enabled, the data is transferring to ECC engine for encoding and decoding. The ECC Engine
should be configured as nfi encoding mode, otherwise the NFI will hang.
6 BYTE_RW Enable byte access. The valid bytes read from NFI_DATAR and NFI_DATAW is only DR0 and
FO
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DW0 if BYTE_RW is enabled.
US L
2 DMA_BURST_EN
EO
1 READ_MODE This field is used to control the activity of read or write transfer.
0: write operation of DMA or PIO.
cn IA
1: read operation of DMA or PIO.
0 DMA_MODE This field is used to control the Operation mode.
0: PIO mode. All data (include read or write) move by MCU through APB access.
1: DMA mode. All data (include read or write) move by HW automation through AHB bus.
m. NT
1E003004 NFI_PAGEFMT NFI Page Format Control Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Mne FDM_ECC_NUM FDM_NUM SPARE_SIZE DBY PAGE_SIZE
TE_E
N
Type R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
15:12 FDM_ECC_NUM The number of each FDM data for HW ECC protection. The valid number of bytes ranges are
from 0 to 8.
11:8 FDM_NUM The FDM data number for each spare area. The valid number of bytes are from 0 to 8.
5:4 SPARE_SIZE
ase O
3 DBYTE_EN 16 bits I/O bus interface enable.
1:0 PAGE_SIZE Page Size. The field specifies the size of one page for the device. Some most widely used
page size are supported.
@ KC
0: The page size is 512 bytes (including 512 bytes data area and (spare_size*1) bytes spare
area).
1: The page size is 2k bytes (including 2048 bytes data area and (spare_size*4) bytes spare
area).
2: The page size is 4k bytes (including 4096 bytes data area and (spare_size*8) bytes spare
area).
3: Reserved.
xia E
ny AT
1E003008 NFI_CON NFI Operation Control Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne SEC_NUM BW BRD NOB SRD NFI_ FIFO
R RST _FL
USH
To DI
Type R/W R/W R/W W/R WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
15:12 SEC_NUM The field represents the sector number to be retrieved from the device or DMA Master. The
valid number ranges from 1 to 8.
M
9 BWR Burst write mode. Setting to be logic-1 enables the data burst write operation.
8 BRD Burst read mode. Setting this field to be logic-1 enables the data read operation. The NFI
core will issue read cycles to retrieve data from the device when the data FIFO is not full or
the device is not in the busy state. The NFI core supports consecutive page reading.
7:5 NOB The field represents the number of bytes to be retrieved from the device in single mode, and
the number of bytes per APB transaction in both single and burst mode. If device is 16-bit IO,
the read bytes number will double
0: Read 8 bytes from the device. (16 byte for 16-bit IO)
1: Read 1 byte from the device. (2 byte for 16-bit IO)
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2: Read 2 bytes from the device. (4 byte for 16-bit IO)
3: Read 3 bytes from the device. (6 byte for 16-bit IO)
US L
EO
4: Read 4 bytes from the device. (8 byte for 16-bit IO)
5: Read 5 byte from the device. (10 byte for 16-bit IO)
6: Read 6 bytes from the device. (12 byte for 16-bit IO)
cn IA
7: Read 7 bytes from the device. (14 byte for 16-bit IO)
4 SRD Setting to be logic-1 initializes the one-shot data read operation. It's mainly used for read ID
and read status command, which requires no more than 4 read cycles to retrieve data from
the device. It used when FIFO is empty or after reset nficore
m. NT
1 NFI_RST Reset the state machine, data FIFO (0x0000) and FDM data (0xffff)
0 FIFO_FLUSH Flush the data FIFO.
.co IDE
1E00300C NFI_ACCCON NAND Flash Access Timing Control register NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne POECS PRECS C2R
Type R/W R/W R/W
Reset F F F F 0F 0F 0F 0F 0F 0F 3F 3F 3F 3F 3F 3F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne W2R
ccn NF WH WST RLT
Type R/W R/W R/W R/W
Reset F F F F F F F F F F F F F F F F
Bit(s) Name Description
ase O
31:28 POECS The field represents the minimum required time for CS post-pulling down after the access to
device.
Minimum required time = PRECS[1:0] + PRECS[2]*8 + PRECS[3]*64 (T)
@ KC
27:22 PRECS The field represents the minimum required time for CS pre-pulling down before any access to
device.
Minimum required time = PRECS[1:0] + PRECS[3:2]*8 + PRECS[5:4]*128 (T)
21:16 C2R The field represents the minimum required time from NCEB low to NREB low. It's in unit of
2T.
Minimum required time = C2R[5:0]*2 + 1 (T)
xia E
15:12 W2R The field represents the minimum required time from NWEB high to NREB low. It's in unit of
2T. So the actual time ranges from 0T to 30T in step of 2T.
Minimum required time = W2R[3:0]*2 + 1 (T)
ny AT
11:8 WH Write-enable hold-time.
The field specifies the hold time of NALE, NCLE, NCEB signals relative to the rising edge of
NWEB. This field is associated with WST to expand the write cycle time, and is associated with
RLT to expand the read cycle time.
7:4 WST Write Wait State
To DI
The field specifies the wait states to be inserted to meet the requirement of the pulse width of
the NWEB signal.
00b: No wait state.
01b: 1T wait state.
10b: 2T wait state.
R E
11b: 3T wait state.
3:0 RLT Read Latency Time
M
The field specifies how many wait states to be inserted to meet the requirement of the read
access time for the device.
00b: No wait state.
01b: 1T wait state.
10b: 2T wait state.
11b: 3T wait state.
FO
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MT7621 PROGRAMMING GUIDE
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NL
1E003010 NFI_INTR_EN NFI Interrupt Enable Register 0000
US L
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne AHB ACC BUS ERA RESE WR_ RD_
cn IA
_DO ESS_ Y_R SE_ T_D DON DON
NE_ LOC ETU DON ONE E_E E_E
EN K_E RN_ E_E _EN N N
N EN N
Type R/W R/W R/W R/W R/W R/W R/W
m. NT
Reset 0 0 0 0 0 0 0
Bit(s) Name Description
6 AHB_DONE_EN The done interrupt enable for DMA mode.
.co IDE
5 ACCESS_LOCK_EN
4 BUSY_RETURN_EN The busy return interrupt enable.
3 ERASE_DONE_EN The erase completion interrupt enable.
2 RESET_DONE_EN The reset completion interrupt enable.
1 WR_DONE_EN The single page write completion interrupt enable.
0 RD_DONE_EN The single page read completion interrupt enable.
ccn NF
1E003014 NFI_INTR NFI Interrupt Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Mne AHB ACC BUS ERA RESE WR_ RD_
_DO ESS_ Y_R SE_ T_D DON DON
NE LOC ETU DON ONE E E
@ KC
K RN E
Type RC RC RC RC RC RC RC
Reset 0 0 0 0 0 0 0
Bit(s) Name Description
6 AHB_DONE Indicates that the AHB operation is completed.
xia E
5 ACCESS_LOCK
4 BUSY_RETURN Indicates that the device state returns from busy by inspecting the R/B# pin.
ny AT
3 ERASE_DONE Indicates that the erase operation is completed.
2 RESET_DONE Indicates that the reset operation is completed.
1 WR_DONE Indicates that the write operation is completed.
0 RD_DONE Indicates that the single page read operation is completed.
To DI
1E003020 NFI_CMD NFI Command register 0000
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne CMD
Type R/W
M
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7:0 CMD Command word.
1E003030 NFI_ADDRNOB NFI Address Length Register 0000
FO
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MT7621 PROGRAMMING GUIDE
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Mne ROW_ADDR_NOB COL_ADDR_NOB
EO
Type R/W R/W
Reset 0 0 0 0 0 0
cn IA
Bit(s) Name Description
6:4 ROW_ADDR_NOB Number of bytes for the row address
2:0 COL_ADDR_NOB Number of bytes for the column address
m. NT
1E003034 NFI_COLADDR NFI Column Address Register 00000000
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne COL_ADDR3 COL_ADDR2
Type R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne COL_ADDR1 COL_ADDR0
Type R/W R/W
Reset 0
ccn NF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 COL_ADDR3 The 3-th column address byte.
23:16 COL_ADDR2 The 2-th column address byte.
ase O
15:8 COL_ADDR1 The 1-th column address byte.
7:0 COL_ADDR0 The 0-th column address byte.
@ KC
1E003038 NFI_ROWADDR NFI Row Address Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ROW_ADDR3 ROW_ADDR2
Type
xia E
R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Mne ROW_ADDR1 ROW_ADDR0
Type R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
31:24 ROW_ADDR3 The 3-th row address byte.
23:16 ROW_ADDR2 The 2-th row address byte.
15:8 ROW_ADDR1 The 1-th row address byte.
7:0 ROW_ADDR0 The 0-th row address byte.
R E
M
1E003040 NFI_STRDATA NFI Data Transfer Start Trigger Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne STR
_DA
TA
Type WO
Reset 0
FO
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MT7621 PROGRAMMING GUIDE
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Bit(s) Name Description
US L
0 STR_DATA This signal triggers the data transfer for read or write. It only takes effect as custom
EO
operation mode
cn IA
1E003044 NFI_CNRNB NFI Check NAND Ready/Busy Register 0000
m. NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne CB2R_TIME STR
_CN
RNB
Type R/W WO
Reset 0 0 0 0 0
.co IDE
Bit(s) Name Description
7:4 CB2R_TIME This time-out registers for polling the NAND busy/ready signal. The unit is 16T clock cycles.
The clock rate is 61.44MHz in normal mode. It will be slow down after enable HW DCM
mode.
0 STR_CNRNB This signal triggers NFI to poll the status the NAND busy/ready signal after CB2R_TIME*16
cycles. This function is used to avoid the fail function of "BUSY2READY" status or
ccn NF
"BUSY_RETURN" interrupt when NAND is operating at very low frequency( <7MHz ). If NAND
is operating in lower frequency, the sampling for the event, NAND busy/ready signal from
low to high, may be failed and NFI will be hanged in busy state. This signal is a time-out
register to check the NAND status. The results will be report to "BUSY2READY" status and
"BUSY_RETURN" interrupt.
ase O
@ KC
1E003050 NFI_DATAW NFI Write Data Buffer 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DW3 DW2
Type WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DW1 DW0
xia E
Type WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:24 DW3 Write data byte 3.
23:16 DW2 Write data byte 2.
15:8 DW1 Write data byte 1.
To DI
7:0 DW0 Write data byte 0.
R E
1E003054 NFI_DATAR NFI Read Data Buffer 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Mne DR3 DR2
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DR1 DR0
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
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Bit(s) Name Description
US L
31:24 DR3 Read data byte 3.
EO
23:16 DR2 Read data byte 2.
cn IA
15:8 DR1 Read data byte 1.
7:0 DR0 Read data byte 0.
m. NT
1E003058 NFI_PIO_DIRDY PIO_mode Data Ready Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PIO_
DI_R
.co IDE
DY
Type RO
Reset 0
Bit(s) Name Description
0 PIO_DI_RDY indicates the PIO mode is ready for read data in read mode and ready for write data in write
mode.
ccn NF
0: NFI_DATAR and NFI_DATAW should not be read or write (not ready).
1: NFI is ready for reading data in ready mode and writing data in write mode.
ase O
1E003060 NFI_STA NFI Status 00001000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Mne NAND_FSM NFI_FSM
Type RO RO
Reset 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne REA BUS BUS ACC DAT DAT ADD CM
D_E Y2R Y ESS_ AW AR R D
MPT EAD LOC
Y Y K
xia E
Type RO RO RO RO RO RO RO RO
Reset 1 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
28:24 NAND_FSM The field represents the state of NAND interface FSM.
000000b: IDLE. idle.
111000b: PRE_CS. Pre CS state.
To DI
001001b: CMD_WRST. command write set up
001010b: CMD_WR. Command write enable.
001011b: CMD_WRHD. Command write hold.
001000b: CMD_WRRDY
010001b: ADDR_WRST. Address write set up
R E
010010b: ADDR_WR. Address write enable
010011b: ADDR_WRHD. Address write hold
010000b: ADDR_WRRDY.
M
011000b: CA2DEXT. Command address write extension.
100001b: DATA_RDST. Data read set up.
100010b: DATA_RD. Data read enable.
100011b: DATA_RDHD. Data read hold.
110001b: DATA_WRST. Data write set up.
110010b: DATA_WR. Data write enable.
110011b: DATA_WRHD. Data write hold.
Others: Reserved
19:16 NFI_FSM The field represents the state of NFI internal FSM.
0000b: idle.
FO
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MT7621 PROGRAMMING GUIDE
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0001b: reset. Reset command to ready
0010b: read busy.
US L
EO
0011b: read data.
0100b: program busy
0101b: program data. Input data command to program command
cn IA
1000b: erase busy. Erase command to ready
1001b: erase data. Erase command 1 to erase command 2
1111b: custom mode
1110b: custom mode for data access
Others: Reserved
m. NT
12 READ_EMPTY Empty page indication during read operation, include all data, FDM and parity for all sectors
9 BUSY2READY It's read-only. This signal indicates NAND from busy to ready state and it will be reset after
nfi_reset or write command/address.
8 BUSY Synchronized busy signal from the NAND flash. It's read-only. This signal is sampled from NFI
.co IDE
4 ACCESS_LOCK The access range is locked for erase or program .
3 DATAW The NFI core is in data write mode.
2 DATAR The NFI core is in data read mode.
1 ADDR The NFI core is in address mode.
0 CMD The NFI core is in command mode.
ccn NF
1E003064 NFI_FIFOSTA NFI FIFO Status 4040
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne
ase O
WR WR WR_REMAIN RD_ RD_ RD_REMAIN
_FU _EM FULL EMP
LL PTY TY
Type RO RO RO RO RO RO
@ KC
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0
Bit(s) Name Description
15 WR_FULL Data FIFO full in burst write mode.
14 WR_EMPTY Data FIFO empty in burst write mode.
12:8 WR_REMAIN Data FIFO remaining byte number in burst write mode.
xia E
7 RD_FULL Data FIFO full in burst read mode.
6 RD_EMPTY Data FIFO empty in burst read mode.
ny AT
4:0 RD_REMAIN Data FIFO remaining byte number in burst read mode.
1E003068 NFI_LOCKSTA NFI Lock Status 0000
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC
ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_
LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
R E
K15 K14 K13 K12 K11 K10 K09 K08 K07 K06 K05 K04 K03 K02 K01 K00
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
15 ACCESS_LOCK15 The access command violates the locking range 15
14 ACCESS_LOCK14 The access command violates the locking range 14
13 ACCESS_LOCK13 The access command violates the locking range 13
12 ACCESS_LOCK12 The access command violates the locking range 12
11 ACCESS_LOCK11 The access command violates the locking range 11
FO
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10 ACCESS_LOCK10 The access command violates the locking range 10
US L
9 ACCESS_LOCK09 The access command violates the locking range 9
EO
8 ACCESS_LOCK08 The access command violates the locking range 8
cn IA
7 ACCESS_LOCK07 The access command violates the locking range 7
6 ACCESS_LOCK06 The access command violates the locking range 6
5 ACCESS_LOCK05 The access command violates the locking range 5
4 ACCESS_LOCK04 The access command violates the locking range 4
m. NT
3 ACCESS_LOCK03 The access command violates the locking range 3
2 ACCESS_LOCK02 The access command violates the locking range 2
1 ACCESS_LOCK01 The access command violates the locking range 1
0 ACCESS_LOCK00 The access command violates the locking range 0
.co IDE
1E003070 NFI_ADDRCNTR NFI Page Address Counter Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne SEC_CNTR SEC_ADDR
Type RO
ccn NF RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:12 SEC_CNTR The sector count.
ase O
9:0 SEC_ADDR The address count of 512 main data and spare data for each sector.
@ KC
1E003080 NFI_STRADDR NFI AHB Start Address Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne STR_ADDR[31:16]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne STR_ADDR[15:0]
Type R/W
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 STR_ADDR The start address of EMI for both read or write in DMA mode.
To DI
If start address of any sector data is not 4-byte aligned, the transfer will be automatically split
into byte and word transaction by NFI DMA. Non 4-byte aligned data will be transferred in
single-byte transaction. Non 16-byte aligned data will be transferred in single-word
transaction. 16-byte aligned data will be transferred by 4 word incrementing bust if the
NFI_CNFG->DMA_BURST_EN is enabled.
R E
M
1E003084 NFI_BYTELEN NFI DMA Byte Length Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne BUS_SEC_CNTR BUS_SEC_ADDR
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
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15:12 BUS_SEC_CNTR The sector count.
US L
9:0 BUS_SEC_ADDR The address count of 512 main data and spare data for each sector.
EO
cn IA
1E003090 NFI_CSEL NFI device select register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Mne CSEL
Type R/W
Reset 0
Bit(s) Name Description
.co IDE
0 CSEL Chip select. The value defaults to 0.
0: Device 1 is selected.
1: Device 2 is selected.
1E003094 NFI_IOCON NFI IO Control register 0006
ccn NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne BRSTN L2N L2N NLD
W R _PD
Type R/W R/W R/W R/W
Reset 0 0 0 0 1 1 0
ase O
Bit(s) Name Description
@ KC
7:4 BRSTN Maximum Burst Number for NAND read and writes. The unit is number of byte (8bits I/O) or
double byte (16bits I/O)
2 L2NW Enable 1T latency for the arbitration from LCD to NAND write operation, this is used to
prevent bus contention between chip, NAND flash and LCD device.
1 L2NR Enable 1T latency for the arbitration from LCD to NAND read operation, this is used to
prevent bus contention between chip, NAND flash and LCD device.
0 NLD_PD data bus pull down when no use.
xia E
0: disable.
1: enable.
ny AT
1E0030A0 NFI_FDM0L NFI Least FDM Data for Sector 0 Register NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Mne FDM0_3 FDM0_2
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FDM0_1 FDM0_0
R E
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
M
Bit(s) Name Description
31:24 FDM0_3 The 3-th FDM byte data for sector 0.
23:16 FDM0_2 The 2-th FDM byte data for sector 0.
15:8 FDM0_1 The 1-th FDM byte data for sector 0.
7:0 FDM0_0 The 0-th FDM byte data for sector 0.
FO
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MT7621 PROGRAMMING GUIDE
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US L
EO
1E0030A4 NFI_FDM0M NFI Most FDM Data for Sector 0 Register NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Mne FDM0_7 FDM0_6
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Mne FDM0_5 FDM0_4
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Bit(s) Name Description
.co IDE
31:24 FDM0_7 The 3-th FDM byte data for sector 0.
23:16 FDM0_6 The 2-th FDM byte data for sector 0.
15:8 FDM0_5 The 1-th FDM byte data for sector 0.
7:0 FDM0_4 The 0-th FDM byte data for sector 0.
ccn NF
1E003100 NFI_LOCK NFI Lock Enable Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne LOC
K_O
ase O
N
Type R/W
1
@ KC
Reset 0
Bit(s) Name Description
0 LOCK_ON Enable the lock checking process for any lock set.
0: Disable lock checking process.
1: Enable lock checking process.
xia E
ny AT
1E003104 NFI_LOCKCON NFI Lock Control Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
K15 K15 K14 K14 K13 K13 K12 K12 K11 K11 K10 K10 K09 K09 K08 K08
_CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN
To DI
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
R E
K07 K07 K06 K06 K05 K05 K04 K04 K03 K03 K02 K02 K01 K01 K00 K00
_CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 LOCK15_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 15 for CS0.
1: Lock range check of set 15 for CS1.
30 LOCK15_EN Enable the lock checking process of lock set 15. Before it takes effect, the LOCK_ON must be
FO
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MT7621 PROGRAMMING GUIDE
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NL
turned on.
US L
0: Disable Lock Range check for set 15.
EO
1: Enable Lock Range check for set 15.
29 LOCK14_CS Indicate the lock checking process of lock set.n for CS0 or CS1
cn IA
0: Lock range check of set 14 for CS0.
1: Lock range check of set 14 for CS1.
28 LOCK14_EN Enable the lock checking process of lock set 14. Before it takes effect, the LOCK_ON must be
turned on.
m. NT
0: Disable Lock Range check for set 14.
1: Enable Lock Range check for set 14.
27 LOCK13_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 13 for CS0.
1: Lock range check of set 13 for CS1.
.co IDE
26 LOCK13_EN Enable the lock checking process of lock set 13. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 13.
1: Enable Lock Range check for set 13.
25 LOCK12_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 12 for CS0.
1: Lock range check of set 12 for CS1.
ccn NF
24 LOCK12_EN Enable the lock checking process of lock set 12. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 12.
1: Enable Lock Range check for set 12.
23 LOCK11_CS Indicate the lock checking process of lock set.n for CS0 or CS1
ase O
0: Lock range check of set 11 for CS0.
1: Lock range check of set 11 for CS1.
22 LOCK11_EN Enable the lock checking process of lock set 11. Before it takes effect, the LOCK_ON must be
@ KC
turned on.
0: Disable Lock Range check for set 11.
1: Enable Lock Range check for set 11.
21 LOCK10_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 10 for CS0.
1: Lock range check of set 10 for CS1.
xia E
20 LOCK10_EN Enable the lock checking process of lock set 10. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 10.
ny AT
1: Enable Lock Range check for set 10.
19 LOCK09_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 9 for CS0.
1: Lock range check of set 9 for CS1.
18 LOCK09_EN Enable the lock checking process of lock set 9. Before it takes effect, the LOCK_ON must be
To DI
turned on.
0: Disable Lock Range check for set 9.
1: Enable Lock Range check for set 9.
17 LOCK08_CS Indicate the lock checking process of lock set.n for CS0 or CS1
R E
0: Lock range check of set 8 for CS0.
1: Lock range check of set 8 for CS1.
16 LOCK08_EN Enable the lock checking process of lock set 8. Before it takes effect, the LOCK_ON must be
M
turned on.
0: Disable Lock Range check for set 8.
1: Enable Lock Range check for set 8.
15 LOCK07_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 7 for CS0.
1: Lock range check of set 7 for CS1.
14 LOCK07_EN Enable the lock checking process of lock set 7. Before it takes effect, the LOCK_ON must be
turned on.
FO
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MT7621 PROGRAMMING GUIDE
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0: Disable Lock Range check for set 7.
1: Enable Lock Range check for set 7.
US L
EO
13 LOCK06_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 6 for CS0.
cn IA
1: Lock range check of set 6 for CS1.
12 LOCK06_EN Enable the lock checking process of lock set 6. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 6.
m. NT
1: Enable Lock Range check for set 6.
11 LOCK05_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 5 for CS0.
1: Lock range check of set 5 for CS1.
10 LOCK05_EN Enable the lock checking process of lock set 5. Before it takes effect, the LOCK_ON must be
.co IDE
turned on.
0: Disable Lock Range check for set 5.
1: Enable Lock Range check for set 5.
9 LOCK04_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 4 for CS0.
1: Lock range check of set 4 for CS1.
8 LOCK04_EN Enable the lock checking process of lock set 4. Before it takes effect, the LOCK_ON must be
ccn NF
turned on.
0: Disable Lock Range check for set 4.
1: Enable Lock Range check for set 4.
7 LOCK03_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 3 for CS0.
ase O
1: Lock range check of set 3 for CS1.
6 LOCK03_EN Enable the lock checking process of lock set 3. Before it takes effect, the LOCK_ON must be
turned on.
@ KC
0: Disable Lock Range check for set 3.
1: Enable Lock Range check for set 3.
5 LOCK02_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 2 for CS0.
1: Lock range check of set 2 for CS1.
4 LOCK02_EN Enable the lock checking process of lock set 2. Before it takes effect, the LOCK_ON must be
turned on.
xia E
0: Disable Lock Range check for set 2.
1: Enable Lock Range check for set 2.
ny AT
3 LOCK01_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 1 for CS0.
1: Lock range check of set 1 for CS1.
2 LOCK01_EN Enable the lock checking process of lock set 1. Before it takes effect, the LOCK_ON must be
turned on.
To DI
0: Disable Lock Range check for set 1.
1: Enable Lock Range check for set 1.
1 LOCK00_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 0 for CS0.
1: Lock range check of set 0 for CS1.
R E
0 LOCK00_EN Enable the lock checking process of lock set 0. Before it takes effect, the LOCK_ON must be
turned on.
M
0: Disable Lock Range check for set 0.
1: Enable Lock Range check for set 0.
1E003108 NFI_LOCKANOB NFI Address Format for Lock Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PROG_RADD_NOB PROG_CADD_NOB ERASE_RADD_NOB ERASE_CADD_NOB
FO
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MT7621 PROGRAMMING GUIDE
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Type R/W1 R/W1 R/W1 R/W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit(s) Name Description
cn IA
14:12 PROG_RADD_NOB Number of bytes for the row address for program operation (command is 8'h8X)
10:8 PROG_CADD_NOB Number of bytes for the column address for program operation (command is 8'h8X)
6:4 ERASE_RADD_NOB Number of bytes for the row address for erase operation (command is 8'h6X)
m. NT
2:0 ERASE_CADD_NOB Number of bytes for the column address for erase operation (command is 8'h6X)
1E003110 NFI_LOCK00ADD NFI Row Start Address for Lock Set00 Register 00000000
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne LOCK00_ROW3 LOCK00_ROW2
Type R/W1 R/W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne LOCK00_ROW1 LOCK00_ROW0
Type R/W1 R/W1
ccn NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 LOCK00_ROW3 The 3-th row start address byte to be locked for lock set 0.
ase O
23:16 LOCK00_ROW2 The 2-th row start address byte to be locked for lock set 0.
15:8 LOCK00_ROW1 The 1-th row start address byte to be locked for lock set 0.
7:0 LOCK00_ROW0 The 0-th row start address byte to be locked for lock set 0.
@ KC
1E003114 NFI_LOCK00FMT NFI Row Address Format for Lock Set00 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne LOCK00_FMT3 LOCK00_FMT2
xia E
Type R/W1 R/W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Mne LOCK00_FMT1 LOCK00_FMT0
Type R/W1 R/W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
31:24 LOCK00_FMT3 The 3-th row address format byte to be locked for lock set 0.
23:16 LOCK00_FMT2 The 2-th row address format byte to be locked for lock set 0.
15:8 LOCK00_FMT1 The 1-th row address format byte to be locked for lock set 0.
R E
7:0 LOCK00_FMT0 The 0-th row address format byte to be locked for lock set 0.
M
1E003190 NFI_FIFODATA0 NFI FIFO Content Data 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FIFO_DATA0[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA0[15:0]
FO
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MT7621 PROGRAMMING GUIDE
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Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit(s) Name Description
cn IA
31:0 FIFO_DATA0
m. NT
1E003194 NFI_FIFODATA1 NFI FIFO Content Data 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FIFO_DATA1[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA1[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0
ccn NF
FIFO_DATA1
1E003198 NFI_FIFODATA2 NFI FIFO Content Data 2 00000000
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FIFO_DATA2[31:16]
Type RO
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA2[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
31:0 FIFO_DATA2
ny AT
1E00319C NFI_FIFODATA3 NFI FIFO Content Data 3 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
To DI
FIFO_DATA3[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA3[15:0]
R E
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 FIFO_DATA3
1E003200 NFI_MCON NFI LCD Monitor Control Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO
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MT7621 PROGRAMMING GUIDE
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Mne BMC BMS
US L
LR TR
EO
Type WO R/W
Reset 0 0
cn IA
Bit(s) Name Description
1 BMCLR Clear NFI-LCD bandwidth monitor register counter
0 BMSTR Enable NFI-LCD bandwidth monitor
m. NT
0: disable.
1: enable.
.co IDE
1E003204 NFI_TOTALCNT NFI LCD Monitor Total Cycle Count 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne NFI_TOTALCNT[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_TOTALCNT[15:0]
ccn NF
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
31:0 NFI_TOTALCNT The total clock cycle count during enabling NFI-LCD bandwidth monitor
@ KC
1E003208 NFI_RQCNT NFI LCD Monitor Request Cycle Count 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne NFI_RQCNT[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
xia E
Mne NFI_RQCNT[15:0]
Type RO
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 NFI_RQCNT The request clock cycle count during enabling NFI-LCD bandwidth monitor
To DI
1E00320C NFI_ACCNT NFI LCD Monitor Access Cycle Count 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Mne NFI_ACCNT[31:16]
Type RO
Reset
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_ACCNT[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 NFI_ACCNT The access clock cycle count during enabling NFI-LCD bandwidth monitor
FO
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US L
EO
1E003210 NFI_MASTERSTA NFI Master Status 0000
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne MAS_ADDR MAS_RD MAS_WR MAS_RDDLY
Type RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
11:9 MAS_ADDR MAS_is in the Address phase of AHB protocol. In this phase, Bus gots the address data from
Master.
000b: There is no MAS in the Address phase of AHB protocol.
.co IDE
001b: NFI is in the Address pahse of AHB protocol.
010b: Auto-Correction is in the Address pahse of AHB protocol.
100b: ECC is in the Address pahse of AHB protocol.
8:6 MAS_RD MAS_is in the Read DATA phase of AHB protocol. In this phase, Bus returns the read data.
5:3 MAS_WR MAS_is in the Write DATA phase of AHB protocol. In this phase, Bus receives the write data.
2:0 MAS_RDDLY MAS is in the Read DATA delay phase of AHB protocol. In this phase, NFI and ECC got the
read back data
ccn NF
2.8.3 Programming Guide
ase O
This section lists the program sequences for the NAND flash operations.
NAND Device Reset
Programming Sequence Memo
@ KC
*NFI_INTR_EN = 0x4; // enable reset complete interrupt
*NFI_CMD = 0xff; Reset command
*NFI_CNRNB = 0xf1
Wait for reset complete interrupt
xia E
NFI reset ( General )
Programming Sequence Memo
ny AT
The NFI reset to reset all register and force NFI master be early
*NFI_CON = 0x3
terminated
while ( *NFI_MASTERSTA != 0 ) ; Wait for master finish the last transaction
The second NFI reset is to ensure any status register affected
*NFI_CON = 0x3
by NFI master is reset to normal status
To DI
Read ID
Programming Sequence Memo
R E
NFI Configuration
*NFI_CON = 0x3; //Reset NFI before any command. (NFI_state back to IDLE)
M
*NFI_CNFG = 0x2042; //Single word PIO read. (set 0x2000 for single byte PIO read).
Write Command and Address to NAND Device
(NFI_state from IDLE state jump to READDATA state)
*NFI_CMD = 0x90;
(Issue command when SW write this APB address)
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
*NFI_ADDRNOB = addres_byte_num; //column and row number of bytes.
FO
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MT7621 PROGRAMMING GUIDE
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(Issue address when the SW write this APB address).
US L
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
EO
Trigger the start to read register and NFI start to read status or ID from NAND Device
cn IA
//set number of read command of single read.
*NFI_CON = 0x0090 If this is x8 NF device, this means read 4*(byte) data.
If this is x16 NF device, this means read 4 * (2byte) data.
Read Data from NFI by using PIO Mode
m. NT
for (int i = 0 ; i < number of byte ; i++ ) { //PIO mode to read out read id.
while (*NFI_PIO_RDY == 0); //if the pio_rdy is not 1, keep polling.
pio_rdy = *NFI_PIO_RDY; //if the pio_rdy is equal to 1, data is available for read out.
read_id[i] = *NFI_DATAR; //The read out data from NFI_DATAR can be byte or word
.co IDE
} //It depends on the setting of BYTE_RW in NFI_CNFG
Read Status
Programming Sequence Memo
Configuration
ccn NF
*NFI_CON = 0x3; //Reset NFI before any command. (NFI_state back to IDLE)
*NFI_CNFG = 0x2042; //Single word PIO read. (set 0x2000 for single byte PIO read).
Write Command to NAND Device
(NFI_state from IDLE state jump to READDATA state)
*NFI_CMD = 0x70;
(Issue command when SW write this APB address)
ase O
Start to read status or ID from NAND Device
//set number of read command of single read.
@ KC
*NFI_CON = 0x0090 If this is x8 NF device, this means read 4*(byte) data.
If this is x16 NF device, this means read 4 * (2byte) data.
Read Data by using PIO Mode
for (int i = 0 ; i < number of byte ; i++ ) { //PIO mode to read out read id.
while (*NFI_PIO_RDY == 0); //if the pio_rdy is not 1, keep polling.
xia E
pio_rdy = *NFI_PIO_RDY; //if the pio_rdy is equal to 1, data is available for read out.
read_status[i] = *NFI_DATAR; //The read out data from NFI_DATAR can be byte or word
ny AT
} //It depends on the setting of BYTE_RW in NFI_CNFG
Block Erase
Programming Sequence Memo
Configuration
To DI
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
*NFI_INTR_EN = 0x8 ; //Enable erase complete interrupt
//erase operation. (NFI_state from IDLE state jump to
*NFI_CNFG = 0x4000;
R E
ERASEDATA state)
Write Command and Address to NAND Device
M
// erase first command.
*NFI_CMD = 0x60;
(Issue command when SW write this APB address)
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
FO
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//erase second command. (NFI state from ERASEDATA state
*NFI_CMD = 0xD0;
US L
jump to ERASEBUSY state)
EO
*NFI_CNRNB = 0xf1
cn IA
nd
After 2 Command 0xD0, Waiting for Erase Done Interrupt
//After Nand flash from busy to ready will issue the IRQ.
Wait for interrupt ……
(NFI_state back to IDLE)
m. NT
Page Program ( Using DMA Mode )
Configure Memo
ECC Engine Configuration
//if hw_ecc_en is needed, set ECC configuration.
.co IDE
if (hw_ecc_en) {
(reference NFIECC Functional spec)
while ( *NFIECC_ENCIDLE == 0 ); //Polling IDLE signal until Encoder is available.
//Configure Encoder parameter in NFI mode.
//The setting must be referred to NFIECC document
*NFIECC_ENCCNFG = 0x10400010; //The encode size depends on the FDMECC setting
//0x10400010 means ENC_MS = 520 (512+8), the setting is
ccn NF
used for hwecc_en = 1, FDM_ECC_NUM = 8
*NFIECC_DECCON = 0x0 ; //make sure Decoder is close.
*NFIECC_ENCCON = 0x1 ; //enable Encoder.
}
ase O
NFI Configuration
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
@ KC
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
if ( custom_mode ) {
*NFI_CNFG = (0x6001 | auto_fmt_en
| hw_ecc_en | nfi_dma_burst )
} else {
xia E
*NFI_CNFG = (0x3001 | auto_fmt_en
//Setting NFI configuration according your usage.
| hw_ecc_en | nfi_dma_burst )
ny AT
}
*NFI_CON = 0x4000; //Set the length of Burst write
if (auto_fmt_en) {
*NFI_FDMxx = FDM_value //set FDM value
To DI
}
Write Command and Address to NAND Device
// write first command.
*NFI_CMD = 0x80; (Issue command when SW write this APB address)
R E
NFI_state from IDLE state jumps to PROGDATA state.
*NFI_COLADDR = col_addr ; //column address
M
*NFI_ROWADDR = row_addr ; //row address
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
*NFI_STRADDR = 0x1000_0000 //Write Data start address
Setting Interrupt,
*NFI_INTR_EN = 0x0042; //Set ahb_done and wr_done interrupt. Ahb_done interrupt
FO
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must be set after setting the length of burst write in NFI_CON
US L
and before burst write strobe.
EO
Trigger the BWR register and NFI start to write the data into NAND device
cn IA
*NFI_CON = *NFI_CON | 0x0200; //Set Burst write strobe.
if ( custom_mode ) *NFI_STRDATA = 1; //strobe to transfer data
//After Nand flash finishing transferring data from ahb bus into
wait for ahb done interrupt
NFI FIFO, AHB_DONE interrupt will be issued
m. NT
//polling when nf_tsf_num is not equal to expted transfer data
while (*NFI_ADDRCNTR != expected_nfi_tsf_num); number. This action is to guarantee all the data in NFI FIFO has
been written into NAND device.
// write second command.
.co IDE
*NFI_CMD = 0x10; (Issue command when SW write this APB address)
NFI_state from PROGDATA jumps to PROGBUSY.
*NFI_CNRNB = 0xf1
//After Nand flash from busy to ready will issue ready_return
Waiting for wr_done interrupt IRQ, also the write_done IRQ.
NFI state from PROGBUSY jumps to IDLE.
ccn NF
Page Program ( Using PIO Mode )
Configure Memo
ECC Engine Configuration
ase O
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en) {
(reference NFIECC Functional spec)
while ( *NFIECC_ENCIDLE == 0 ); //Polling IDLE signal until Encoder is available.
@ KC
//Configure Encoder parameter in NFI mode.
*NFIECC_ENCCNFG = 0x10400010; //The setting must be referred to NFIECC document
//The encode size depends on the FDMECC setting
*NFIECC_DECCON = 0x0 ; //make sure Decoder is close.
*NFIECC_ENCCON = 0x1 ; //enable Encoder.
xia E
}
NFI Configuration
ny AT
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
if ( custom_mode ) {
*NFI_CNFG = (0x6000 | auto_fmt_en
To DI
| hw_ecc_en )
} else {
*NFI_CNFG = (0x3000 | auto_fmt_en
//Setting NFI configuration according your usage.
R E
| hw_ecc_en )
}
M
*NFI_CON = 0x4000; //Set the length of Burst write
if ( custom_mode ) *NFI_STRDATA = 1; //strobe to transfer data
if (auto_fmt_en) {
*NFI_FDMxx = FDM_value //set FDM value
}
Write Command and Address to NAND Device
*NFI_CMD = 0x80; // write first command.
FO
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(Issue command when SW write this APB address)
US L
NFI_state from IDLE state jumps to PROGDATA state.
EO
*NFI_COLADDR = col_addr ; //column address
cn IA
*NFI_ROWADDR = row_addr ; //row address
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
m. NT
*NFI_STRADDR = 0x1000_0000 //Write Data start address
Setting Interrupt,
//Set ahb_done and wr_done interrupt. Ahb_done interrupt
*NFI_INTR_EN = 0x0042; must be set after setting the length of burst write in NFI_CON
.co IDE
and before burst write strobe.
Trigger the BWR register and NFI start to write the data into NAND device
*NFI_CON = *NFI_CON | 0x0200; //Set Burst write strobe.
Read Data by using PIO Mode
//PIO mode.
// if (~autofmt_en ) transfer size = sec_num*(512+spare_size)
ccn NF
// if ( autofmt_en ) transfer size = sec_num*(512+(spare_size-
for ( int i = 0; i < sec_num *(512+spare_size) ; i++ ) {
fdm_num) )
// The parity data in spare area must be read from NFIECC
register by MCU in PIO mode.
ase O
while (*NFI_PIO_RDY ==0x0 ) //if the pio_rdy is not 1, keep polling.
pio_rdy = *NFI_PIO_RDY;
@ KC
*NFI_DATAW = nfi_data[i]; //if the pio_rdy is equal to 1, data is available for write in.
}
nd
Check end condition and write 2 command to NAND device
//polling when nf_tsf_num is not equal to expted transfer data
while (*NFI_ADDRCNTR != expected_nfi_tsf_num); number. This action is to guarantee all the data in NFI FIFO has
been written into NAND device.
xia E
// write second command.
*NFI_CMD = 0x10; (Issue command when SW write this APB address)
ny AT
NFI_state from PROGDATA jumps to PROGBUSY.
*NFI_CNRNB = 0xf1
//After Nand flash from busy to ready will issue ready_return
Waiting for wr_done interrupt IRQ, also the write_done IRQ.
NFI state from PROGBUSY jumps to IDLE.
To DI
Page Read (DMA Mode)
Configure Memo
R E
ECC Engine Configuration
//if hw_ecc_en is needed, set ECC configuration.
M
if (hw_ecc_en) {
(reference NFIECC Functional spec)
dec_idle = *NFIECC_DECIDLE ; //Polling IDLE signal until Decoder is available.
while (dec_idle==0) ;
dec_idle = *NFIECC_DECIDLE ;
*NFIECC_DECCNFG = 0x90743010; //Configure Decoder parameter in NFI mode.
*NFIECC_ENCCON = 0x0 ; //make sure Encoder is close.
*NFIECC_DECCON = 0x1 ; //enable Decoder.
FO
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MT7621 PROGRAMMING GUIDE
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}
US L
NFI Configuration
EO
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
cn IA
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
if ( custom_mode ) {
*NFI_CNFG= (0x3003 | auto_fmt_en | hw_ecc_en |
m. NT
nfi_dma_burst )
} else {
*NFI_CNFG= (0x1003 | auto_fmt_en | hw_ecc_en |
//Setting NFI configuration according your usage.
nfi_dma_burst )
.co IDE
}
*NFI_INTR_EN = 0x0010; //Set busy_return interrupt
*NFI_STRADDR = 0x1000_0000 //Read Data start address
*NFI_CON = 0x4000; //Set length of Burst read
Write Command and Address to NAND Device
// read first command.
ccn NF
*NFI_CMD = 0x00; (Issue command when SW write this APB address)
NFI_state from IDLE state jumps to READBUSY state.
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
ase O
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
@ KC
while (*NFI_STA &0xf !== 0) ; //polling when programming state is not equal to 0.
// read second command.
*NFI_CMD = 0x30;
(Issue command when SW write this APB address)
*NFI_CNRNB = 0xf1
//After Nand flash from busy to ready will issue ready_return
Wait for ready_return interrupt IRQ.
xia E
NFI state from READBUSY jumps to READDATA.
Trigger the BWR register and NFI start to write the data into NAND device
ny AT
*NFI_CON = *NFI_CON | 0x0100; //Set Burst read strobe.
wait for ahb_done interrupt //After Nand flash from busy to ready will issue the IRQ.
//Polling bytelen; nf_tsf_num should be equal to expected
nfi_tsf_num = *NFI_BYTELEN;
transfer data number.
To DI
//polling when nf_tsf_num is not equal to expted transfer data
while (nfi_tsf_num !== expected_nfi_tsf_num)
number.
nfi_tsf_num = *NFI_BYTELEN;
//read AHB_done IRQ and read_done IRQ. nfi_irq_sta should
nfi_irq_sta = *NFI_INTR;
R E
be 0x41;
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en)
M
(reference NFIECC Functional spec)
dec_done = *NFIECC_DECDONE ; //Polling ECC Decoder Done signal.
while (dec_done !==0xf) ; //Because the sec_num is 4; according to sec_num;
dec_done = *NFIECC_DECDONE;
endif
Page Read (PIO Mode)
FO
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Configure Memo
US L
ECC Engine Configuration
EO
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en) {
cn IA
(reference NFIECC Functional spec)
dec_idle = *NFIECC_DECIDLE ; //Polling IDLE signal until Decoder is available.
while (dec_idle==0) ;
dec_idle = *NFIECC_DECIDLE ;
m. NT
*NFIECC_DECCNFG = 0x90743010; //Configure Decoder parameter in NFI mode.
*NFIECC_ENCCON = 0x0 ; //make sure Encoder is close.
*NFIECC_DECCON = 0x1 ; //enable Decoder.
}
.co IDE
NFI Configuration
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
if ( custom_mode ) {
*NFI_CNFG= (0x6003 | auto_fmt_en | hw_ecc_en |
ccn NF
nfi_dma_burst )
} else {
*NFI_CNFG= (0x1003 | auto_fmt_en | hw_ecc_en |
//Setting NFI configuration according your usage.
nfi_dma_burst )
ase O
}
*NFI_INTR_EN = 0x0010; //Set busy_return interrupt
@ KC
*NFI_STRADDR = 0x1000_0000 //Read Data start address
*NFI_CON = 0x4000; //Set length of Burst read
Write Command and Address to NAND Device
// read first command.
*NFI_CMD = 0x00; (Issue command when SW write this APB address)
NFI_state from IDLE state jumps to READBUSY state.
xia E
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
ny AT
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
while (*NFI_STA &0xf !== 0) ; //polling when programming state is not equal to 0.
// read second command.
*NFI_CMD = 0x30;
To DI
(Issue command when SW write this APB address)
*NFI_CNRNB = 0xf1
//After Nand flash from busy to ready will issue ready_return
Wait for ready_return interrupt IRQ.
R E
NFI state from READBUSY jumps to READDATA.
Trigger the BWR register and NFI start to write the data into NAND device
M
*NFI_CON = *NFI_CON | 0x0100; //Set Burst read strobe.
for ( int i = 1 ; i < sec_num*(512+fdm_size) ; i++ ){ //PIO mode.
pio_rdy = *NFI_PIO_RDY; //poling pio_ready register.
while (pio_rdy==0x0) //if the pio_rdy is not 1, keep polling.
pio_rdy = *NFI_PIO_RDY;
*NFI_DATAR = nfi_data[i]; //if the pio_rdy is equal to 1, data is available for write in.
}
FO
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//After NFI has read out all data from Nand Flash then issue
while (nfi_irq_b==0x1);
US L
read_done IRQ.
EO
nfi_irq_sta = *NFI_INTR; //read read_done IRQ. nfi_irq_sta should be 0x01;
cn IA
//Polling bytelen; nf_tsf_num should be equal to expected
nfi_tsf_num = *NFI_BYTELEN;
transfer data number. (make sure the FDM data is all read out)
//polling when nf_tsf_num is not equal to expted transfer data
while (nfi_tsf_num !== expected_nfi_tsf_num)
number.
m. NT
nfi_tsf_num = *NFI_BYTELEN;
dec_done = *NFIECC_DECDONE ; //Polling ECC Decoder Done signal.
while (dec_done !==0xf) ; //Because the sec_num is 4; according to sec_num;
dec_done = *NFIECC_DECDONE;
.co IDE
endif
Two block erase ( Pseudo-Code )
Configure Memo
Set Interrupt Reg (0x10) //Set busy to ready interrupt
Write command to NAND (0x60)
ccn NF
Write address to NAND ( First block address )
Write command to NAND (0x60)
Write address to NAND ( Second block address )
Write Command to NAND (0xd0)
ase O
Waiting for Interrupt …
Multiplane Page Program ( Pseudo-Code )
@ KC
Configure Memo
This reference pseudo code is for TOSHIBA NAND device
st
Write 1 Page to NAND Device
Write command to NAND (0x80)
st
Write address to NAND (The 1 address) Ex: NFI_ROWADDR = 0x100
xia E
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
custom_mode enabled
ny AT
Set Interrupt Reg (0x10) //Set busy to ready interrupt
Write_command(0x11)
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
Wait for B2R interrupt
To DI
nd
Write 2 Page to NAND Device
Reset NFI
Write command to NAND (0x80)
R E
nd
Write address to NAND ( The 2 address ) Ex: NFI_ROWADDR = 0x20100
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
M
custom_mode enabled
Set Interrupt Reg (0x10) //Set busy to ready interrupt
Write_command(0x11)
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
Wait for B2R interrupt
rd
Write 3 Page to NAND Device
FO
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Reset NFI
US L
Write command to NAND (0x80)
EO
rd
Write address to NAND ( The 3 address ) Ex: NFI_ROWADDR = 0x101
cn IA
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
custom_mode enabled
Set Interrupt Reg (0x10) //Set busy to ready interrupt
Write_command(0x11)
m. NT
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
Wait for B2R interrupt
th
Write 4 Page to NAND Device
.co IDE
Reset NFI
Write command to NAND (0x80)
th
Write address to NAND ( The 4 address ) Ex: NFI_ROWADDR = 0x20101
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
custom_mode enabled
Set Interrupt Reg (0x10) //Set busy to ready interrupt
ccn NF
Write_command(0x11)
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
Wait for B2R interrupt
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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US L
2.9 NFI ECC Controller
EO
2.9.1 Features
cn IA
ECC (BCH code) acceleration is capable of 4 bits correction in one full or shorten ECC coded block
size which is less than 8192 (<8192bits)
m. NT
Support data input in 8 bits in NFI mode and 32 bits in DMA / PIO mode and works in 122.88MHz.
Support encoder and decoder work separately in DMA and PIO mode and automatic error
correction.
.co IDE
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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2.9.2 Registers
US L
EO
cn IA
Address Name Width Register Function
1E003800 NFIECC_ENCCON 16 NFIECC Encoder Control Register
This register is for Encoder control.
1E003804 NFIECC_ENCCNFG 32 NFIECC Configure Register
m. NT
This register is for NFIECC encoder configuration.
1E003808 NFIECC_ENCDIADDR 32 NFIECC Encoder DI Memory Address Register
The register indicates the data start address of input data to the Encoder AHB
mode.
1E00380C NFIECC_ENCIDLE 16 NFIECC Encoder Idle Status Register
.co IDE
This register is for NFIECC Encoder idle status.
1E003810 NFIECC_ENCPAR0 32 NFIECC Parity0 Register
The register indicates the highest order of parity bits
1E003814 NFIECC_ENCPAR1 32 NFIECC Parity1 Register
The register indicates the parity bits
32
1E003818
ccn NF
NFIECC_ENCPAR2 NFIECC Parity2 Register
The register indicates the parity bits
1E00381C NFIECC_ENCPAR3 32 NFIECC Parity3 Register
The register indicates the parity bits
1E003820 NFIECC_ENCPAR4 32 NFIECC Parity4 Register
ase O
The register indicates the parity bits
1E003824 NFIECC_ENCSTA 32 NFIECC Encoder Status Register
@ KC
This register is for NFIECC Encoder status for SW polling.
1E003828 NFIECC_ENCIRQEN 16 NFIECC Encoder IRQ enable Register
This register is for software programmer to enable NFIECC IRQ signals (ignore in
NFI mode)
1E00382C NFIECC_ENCIRQSTA 16 NFIECC Encoder IRQ status Register
This register is for software programmer tracking NFIECC IRQ status. (ignore in
NFI mode)
xia E
1E003880 NFIECC_PIO_DIRDY 16 NFIECC PIO Data Ready Register
This register indicates the data is ready for input
ny AT
1E003884 NFIECC_PIO_DI 32 NFIECC PIO Data Register
The register indicates PIO mode data input by MCU
1E003900 NFIECC_DECCON 16 NFIECC Decoder Control Register
This register is for Decoder control.
To DI
1E003904 NFIECC_DECCNFG 32 NFIECC Decoder Configure Register
This register is for NFIECC configuration.
1E003908 NFIECC_DECDIADDR 32 NFIECC Decoder DI Memory Address Register
The register indicates the data start address of input data to the Decoder AHB
R E
mode.
1E00390C NFIECC_DECIDLE 16 NFIECC Decoder Idle Status Register
This register indicates the Decoder Idle status.
M
1E003910 NFIECC_DECFER 16 NFIECC Decoder Found Error Status Register
This register is for NFIECC Decoder status.
1E003914 NFIECC_DECENUM 32 NFIECC Decode Error Number Register
The register indicates the error number of the coded block.
1E003918 NFIECC_DECDONE 16 NFIECC Decoder Error Status Register
This register is for NFIECC Decoder done status.
1E00391C NFIECC_DECEL0 32 NFIECC Decoder Error location0 Register
FO
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The register indicates the error location of the decoding result
US L
1E003920 NFIECC_DECEL1 32 NFIECC Decoder Error Location1 Register
EO
The register indicates the error location of the decoding result.
cn IA
1E003924 NFIECC_DECEL2 32 NFIECC Decoder Error Location2 Register
The register indicates the error location of the decoding result.
1E003928 NFIECC_DECEL3 32 NFIECC Decoder Error Location3 Register
The register indicates the error location of the decoding result.
m. NT
1E00392C NFIECC_DECEL4 32 NFIECC Decoder Error Location4 Register
The register indicates the error location of the decoding result.
1E003930 NFIECC_DECEL5 32 NFIECC Decoder Error Location5 Register
The register indicates the error location of the decoding result.
1E003934 NFIECC_DECIRQEN 16 NFIECC Decoder IRQ enable Register
.co IDE
This register is for software programmer to enable NFIECC IRQ signals (ignore in
NFI mode)
1E003938 NFIECC_DECIRQSTA 16 NFIECC Decoder IRQ status Register
This register is for software programmer tracking NFIECC IRQ status. (ignore in
NFI mode)
1E00393C NFIECC_FDMADDR 32 NFIECC FDM Register Address
ccn NF
The register indicates the address of FDM data in NFI module.
1E003940 NFIECC_DECFSM 32 NFIECC Decoder FSM
The register indicates the finite state machine status of decoder.
1E003944 NFIECC_SYNSTA 32 NFIECC Syndrome Status Register
ase O
This register is for NFIECC Syndrom status.
1E003948 NFIECC_NFIDIDECNFI 32 NFIECC NFI input dataNFI input data Register
DI This register is for checking NFI input data.
@ KC
1E00394C NFIECC_SYN0 32 NFIECC Syndrom Register
The register indicates the error location of the decoding result.
1E003800 NFIECC_ENCCO NFIECC Encoder Control Register 0000
xia E
N
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Mne ENC
_EN
Type R/W
Reset 0
Bit(s) Name Description
To DI
0 ENC_EN indicates the enable in NFI mode and start to work in AHB mode. In AHB mode, parity bits is
remained in the PAR0~PAR4 register field until the ENC_EN is deasserted to 0.
0: means disable the Encode block.
1: means enable the Encode block. In AHB mode, the Encoder starts to fetch data when the
R E
register changes from 0 to 1. In NFI mode, the register enables the Encode block, and then the
Encoder module waits start signal and data from NFI.
M
1E003804 NFIECC_ENCCNF NFIECC Configure Register 00000000
G
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_MS
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Mne ENC ENC_MODE ENC_TNUM
EO
_BU
RST
cn IA
_EN
Type R/W R/W R/W
R/W
Reset 0 0 0 0 0 0
m. NT
Bit(s) Name Description
28:16 ENC_MS indicates the total bit size of message block including main data and control(FDM) data in the
NFI mode. The spare_ECC_num parameter in old version has been merged into the message
block_size parameter. If the block_size is equal to zero, the NFIECC do nothing.
The acceptable coded block size, which includes data and parity bits size, is 1~8191bits.
.co IDE
Different ENC_TNUM results in different parity bits, and also results in different maximum
message block size.
8 ENC_BURST_EN indicates the burst enalbe.
0: means DMA mode uses single read.
1: means DMA mode uses burst read.
5:4 ENC_MODE indicates the data source from access through AHB bus or from NFI.
00b: means source data from access through Bus. (DMA mode)
ccn NF
01b: means source data from NFI module. (NFI mode)
10b: means source data is written by MCU. (PIO mode)
11b: reserved mode.
2:0 ENC_TNUM indicates the correct capability in one block size. (Remove)
0: means the NFIECC is capable of correct 4 bits in one block size.
ase O
1: means the NFIECC is capable of correct 6 bits in one block size.
2: means the NFIECC is capable of correct 8 bits in one block size.
3: means the NFIECC is capable of correct 10 bits in one block size.
@ KC
4: means the NFIECC is capable of correct 12 bits in one block size.
1E003808 NFIECC_ENCDIA NFIECC Encoder DI Memory Address Register 00000000
DDR
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_DIADDR[29:14]
Type R/W
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_DIADDR[13:0]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:2 ENC_DIADDR indicates the memory address of input data to Encoder block in AHB mode. (4-Byte align)
R E
1E00380C NFIECC_ENCIDLE NFIECC Encoder Idle Status Register 0000
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC
_IDL
E
Type R
Reset 0
Bit(s) Name Description
FO
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0 ENC_IDLE indicates the Encode block in idle state and ready for new message block.
US L
0: means the Encode block is under working.
EO
1: means the Encode block is in Idle state and available for new message block.
cn IA
1E003810 NFIECC_ENCPAR NFIECC Parity0 Register 00000000
0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR0[31:16]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Mne ENC_PAR0[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 ENC_PAR0 indicates the highest order of output parity bits and the bit 0 is the highest order of parity
bit. The PAR0~PAR4 register is remain the last message block parity bits until ENC_EN is
ccn NF
deasserted. The parity bits should append after main data by order of {PAR0[31:0],
PAR1[31:0], PAR2[31:0], PAR3[31:0], PAR4[31:4], 4'b0}, The redundant bit of parity bit will
be padded by 0.
ase O
1E003814 NFIECC_ENCPAR NFIECC Parity1 Register 00000000
1
@ KC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR1[31:16]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR1[15:0]
xia E
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:0 ENC_PAR1 indicates the parity bits and the bit 0 is the highest order of parity bit.
To DI
1E003818 NFIECC_ENCPAR NFIECC Parity2 Register 00000000
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Mne ENC_PAR2[31:16]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR2[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 ENC_PAR2 indicates the parity bits and the bit 0 is the highest order of parity bit.
FO
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US L
EO
1E00381C NFIECC_ENCPAR NFIECC Parity3 Register 00000000
3
cn IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR3[31:16]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR3[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:0 ENC_PAR3 indicates the parity bits and the bit 0 is the highest order of parity bit.
1E003820 NFIECC_ENCPAR NFIECC Parity4 Register 00000000
4
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR4[27:16]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR4[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
27:0 ENC_PAR4 indicates the parity bits and the 31 is the highest order of parity bit.
xia E
1E003824 NFIECC_ENCSTA NFIECC Encoder Status Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ny AT
Mne COUNT_MS
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne COUNT_PS ENC_FSM
To DI
Type R R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
29:16 COUNT_MS indicates the remaining un-processing message bits.
15:7 COUNT_PS indicates the parity bits that have not read out from NFI.
M
5:0 ENC_FSM indicates encoder finite state machine state
6'd0: IDLE
6'd1: WAITIN
6'd2: BUSY
6'd4: PAROUT
1E003828 NFIECC_ENCIRQ NFIECC Encoder IRQ enable Register 0000
FO
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MT7621 PROGRAMMING GUIDE
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NL
EN
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Mne ENC
_IR
cn IA
QEN
Type R/W
Reset 0
m. NT
Bit(s) Name Description
0 ENC_IRQEN Encoder IRQ mask: triggered when Encoder operation is completed.
0: Disable
1: Enable
.co IDE
1E00382C NFIECC_ENCIRQ NFIECC Encoder IRQ status Register 0000
STA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC
ccn NF _IR
QST
A
Type RC
Reset 0
ase O
Bit(s) Name Description
0 ENC_IRQSTA indicates interrupt status for Encoder processing.
@ KC
0: No interrupt is generated.
1: An interrupt is pending and waiting for service. Active when Encoder processing is done.
1E003880 NFIECC_PIO_DIR NFIECC PIO Data Ready Register 0000
DY
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PIO_
ny AT
DI_R
DY
Type R
Reset 0
To DI
Bit(s) Name Description
0 PIO_DI_RDY indicates the PIO mode (Encoder/Decoder) is ready for input data.
0: ECC is busy. During busy state, NFIECC_PIO_DI should not be over-write.
1: ECC is ready for input data. In PIO mode, write next PIO_DI when pio_di_rdy is equal to 1.
R E
M
1E003884 NFIECC_PIO_DI NFIECC PIO Data Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne PIO_DI[31:16]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PIO_DI[15:0]
Type R/W
FO
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MT7621 PROGRAMMING GUIDE
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NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit(s) Name Description
cn IA
31:0 PIO_DI indicates the PIO mode data input.
1E003900 NFIECC_DECCO NFIECC Decoder Control Register 0000
m. NT
N
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC
_EN
Type R/W
.co IDE
Reset 0
Bit(s) Name Description
0 DEC_EN indicates the enable in NFI mode and start to work in AHB mode. In AHB mode, the decode-
status FER and error number registers and error location registers will be reset to 0 when
DEC_EN is deasserted.
ccn NF
0: means disable the Decode block.
1: means enable the Decode block. In AHB mode, the Decoder starts to fetch data when the
register changes from 0 to 1. In NFI mode, the register enables the Decode block, and then the
Decoder module waits start signal and data from NFI.
ase O
1E003904 NFIECC_DECCNF NFIECC Decoder Configure Register 00003000
@ KC
G
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC DEC_CS
_EM
PTY
_EN
Type R/W R/W
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_CON DEC DEC_MODE DEC_TNUM
ny AT
_BU
RST
_EN
Type R/W R/W R/W R/W
R/W
Reset 1 1 0 0 0 0 0 0
To DI
Bit(s) Name Description
31 DEC_EMPTY_EN indicates the Decoder automatically detects the empty source data and by pass the auto-
correction block (data are all equal to 1). (ignore in AHB_mode)
R E
0: means disenable the detection of empty source data.
1: means enable the detection of empty source data.
M
28:16 DEC_CS indicates the total bit size of coded block including protected data and parity bits. The
acceptable coded block size is 1~8191bits. If the coded block size is equal to zero, the
decoder does nothing. The detail figure shows in Figure 2.
13:12 DEC_CON indicates the bypass configuration in decoding processor.
0: is reserved
1: means only active syndrome calculator for error detecting purpose. ECC reports DONE and
FER status after syndrome calculator is done.
2: means error-correction module is bypassed for being aware of error location purpose. ECC
reports DONE, FER, EL and ERRNUM status after Chien search is done.
FO
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MT7621 PROGRAMMING GUIDE
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3: means the ECC processor decoded data and auto-correction error data. The data address is
signaled by DEC_DIADDR register in AHB mode and NFI_DIADDR in NFI mode. ECC reports
US L
EO
DONE, FER, EL and ERRNUM status after error-correction is done.
8 DEC_BURST_EN indicates the burst enalbe.
cn IA
0: means DMA mode uses single read.
1: means DMA mode uses burst read.
5:4 DEC_MODE indicates the data source from access AHB bus or from NFI.
00b: means source data from access through Bus. (DMA mode)
m. NT
01b: means source data from NFI module. (NFI mode)
10b: means source data is written by MCU. (PIO mode)
11b: Reserved mode.
2:0 DEC_TNUM indicates the correct capability in one block size.
0: means the Decoder is capable of correct 4 bits in one block size.
1: means the Decoder is capable of correct 6 bits in one block size.
.co IDE
2: means the Decoder is capable of correct 8 bits in one block size.
3: means the NFIECC is capable of correct 10 bits in one block size.
4: means the NFIECC is capable of correct 12 bits in one block size.
1E003908 NFIECC_DECDIA NFIECC Decoder DI Memory Address Register 00000000
ccn NF
DDR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_DIADDR[29:14]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_DIADDR[13:0]
Type R/W
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:2 DEC_DIADDR indicates the memory address of input data to the Decoder block in AHB mode. (4-Byte
align).
xia E
ny AT
1E00390C NFIECC_DECIDLE NFIECC Decoder Idle Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC
_IDL
E
Type R
To DI
Reset 0
Bit(s) Name Description
R E
0 DEC_IDLE indicates the Decode block is in idle state and ready for new coded block.
0: means the Decode block is under working.
1: means the Decode block is in idle state and available for new coded block.
M
1E003910 NFIECC_DECFER NFIECC Decoder Found Error Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FER FER FER FER FER FER2 FER FER
7 6 5 4 3 1 0
Type R R R R R R R R
Reset 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
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Bit(s) Name Description
EO
7 FER7 indicates the error found or not in the coded block. The FER numbered by NFI sector number
cn IA
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
6 FER6 indicates the error found or not in the coded block. The FER numbered by NFI sector number
m. NT
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
5 FER5 indicates the error found or not in the coded block. The FER numbered by NFI sector number
.co IDE
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
4 FER4 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
ccn NF 0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
3 FER3 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
ase O
1: means there is(are) error(s) detected in the coded block.
2 FER2 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
@ KC
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
1 FER1 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
xia E
1: means there is(are) error(s) detected in the coded block.
0 FER0 indicates the error found or not in the coded block. The FER numbered by NFI sector number
ny AT
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
To DI
1E003914 NFIECC_DECENU NFIECC Decode Error Number Register 00000000
M
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ERRNUM7 ERRNUM6 ERRNUM5 ERRNUM4
Type R R R R
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ERRNUM3 ERRNUM2 ERRNUM1 ERRNUM0
Type R R R R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:28 ERRNUM7 indicates the error numbers of coded block in one start signal. 4'hf means the error is
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MT7621 PROGRAMMING GUIDE
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uncorrectable.
US L
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
EO
capability, ECC only can partially detect the situation.
27:24 ERRNUM6 indicates the error numbers of coded block in one start signal. 4'hf means the error is
cn IA
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
23:20 ERRNUM5 indicates the error numbers of coded block in one start signal. 4'hf means the error is
m. NT
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
19:16 ERRNUM4 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
.co IDE
capability, ECC only can partially detect the situation.
15:12 ERRNUM3 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
11:8 ERRNUM2 indicates the error numbers of coded block in one start signal. 4'hf means the error is
ccn NF uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
7:4 ERRNUM1 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
ase O
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
3:0 ERRNUM0 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
@ KC
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
1E003918 NFIECC_DECDO NFIECC Decoder Error Status Register 0000
xia E
NE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Mne DON DON DON DON DON DON DON DON
E7 E6 E5 E4 E3 E2 E1 E0
Type R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
7 DONE7 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
R E
in the Table 7.
6 DONE6 indicates the Decoding procedure is done.
M
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
5 DONE5 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
FO
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4 DONE4 indicates the Decoding procedure is done.
US L
0: means the Decode block is under working.
EO
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
cn IA
in the Table 7.
3 DONE3 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
m. NT
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
2 DONE2 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
.co IDE
in the Table 7.
1 DONE1 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
0 DONE0 indicates the Decoding procedure is done.
ccn NF
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
ase O
1E00391C NFIECC_DECEL0 NFIECC Decoder Error location0 Register 00000000
@ KC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL10
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL01
Type R
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
28:16 DEC_EL10 indicates the error location 1 of the decoding result.
12:0 DEC_EL01 indicates the error location 0 of the decoding result. The EL remains until the DEC_EN is
deasserted to 0 in both AHB and NFI mode. When the error number is less than 12, error
location registers will be filled from DEC_EL0, and the redundant register fields remain 0.
To DI
1E003920 NFIECC_DECEL1 NFIECC Decoder Error Location1 Register 00000000
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL3
Type
M
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL2
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 DEC_EL3 indicates the error location 3 of the decoding result.
FO
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12:0 DEC_EL2 indicates the error location 2 of the decoding result.
US L
EO
cn IA
1E003924 NFIECC_DECEL2 NFIECC Decoder Error Location2 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL5
Type R
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL4
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
28:16 DEC_EL5 indicates the error location 5 of the decoding result.
12:0 DEC_EL4 indicates the error location 4 of the decoding result.
ccn NF
1E003928 NFIECC_DECEL3 NFIECC Decoder Error Location3 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL7
Type R
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL6
@ KC
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 DEC_EL7 indicates the error location 7 of the decoding result.
12:0 DEC_EL6 indicates the error location 6 of the decoding result.
xia E
ny AT
1E00392C NFIECC_DECEL4 NFIECC Decoder Error Location4 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL9
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL8
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
M
28:16 DEC_EL9 indicates the error location 9 of the decoding result.
12:0 DEC_EL8 indicates the error location 8 of the decoding result.
1E003930 NFIECC_DECEL5 NFIECC Decoder Error Location5 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL11
FO
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MT7621 PROGRAMMING GUIDE
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Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL10
cn IA
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
28:16 DEC_EL11 indicates the error location 11 of the decoding result.
12:0 DEC_EL10 indicates the error location 10 of the decoding result.
.co IDE
1E003934 NFIECC_DECIRQ NFIECC Decoder IRQ enable Register 0000
EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC
_IR
QEN
Type R/W
ccn NF
Reset 0
Bit(s) Name Description
0 DEC_IRQEN Decoder IRQ mask: triggered when Decoder operation is completed.
ase O
0: Disable
1: Enable
@ KC
1E003938 NFIECC_DECIRQ NFIECC Decoder IRQ status Register 0000
STA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC
xia E
_IR
QST
A
ny AT
Type RC
Reset 0
Bit(s) Name Description
0 DEC_IRQSTA indicates Interrupt status for Decoder processing.
To DI
0: No interrupt is generated.
1: An interrupt is pending and waiting for service. Active when Decoder processing is done.
R E
1E00393C NFIECC_FDMAD NFIECC FDM Register Address 00000000
DR
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FDM_ADDR[31:16]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FDM_ADDR[15:0]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
Bit(s) Name Description
EO
31:0 FDM_ADDR indicates the APB register address of FDM data in NFI module.
cn IA
1E003940 NFIECC_DECFSM NFIECC Decoder FSM 00000000
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne AUTOC_FSM CHIEN_FSM
Type R/W R
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne BMA_FSM SYN_FSM
.co IDE
Type R/W R
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:24 AUTOC_FSM indicates the status of auto-correction stage.
5'd0: IDLE
ccn NF
5'd1: READ
5'd2: WRITE
5'd4: DONE
20:16 CHIEN_FSM indicates the status of Chien search stage.
5'd0: IDLE
ase O
5'd1: BUSY
5'd2: DONE
12:8 BMA_FSM indicates the status of BMA stage.
@ KC
5'd0: IDLE
5'd1: BUSY
5'd2: DONE
5:0 SYN_FSM indicates the status of syndrome stage.
6'd0: IDLE
6'd1: WAITIN
6'd2: BUSY
xia E
6'd4: DONE
ny AT
1E003944 NFIECC_SYNSTA NFIECC Syndrome Status Register NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne SYN_SNUM DIBW NFI_SEC_NUMNFI_S
EC_NUM
To DI
Type 0 R RR
Reset R R R 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_ SYN_COUNT_CS
R E
STR
_SET
Type R R
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:29 SYN_SNUM indicates the sector number recorded by syndrome.
25:20 DIBW indicates input bandwidth.
18:16 NFI_SEC_NUMNFI_SEC_N indicates the sector number from NFI.
UM
15 NFI_STR_SET indicates the NFI_STR signal from NFI.
FO
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MT7621 PROGRAMMING GUIDE
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NL
13:0 SYN_COUNT_CS indicates the remaining un-processing coded block bits.
US L
EO
cn IA
1E003948 NFIECC_NFIDIDE NFIECC NFI input dataNFI input data Register NA
CNFIDI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Mne NFI_DINFI_DI[31:16]
Type 0
Reset RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_DINFI_DI[15:0]
Type 0
.co IDE
Reset RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR
Bit(s) Name Description
31:0 NFI_DINFI_DI indicates the latest 4 byte input data from nfi.
ccn NF
1E00394C NFIECC_SYN0 NFIECC Syndrom Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_SYN3
Type R
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_SYN1
@ KC
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 DEC_SYN3 informs the syndrome 3 from syndrome calculator.
12:0 DEC_SYN1 informs the syndrome 1 from syndrome calculator.
xia E
ny AT
2.9.3 Programming Guide
This section lists the program sequences for ECC operations.
To DI
Encoding in NFI mode
Caution: Before NFI address phase enable and configure ECC.
Configure Memo
R E
*NFIECC_ENCCNFG = 0x10400010; //configure Encoder parameter in NFI mode.
*NFIECC_ENCCON = 0x1 ; //enable Encoder.
M
while (NFI_STR==0x1) ; //NFI_STR is happened in NFI address phase. NFI_STR is from NFI.
0 = *NFIECC_ENCIDLE ; //It indicates the start is triggered and Encoder is in busy state.
//Wait all message data from NFI. After all data has input IDLE will be
while (*NFIECC_ENCIDLE==0x1) ;
asserted.
parity = {*NFIECC_PAR0,*NFIECC_PAR1,
*NFIECC_PAR2, *NFIECC_PAR3, //If parity is necessary, Read out parity from APB register after IDLE=1.
*NFIECC_PAR4}
FO
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Encoding in DMA mode
EO
Configure Memo
cn IA
while (*NFIECC_ENCIDLE==1) ; //polling IDLE signal until Encoder is available.
*NFIECC_ENCCNFG = 0x10400010; //configure Encoder parameter in NFI mode.
*NFIECC_ENCIRQEN = 0x1; //If IRQ is required when Encoder is done.
*NFIECC_ENCDIADDR= 0x10000000; //Configure Data start address.
m. NT
*NFIECC_ENCCON = 0x1 ; //Encoder starts fetching data from ENCDIADDR.
0 = *NFIECC_ENCIDLE ; //It indicates the start is triggered and Encoder is in busy state.
while (*NFIECC_ENCIDLE==0x1) ; //After all data has fetched and encoded, IDLE will be asserted.
parity = {*NFIECC_PAR0,*NFIECC_PAR1,
// Read out parity from APB register after IDLE=1 and must append parity
.co IDE
*NFIECC_PAR2, *NFIECC_PAR3,
bits behind the original data for decoding.
*NFIECC_PAR4}
Encoding in PIO mode
Configure Memo
ccn NF
while (*NFIECC_ENCIDLE==1) ; //polling IDLE signal until Encoder is available.
*NFIECC_ENCCNFG = 0x10400010; //configure Encoder parameter in NFI mode.
*NFIECC_ENCIRQEN = 0x1; //If IRQ is required when Encoder is done.
*NFIECC_ENCCON = 0x1 ; //Encoder starts.
ase O
while (*NFIECC_PIO_DIRDY==0x1) { //Wait the NFIECC_PIO_DIRDY is active then
*NFIECC_PIO_DI = DATA[i]; i++ } //Input data 32bit by 32bit input NFIECC_PIO_DI APB register.
@ KC
//After all data has been written in PIO_DI and encoder has been done, IDLE
while (*NFIECC_ENCIDLE==0x1) ;
will be asserted.
parity = {*NFIECC_PAR0,*NFIECC_PAR1,
// Read out parity from APB register after IDLE=1 and must append parity
*NFIECC_PAR2, *NFIECC_PAR3,
bits behind the original data for decoding.
*NFIECC_PAR4}
xia E
Decoding in NFI mode
ny AT
Caution: Before NFI address phase enable and configure ECC.
Caution: When NFI AUTO_FMT_EN=0, ECC will correct all errors (include parity bits) found in Chien search.
Be careful of those FDM data that was not protected by ECC. Those data would not be realized by ECC
module and might be polluted by ECC module.
Caution: ECC correct limitation is error_limit = error_correct_capability. If the error number(data error
To DI
number + parity error number) is bigger than the error_limit, ECC might decode error.
Configure Memo
*NFIECC_DECCNFG = 0x90743010; //configure Decoder parameter in NFI mode.
R E
//configure FDM0 APB address in NFI mode into FDMADDR.
*NFIECC_FDMADDR = 0x800320A0;
(NFI_BASE_ADDR+FDM0_OFFSET_ADDR)
M
*NFIECC_DECCON = 0x1 ; //enable Decoder.
for i = 1:8 // 8 is equal to NFI read sector number.
while (NFI_STR==0x1) ; //NFI_STR is happened in NFI address phase. NFI_STR is from NFI.
0 = *NFIECC_DECIDLE ; //It indicates the start is triggered and Decoder is in busy state.
//Wait all message data from NFI. After all data has input IDLE will be
while (*NFIECC_DECIDLE==0x1) ;
asserted and FER will be reported.
end for
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while (*NFIECC_DECDONE==0xff) //Decoder and correction processor is done.
US L
Additional Usage for detecting error number or uncorrectable error (execute after Done)
EO
while (*NFIECC_DECFSM==0x0) //All Hardware is done
cn IA
ERR_SEC = *NFIECC_FER //Read Error status
for i = 0 : (SEC_NUM-1)
if (ERR_SEC[i] == 1) //If the sector has error
ERR_NUM = *NFIECC_DECENUM //Read Error number
m. NT
end if
//Read Error Location to check if location exceeds coded data size. If error
for i = 0 : (ERR_NUM-1)
location exceeds coded data size, it is an uncorrected decoding sector.
ErrorLocation[i] = *NFIECC_EL0+2i;
.co IDE
end for
end for
*NFIECC_DECCON = 0x0 //Disable Decoder.
Decoding in DMA mode
Configure Memo
ccn NF
while (*NFIECC_DECIDLE==1) ; //polling IDLE signal until Decoder is available.
*NFIECC_DECCNFG = 0x90743010; //configure Decoder parameter in NFI mode.
*NFIECC_DECIRQEN = 0x1; //If IRQ is required when Encoder is done.
*NFIECC_DECDIADDR= 0x10000000; //Configure Data start address.
ase O
*NFIECC_DECCON = 0x1 ; //Decoder starts to fetch data from DECDIADDR.
0 = *NFIECC_DECIDLE ; //It indicates the start is triggered and Decoder is in busy state.
@ KC
while (*NFIECC_DECDONE==0x1) //Decoder and correction processor is done.
Additional Usage for detecting error number or uncorrectable error (execute after Done)
while (*NFIECC_DECFSM==0x0) //All Hardware is done
ERR_SEC = *NFIECC_FER //Read Error status
for i = 0 : (SEC_NUM-1) //In DMA mode only support SEC_NUM=1
if (ERR_SEC[i] == 1) //If the sector has error
xia E
ERR_NUM = *NFIECC_DECENUM //Read Error number
end if
ny AT
//Read Error Location to check if location exceeds coded data size. If error
for i = 0 : (ERR_NUM-1)
location exceeds coded data size, it is an uncorrected decoding sector.
ErrorLocation[i] = *NFIECC_EL0+2i;
end for
end for
To DI
*NFIECC_DECCON = 0x0 //Disable Decoder.
Decoding in PIO mode
R E
Configure Memo
while (*NFIECC_DECIDLE==1) ; //polling IDLE signal until Decoder is available.
M
*NFIECC_DECCNFG = 0x90743010; //configure Decoder parameter in NFI mode.
*NFIECC_DECIRQEN = 0x1; //If IRQ is required when Encoder is done.
*NFIECC_DECCON = 0x1 ; //Decoder starts.
while (*NFIECC_PIO_DIRDY==0x1) { //Wait the NFIECC_PIO_DIRDY is active then
*NFIECC_PIO_DI = DATA[i]; i++ } //Input data 32bit by 32bit input NFIECC_PIO_DI APB register.
while (*NFIECC_DECDONE==0x1) //Decoder and correction processor is done.
Additional Usage for detecting error number or uncorrectable error (execute after Done)
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while (*NFIECC_DECFSM==0x0) //All Hardware is done
US L
ERR_SEC = *NFIECC_FER //Read Error status
EO
for i = 0 : (SEC_NUM-1) //In PIO mode only support SEC_NUM=1
cn IA
if (ERR_SEC[i] == 1) //If the sector has error
ERR_NUM = *NFIECC_DECENUM //Read Error number
end if
//Read Error Location to check if location exceeds coded data size. If error
m. NT
for i = 0 : (ERR_NUM-1)
location exceeds coded data size, it is an uncorrected decoding sector.
ErrorLocation[i] = *NFIECC_EL0+2i;
end for
end for
.co IDE
*NFIECC_DECCON = 0x0 //Disable Decoder.
ccn NF
ase O
@ KC
xia E
ny AT
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R E
M
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2.10 PCM Controller
EO
2.10.1 Features
cn IA
Two clock sources are reserved for PCM circuit. (From internal clock generator, INT_PCM_CLK and
EXT_PCM_CLK)
PCM module can drive a clock out (with fraction-N dividor) to an external codec.
m. NT
Up to 4 channels PCM are available. 4 to 128 slots are configurable.
Each channel supports a-law (8-bit)/u-law (8-bit)/raw-PCM (8-bit and 16-bit) transfer.
Hardware converter of a-law<->raw-16 and u-law <-> raw-16 are implemented in design.
Support long (8 cycle)/short (1 cycle)/configurable (intervals are configurable, use to emulate I S
2
interface) FSYNC.
.co IDE
DATA & FSYNC can be driven and sampled by either rising/falling of clock.
Last bit of DTX can be configured as tri-stated on falling edge.
Beginning of each slot is configurable by 10-bit registers on each channel.
32-byte FIFO are available for each channel
PCM interface can emulate I2S interface (only 16-bit data-width supported ).
ccn NF
MSB/LSB order is configurable.
Supports both a-law/u-law (8-bits) linear PCM(16-bit) and linear PCM(16-bit) a-law/u-law (8-bit)
2.10.2 Block Diagram
PCM Module
ase O
APBBUS
@ KC
PCM Control
APBBUS LTF
Status Register
xia E
RFIFO TFIFO RFIFO TFIFO
(32 bytes) (32 bytes) (32 bytes) (32 bytes)
ny AT
DRAM CH1 CH0
GDMA LTF
To DI
a/ulaw a/ulaw
SYS clock domain
R E
PCM clock domain
M
PCM IF/I2S IF
Figure 2-4 PCM Controller Block Diagram
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Two clock domains are partitioned in this design. PCM converter (u-law < = > raw-16-bit and A-law < = > raw
US L
16-bit) are implemented in PCM. The threshold of FIFO is configurable. When the threshold is reached, PCM (a)
EO
triggers the DMA interface to notify external DMA engine to transfer data, and (b) triggers an interrupt to the
cn IA
host.
The interrupt sources include:
The threshold is reached.
FIFO is under-run or over-run.
m. NT
A fault is detected at the DMA interface.
The A-law and u-law converter is implemented based on the ITU-G.711 A-law and u-law table. In this design,
both A-law/u-law(8-bit) linear PCM (16-bit) and linear PCM (16-bit) A-law/u-law (8-bit) are supported.
The data-flow from codec to PCM-controller (Rx-flow) is shown as below:
.co IDE
The PCM controller latches the data from DRX at the indicated time slot and then writes it to FIFO. If FIFO
is full, the data is lost.
When the Rx-FIFO reaches the threshold, two actions may be taken:
When DMA_ENA=1, DMA_REQ is asserted to request a burst transfer. It rechecks the FIFO threshold
after DMA_END is asserted by GDMA. (GDMA should be configured before channel is enabled.)
Assert the interrupt source to notify the host. The host can check RFIFO_AVAIL information then get
ccn NF
back the data from FIFO.
The data flow from the PCM controller to codec (Tx-flow) is shown below. After GDMA is configured, software
should configure and enable the PCM channel. The empty FIFO should behave as follows.
ase O
When DMA_ENA=1, DMA_REQ is triggered to request a burst transfer. It then re-checks the FIFO
threshold after DMA_END is asserted by GDMA (a burst is completed).
@ KC
The Interrupt source is asserted to notify HOST. HOST writes the data to Tx-FIFO. After that, HOST
rechecks TFIFO_EMPTY information, and then writes more data if available.
NOTE: When DMA_ENA=1, the burst size of GDMA should be less than the threshold value.
xia E
ny AT
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R E
M
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2.10.3 List of Registers
EO
PCM Changes LOG
cn IA
Revision Date Author Change Log
0.1 2012/10/8 Paddy Wu Initialization
m. NT
Module name: PCM Base address: (+1E002000h)
Address Name Widt Register Function
h
.co IDE
1E002000 GLB_CFG 32 Global Config
1E002004 PCM_CFG 32 PCM configuration
1E002008 INT_STATUS 32 Interrupt status
1E00200C INT_EN 32 Interrupt enable
1E002010 CHA0_FF_STATU 32 Channel A0(represents channel 0) FIFO status
S
ccn NF
1E002014 CHB0_FF_STATU 32 Channel B0(represents channel 1) FIFO status
S
1E002020 CHA0_CFG 32 Channel A0(represents channel 0) Config
1E002024 CHB0_CFG 32 Channel B0(represents channel 1) Config
ase O
1E002030 FSYNC_CFG 32 FSYNC config
1E002034 CHA0_CFG2 32 Channel A0(represents channel 0) Config
1E002038 CHB0_CFG2 32 Channel B0(represents channel 1) Config
@ KC
1E002040 IP_INFO 32 IP version info
1E002044 RSV_REG16 32 SPARE REG 16 bits
1E002050 DIVCOMP_CFG 32 Dividor Compensation part config
1E002054 DIVINT_CFG 32 Dividor Integer part config
1E002060 DIGDELAY_CFG 32 Digital delay config
xia E
1E002080 CH0_FIFO 32 Channel 0 FIFO access point
1E002084 CH1_FIFO 32 Channel 1 FIFO access point
ny AT
1E002088 CH2_FIFO 32 Channel 2 FIFO access point
1E00208C CH3_FIFO 32 Channel 3 FIFO access point
1E002110 CHA0_FF_STATU 32 Channel A1(represents channel 3) FIFO status
S
To DI
1E002114 CHB1_FF_STATU 32 Channel B1(represents channel 4) FIFO status
S
1E002120 CHA1_CFG 32 Channel A1(represents channel 3) Config
1E002124 CHB1_CFG 32 Channel B1(represents channel 1) Config
R E
1E002134 CHA1_CFG2 32 Channel A1(represents channel 3) Config
1E002138 CHB1_CFG2 32 Channel B1(represents channel 4) Config
M
1E002000 GLB_CFG Global Config 0044000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PC DM LB EXT
RSV0 RFF_THRES
RS
TFF_THRES
M_ A_E K_E _LB V1
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EN N N K_E
US L
N
EO
Type RW RW RW RW RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV2 CH_EN
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31 PCM_EN PCM Enable
When disabled, all FSM of PCM are cleared to their default value.
0: disable
1: enable
.co IDE
30 DMA_EN DMA Enable
0: Disable the DMA interface, transfer data using software.
1: Enable the DMA interface, transfer data using DMA.
0: disable
1: enable
29 LBK_EN loopback enable, loopback path is shown as (Asyn-TXFIFO ->DTX -> DRX->Asyn-
ccn NF RXFIFO)
0: disable
1: enable
28 EXT_LBK_EN loopback enable, loopback path is shown as (Ext-Codec->DRX->DTX->Ext-
Codec)
0: disable
ase O
1: enable
27:23 RSV0 Reserved
@ KC
22:20 RFF_THRES RXFIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO. The threshold
should be >2 and <6.
When data in FIFO is under the threshold, the following interrupts and GDMA are
triggered.
CH0T_THRES, CH0R_THRES, CH1T_THRES, CH1R_THRES
(unit: word)
xia E
19 RSV1 Reserved
18:16 TFF_THRES TXFIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO.
ny AT
It should be >2 and <6.
When data in FIFO is over the threshold, an interrupt and DMA are triggered.
(unit: word)
15:4 RSV2 Reserved
3:0 CH_EN Channels 3 to 0 Tx and Rx Enable
To DI
0: disable
1: enable
R E
1E002004 PCM_CFG PCM configuration 0300000
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL EXT LO FSY
DT
RS KO _FS NG NC
RSV1 X_T RSV2[20:13]
V0 UT_ YN _SY _P
RI
EN C NC OL
Type RO RW RO RW RW RW RW RO
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Name RSV2[12:0] SLOT_MODE
US L
Type RO RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31 RSV0 Reserved
30 CLKOUT_EN PCM Clock Out Enable
m. NT
0: A PCM clock is provided from the external Codec/OSC.
1: A PCM clock is provided from the internal dividor.
NOTE: Normally, the register should be asserted to 1. Also, it should be asserted after
configuring the divider and enabling the divider clock.
0: EXT_CLK
1: INT_DIV
.co IDE
29:28 RSV1 Reserved
27 EXT_FSYNC FSYNC is provided externally
0: FSYNC is generated by internal circuit.
1: FSYNC is provided externally
26 LONG_SYNC FSYNC Mode
0: Short FSYNC
1: Long FSYNC
ccn NF
25 FSYNC_POL FSYNC Polarity
0: FSYNC is low active
1: FSYNC is high active
24 DTX_TRI DTX Tri-State
ase O
Tristates DTX when the clock signal on the last bit is has a falling edge.
0: Non- tristate DTX
1: Tristate DTX
@ KC
23:3 RSV2 Reserved
2:0 SLOT_MODE Sets the number of slots in each PCM frame.
0: 4 slots, PCM clock out/in should be 256 KHz.
1: 8 slots, PCM clock out/in should be 512 KHz.
2: 16 slots, PCM clock out/in should be 1.024 MHz.
3: 32 slots, PCM clock out/in should be 2.048 MHz.
4: 64 slots, PCM clock out/in should be 4.096 MHz.
5:128 slots, PCM clock out/in should be 8.192 MHz.
xia E
Other: Reserved.
NOTE: When using the external clock, the frequency clock should be equal to
PCM_clock out. Otherwise, the PCM_CLKin should be 8.192 MHz.
ny AT
0: _4_SLOT
1: _8_SLOT
2: _16_SLOT
3: _32_SLOT
4: _64_SLOT
5: _128_SLOT
To DI
1E002008 INT_STATUS Interrupt status 0000000
R E
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name RSV0[23:8]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
CH CH CH
CH CH CH
CH
T_D R_ R_ R_
T_O T_U T_T R_T
RSV0[7:0] MA DM OV UN
VR NR HR HR
_FA A_F RU RU
UN UN ES ES
ULT AU N N
FO
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LT
US L
Type RO
W1 W1 W1 W1 W1 W1 W1 W1
EO
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31:8 RSV0 Reserved
7 CHT_DMA_FAULT Channel Tx DMA Fault Interrupt, Asserts when a fault has been detected in a CH-
m. NT
Tx DMA signal.
6 CHT_OVRUN Channel Tx FIFO Overrun Interrupt, Asserts when the CH-Tx FIFO is overrun.
5 CHT_UNRUN Channel Tx FIFO Underrun Interrupt, Asserts when the CH-Tx FIFO is underrun.
4 CHT_THRES Channel Tx Threshold Interrupt, Asserts when the CH-Tx FIFO is lower than the
defined threshold.
.co IDE
3 CHR_DMA_FAULT Channel Rx DMA Fault Interrupt, Asserts when a fault is detected in a CH-Rx
DMA signal.
2 CHR_OVRUN Channel Rx Overrun Interrupt, Asserts when the CH-Rx FIFO is overrun.
1 CHR_UNRUN Channel Rx Underrun Interrupt, Asserts when the CH-Rx FIFO is underrun.
0 CHR_THRES Channel Rx Threshold Interrupt, Asserts when the CH-Rx FIFO is lower than the
defined threshold.
ccn NF
1E00200C INT_EN Interrupt enable 0000000
0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
@ KC
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name INT INT INT INT INT INT INT INT
RSV0[7:0] 7_E 6_E 5_E 4_E 3_E 2_E 1_E 0_E
N N N N N N N N
Type RO RW RW RW RW RW RW RW RW
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ny AT
31:8 RSV0 Reserved
7 INT7_EN INT_STATUS[7] Enable,Enables the Channel Tx DMA Fault Interrupt. This
interrupt asserts when a fault has been detected in a CH-Tx DMA signal.
6 INT6_EN INT_STATUS[6] Enable,Enables the Channel Tx FIFO Overrun Interrupt. This
interrupt asserts when the CH-Tx FIFO is overrun.
To DI
5 INT5_EN INT_STATUS[5] Enable,Enables the Channel Tx FIFO Underrun Interrupt. This
interrupt asserts when the CH-Tx FIFO is underrun.
4 INT4_EN INT_STATUS[4] Enable,Enables the Channel Tx Threshold Interrupt. This
interrupt when the CH-Tx FIFO is lower than the defined threshold.
R E
3 INT3_EN INT_STATUS[3] Enable,Enables the Channel Rx DMA Fault Interrupt. This
interrupt when a fault is detected in a CH-Rx DMA signal.
M
2 INT2_EN INT_STATUS[2] Enable,Enables the Channel Rx Overrun Interrupt. This interrupt
when the CH-Rx FIFO is overrun.
1 INT1_EN INT_STATUS[1] Enable,Enables the Channel Rx Underrun Interrupt. This
interrupt when the CH-Rx FIFO is under-run.
0 INT0_EN INT_STATUS[0] Enable,Enables the Channel Rx Threshold Interrupt. This
interrupt asserts when the CH-Rx FIFO is lower than the defined threshold.
FO
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1E002010 CHA0_FF_ST Channel A0(represents channel 0) FIFO status 0010000
US L
EO
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name CH CH
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
RSV0 OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
AU AU
m. NT
N N S N N S
LT LT
Type W1 W1 W1 W1 W1 W1 W1 W1
RO
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit(s) Name Description
31:24 RSV0 Reserved
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A0
ccn NF
Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel A0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel A0 Tx FIFO is underrun.
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO is lower
ase O
than the defined threshold.
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A0
Rx DMA signal.
@ KC
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel A0 Rx FIFO is overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel A0 Rx FIFO is underrun.
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO is lower
than the defined threshold.
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel A0 RXFIFO Available Space Count,Counts the available space for reads
xia E
in channel A0 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel A0 TXFIFO Available Space Count,Counts the available space for writes
ny AT
in channel A0 TXFIFO.(unit: word)
1E002014 CHB0_FF_ST Channel B0(represents channel 1) FIFO status 0010000
To DI
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH CH
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
R E
DM DM
RSV0 OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
M
LT LT
Type W1 W1 W1 W1 W1 W1 W1 W1
RO
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
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Bit(s) Name Description
US L
31:24 RSV0 Reserved
EO
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B0
cn IA
Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel B0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel B0 Tx FIFO is underrun.
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel B0 FIFO is lower
m. NT
than the defined threshold.
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B0
Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel B0 Rx FIFO is overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel B0 Rx FIFO is underrun.
.co IDE
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel B0 FIFO is lower
than the defined threshold.
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel B0 RXFIFO Available Space Count,Counts the available space for reads
in channel B0 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel B0 TXFIFO Available Space Count,Counts the available space for writes
ccn NF in channel B0 TXFIFO.(unit: word)
1E002020 CHA0_CFG Channel A0(represents channel 0) Config 0000000
ase O
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE
@ KC
RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
xia E
Bit(s) Name Description
31:30 RSV0 Reserved
ny AT
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
To DI
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
R E
compressed format)
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
16-bit format)
M
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
9:0 TS_START Timeslot starting location
(unit: clock cycles)
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E002024 CHB0_CFG Channel B0(represents channel 1) Config 0000000
cn IA
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
.co IDE
Bit(s) Name Description
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
ccn NF
011: Reserved
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
ase O
compressed format)
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
16-bit format)
@ KC
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
xia E
9:0 TS_START Timeslot starting location
(unit: clock cycles)
ny AT
1E002030 FSYNC_CFG FSYNC config 2800000
0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CF PO PO
PO PO
G_F S_C S_D
S_C S_D
SY AP_ RV_ RSV0 RSV1[11:6]
AP_ RV_
NC FSY FSY
R E
DT DT
_EN NC NC
Type RW RW RW RW RW RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] FSYNC_INTV
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 CFG_FSYNC_EN Enables configurable FSYNC.
30 POS_CAP_DT Positive Edge Capture Data, Sets the PCM controller to capture data on the
FO
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MT7621 PROGRAMMING GUIDE
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negative or positive edge of the PCM clock. NOTE: This configuration should be
0 if DTX_TRI=1.
US L
EO
29 POS_DRV_DT Positive Edge Drive Data, Sets the PCM controller to drive data on the negative or
positive edge of the PCM clock.
cn IA
28 POS_CAP_FSYNC Positive Edge Capture FSYNC, Sets the PCM controller to capture FSYNC on the
positive or negative edge of the PCM clock.
27 POS_DRV_FSYNC Positive Edge Driver FSYNC, Sets the PCM controller to drive FSYNC on the
negative or positive edge of the PCM clock.
m. NT
26:22 RSV0 Reserved
21:10 RSV1 Reserved
9:0 FSYNC_INTV Interval when FSYNC may be configured.
(unit: clock cycles)
.co IDE
1E002034 CHA0_CFG2 Channel A0(represents channel 0) Config 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
ccn NF
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH CH
_RX _TX CH
RS
ase O
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel A0 Rx FIFO Clear
0: Normal operation
xia E
1: Clear this bit
2 CH_TXFF_CLR Channel A0 Tx FIFO Clear
ny AT
0: Normal operation
1: Clear this bit
1 RSV1 Reserved
0 CH_LSB Enable CH A0 Tx in LSB order.
To DI
1E002038 CHB0_CFG2 Channel B0(represents channel 1) Config 0000000
0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
M
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH CH
_RX _TX CH
RS
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
Bit(s) Name Description
EO
31:4 RSV0 Reserved
cn IA
3 CH_RXFF_CLR Channel B0 Rx FIFO Clear
0: Normal operation
1: Clear this bit
2 CH_TXFF_CLR Channel B0 Tx FIFO Clear
m. NT
0: Normal operation
1: Clear this bit
1 RSV1 Reserved
0 CH_LSB Enable CH B0 Tx in LSB order.
.co IDE
1E002040 IP_INFO IP version info 0000040
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0
Type
ccn NF RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MAX_CH VER
Type RO RO
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
ase O
Bit(s) Name Description
@ KC
31:16 RSV0 Reserved
15:8 MAX_CH Maximum channel number.
7:0 VER Version of this PCM Controller
xia E
1E002044 RSV_REG16 SPARE REG 16 bits 0000000
0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPARE_REG
To DI
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
31:16 RSV0 Reserved
15:0 SPARE_REG Spare register for future use
M
1E002050 DIVCOMP_CF Dividor Compensation part config 0000000
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL
RSV0[22:8]
K_E
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
N
US L
Type RW RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name RSV0[7:0] DIVCOMP
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31 CLK_EN Clock Enable
Enables setting of the PCM interface clock based on DIVCOMP and DIVINT
parameters.
30:8 RSV0 Reserved
.co IDE
7:0 DIVCOMP A parameter in an equation which determines FREQOUT. See DIVINT.
1E002054 DIVINT_CFG Dividor Integer part config 0000000
0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[21:6]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name RSV0[5:0] DIVINT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:10 RSV0 Reserved
9:0 DIVINT A parameter in an equation which determines FREQOUT.
Formula:
FREQOUT = 1/(FREQIN*2*(DIVINT+DIVCOMP /(2^8)))
FREQIN is always fixed to 40 MHz.
xia E
ny AT
1E002060 DIGDELAY_C Digital delay config 0000000
FG 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX CH CH CH CH
To DI
TX
D_ EN_ EN EN EN
D_
CL CL N_ P_ RS PD_
RSV0 GL RSV1 RSV2
R_ R_ GL GL V3 GL
T_S
GL GL T_S T_S T_S
T
T T T T T
R E
Type RW RW RO RW RO RW RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX CH
D_ EN_
DIG DIG
RSV4 TXD_DLYVAL RSV5 CHEN_DLYVAL
DL DL
Y_E Y_E
N N
Type RW RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit(s) Name Description
US L
31 TXD_CLR_GLT TXD Clear Glitch Flag
EO
Clears the glitch detected flag for TXD.
0: No effect.
cn IA
1: Clear the flag.
30 CHEN_CLR_GLT Channel Enable (CHEN) Clear Glitch Flag
Clears the glitch detected flag for CHEN.
0: No effect .
m. NT
1: Clear the flag.
29:27 RSV0 Reserved
26 TXD_GLT_ST TXD Glitch Status
Indicates if a glitch is detected in a TXD signal. It can be cleared by bit[31].
0: Not detected.
.co IDE
1: Detected
25:23 RSV1 Reserved
22 CHENN_GLT_ST CHEN Negative Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30] (negedge
sample).
0: Not detected.
1: Detected
ccn NF
21:19 RSV2 Reserved
18 CHENP_GLT_ST CHEN Positive Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30] (posedge
sample).
0: Not detected.
ase O
1: Detected
17 RSV3 Reserved
@ KC
16 CHENPD_GLT_ST CHEN Positive Delay Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30] (posedge
sample, delay 1 cycle).
0: Not detected.
1: Detected
15 TXD_DIGDLY_EN TXD Digital Delay Enable
Enables digital delay path.
xia E
0: Disable
1: Enable
14:13 RSV4 Reserved
ny AT
12:8 TXD_DLYVAL Delay Count Value
The description is the same as the CHEN_DLYVAL field in this register.
CHEN Digital Delay Enable, Enables the digital delay path.
0: Disable
1: Enable
To DI
7 CHEN_DIGDLY_EN CHEN Digital Delay Enable
Enables the digital delay path.
0: Disable
1: Enable
R E
6:5 RSV5 Reserved
4:0 CHEN_DLYVAL Delay Count Value
M
The delay error =
CLK_PERIOD * (SYNC_DELAY + SYNC_DELTA + (DLYCNT_CFG) + 1)
For example,
DLYCNT_CFG = 4,
(SYNC_DELAY is always fixed to 4)
Final Delay
= CLK_PERIOD * (2 + (-1/0/+1) + (4) + 1)
= CLK_PERIOD * (6/7/8)= CLK_PERIOD * (6 to 8)
= 25 ns to 33.3 ns
NOTE:
FO
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MT7621 PROGRAMMING GUIDE
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NL
Period is 1/240 MHz = 4.1667 ns in MT7620.
US L
EO
cn IA
1E002080 CH0_FIFO Channel 0 FIFO access point 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH0_FIFO[31:16]
m. NT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH0_FIFO[15:0]
Type RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH0_FIFO Channel 0 FIFO access point
ccn NF
1E002084 CH1_FIFO Channel 1 FIFO access point 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH1_FIFO[31:16]
ase O
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name CH1_FIFO[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH1_FIFO Channel 1 FIFO access point
xia E
ny AT
1E002088 CH2_FIFO Channel 2 FIFO access point 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH2_FIFO[31:16]
Type RW
To DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH2_FIFO[15:0]
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 CH2_FIFO Channel 2 FIFO access point
1E00208C CH3_FIFO Channel 3 FIFO access point 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Name CH3_FIFO[31:16]
US L
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name CH3_FIFO[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:0 CH3_FIFO Channel 3 FIFO access point
.co IDE
1E002110 CHA0_FF_ST Channel A1(represents channel 3) FIFO status 0010000
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH
CH CH CH
CH
CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
RSV0 OV UN TH OV UN TH
A_F A_F
ccn NF RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
Type W1 W1 W1 W1 W1 W1 W1 W1
RO
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
@ KC
Bit(s) Name Description
31:24 RSV0 Reserved
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A1
Tx DMA signal.
xia E
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel A0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel A1 Tx FIFO is underrun.
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO is lower
ny AT
than the defined threshold.
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A1
Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel A1 Rx FIFO is overrun.
To DI
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel A1 Rx FIFO is underrun.
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel A1 FIFO is lower
than the defined threshold.
15:8 RSV1 Reserved
R E
7:4 CHRFF_AVCNT Channel A1 RXFIFO Available Space Count,Counts the available space for reads
in channel A1 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel A1 TXFIFO Available Space Count,Counts the available space for writes
M
in channel A1 TXFIFO.(unit: word)
1E002114 CHB1_FF_ST Channel B1(represents channel 4) FIFO status 0010000
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CH CH CH CH CH CH CH CH
FO
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MT7621 PROGRAMMING GUIDE
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NL
TX_ TX_ TX_ TX_ RX_ RX_ RX_ RX_
US L
DM OV UN TH DM OV UN TH
EO
A_F RU RU RE A_F RU RU RE
AU N N S AU N N S
cn IA
LT LT
Type RO
W1 W1 W1 W1 W1 W1 W1 W1
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit(s) Name Description
.co IDE
31:24 RSV0 Reserved
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B1
Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel B0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel B1 Tx FIFO is underrun.
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel B1 FIFO is lower
ccn NF than the defined threshold.
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B1
Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel B1 Rx FIFO is overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel B1 Rx FIFO is underrun.
ase O
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel B1 FIFO is lower
than the defined threshold.
@ KC
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel B1 RXFIFO Available Space Count,Counts the available space for reads
in channel B1 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel B1 TXFIFO Available Space Count,Counts the available space for writes
in channel B1 TXFIFO.(unit: word)
xia E
1E002120 CHA1_CFG Channel A1(represents channel 3) Config 0000000
ny AT
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R E
Bit(s) Name Description
31:30 RSV0 Reserved
M
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
FO
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MT7621 PROGRAMMING GUIDE
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110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
compressed format)
US L
EO
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
16-bit format)
0: DIS_CONV16
cn IA
2: DIS_CONV8
4: EN_ULW2R
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
m. NT
26:10 RSV1 Reserved
9:0 TS_START Timeslot starting location
(unit: clock cycles)
.co IDE
1E002124 CHB1_CFG Channel B1(represents channel 1) Config 0000000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
ccn NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ase O
Bit(s) Name Description
@ KC
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
xia E
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
ny AT
110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
compressed format)
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
16-bit format)
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
To DI
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
R E
9:0 TS_START Timeslot starting location
(unit: clock cycles)
M
1E002134 CHA1_CFG2 Channel A1(represents channel 3) Config 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
Type RO
FO
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MT7621 PROGRAMMING GUIDE
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Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name CH CH
_RX _TX CH
RS
cn IA
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel A1 Rx FIFO Clear
.co IDE
0: Normal operation
1: Clear this bit
2 CH_TXFF_CLR Channel A1 Tx FIFO Clear
0: Normal operation
1: Clear this bit
1 RSV1 Reserved
0 CH_LSB Enable CH A1 Tx in LSB order.
ccn NF
1E002138 CHB1_CFG2 Channel B1(represents channel 4) Config 0000000
0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
@ KC
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH CH
_RX _TX CH
RS
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
xia E
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel B1 Rx FIFO Clear
0: Normal operation
To DI
1: Clear this bit
2 CH_TXFF_CLR Channel B1 Tx FIFO Clear
0: Normal operation
1: Clear this bit
R E
1 RSV1 Reserved
0 CH_LSB Enable CH B1 Tx in LSB order.
FOM
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MT7621 PROGRAMMING GUIDE
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NL
US L
2.10.4 PCM Configuration
EO
PCM Initialization Flow
1. Set PCM_CFG
cn IA
2. Set CH0/1_CFG
3. Write PCM data to FIFO CH0/1_FIFO
4. Set GLB_CFG to enable the PCM and channel.
m. NT
5. Set dividor clock
6. Enable clock
7. Monitor FF_STATUS to receive/transmit the other PCM data.
PCM Configuration Examples
.co IDE
Below are some examples of PCM configuration.
Case 1:
CFG_FSYNC Register: CFG_FSYNC_EN = 0 (PS: fsync is always driven at SLOT_CNT=1)
CH0_CFG Register: TS_START=1
ccn NF
CH1_CFG Register: TS_START=9
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0
ase O
@ KC
xia E
Case 2:
ny AT
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0, interval=16
CH0_CFG Register: TS_START=1
CH1_CFG Register: TS_START=17
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0, RAW16-bits
To DI
R E
M
FO
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MT7621 PROGRAMMING GUIDE
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US L
EO
Case 3:
cn IA
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0x1A, interval=2
CH0_CFG Register: TS_START=1 (disable)
CH1_CFG Register: TS_START=0x1A
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b0 (LOW active), DRX_TRI=1’b0, SLOT_MODE=3’b0,
m. NT
RAW16-bits
.co IDE
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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MT7621 PROGRAMMING GUIDE
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US L
2.11 Generic DMA Controller
EO
2.11.1 Features
cn IA
Supports 16 DMA channels
Supports 32 bit address.
Maximum 65535 byte transfer
m. NT
Programmable DMA burst size (1, 2, 4, 8, 16 double word burst)
Supports memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
transfers.
Supports continuous mode.
Supports division of target transfer count into 1 to 256 segments
.co IDE
Support for combining different channels into a chain.
Programmable hardware channel priority.
Interrupts for each channel.
2.11.2 Block Diagram
ccn NF
Rbus Interface Rbus Interface
ase O
(Master) Rbus Rbus (Master)
Master Master
DMA Engine
@ KC
DMA
Interface
xia E
Arbiter
ny AT
Interrupt
Interface Ch0 APBbus
To DI
Interrupt Interface
Controller ABbus (Slave)
Mux
Slave
R E
Ch"n"
M
Figure 2-5 Generic DMA Controller Block Diagram
FO
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MT7621 PROGRAMMING GUIDE
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2.11.3 Peripheral Channel Connection
US L
EO
Channel number Peripheral
0 Reserved
cn IA
1 Reserved
2 I2S Controller (TXDMA)
3 I2S Controller (RXDMA)
m. NT
4 PCM Controller (RDMA, channel-0)
5 PCM Controller (RDMA, channel-1)
6 PCM Controller (TDMA, channel-0)
.co IDE
7 PCM Controller (TDMA, channel-1)
8 PCM Controller (RDMA, channel-2)
9 PCM Controller (RDMA, channel-3)
10 PCM Controller (TDMA, channel-2)
11 PCM Controller (TDMA, channel-3)
ccn NF
12 SPI Controller (RXDMA)
13 SPI Controller (TXDMA)
8 to 15 Reserved
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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US L
2.11.4 Registers
EO
GDMA Changes LOG
cn IA
Revision Date Author Change Log
0.1 2012/10/15 Mark Wang Initialization
m. NT
Module name: GDMA Base address: (+1E002800h)
Address Name Widt Register Function
h
.co IDE
1E002800 GDMA_SA_0 32 Source Address of GDMA Channel 0
1E002804 GDMA_DA_0 32 Destination Address of GDMA Channel 0
1E002808 GDMA_CT0_0 32 Control Register 0 of GDMA Channel 0
1E00280C GDMA_CT1_0 32 Control Register 1 of GDMA Channel 0
1E002810 GDMA_SA_1 32 Source Address of GDMA Channel 1
1E002814 GDMA_DA_1 32 Destination Address of GDMA Channel 1
ccn NF
1E002818 GDMA_CT0_1 32 Control Register 0 of GDMA Channel 1
1E00281C GDMA_CT1_1 32 Control Register 1 of GDMA Channel 1
1E002820 GDMA_SA_2 32 Source Address of GDMA Channel 2
1E002824 GDMA_DA_2 32 Destination Address of GDMA Channel 2
ase O
1E002828 GDMA_CT0_2 32 Control Register 0 of GDMA Channel 2
1E00282C GDMA_CT1_2 32 Control Register 1 of GDMA Channel 2
@ KC
1E002830 GDMA_SA_3 32 Source Address of GDMA Channel 3
1E002834 GDMA_DA_3 32 Destination Address of GDMA Channel 3
1E002838 GDMA_CT0_3 32 Control Register 0 of GDMA Channel 3
1E00283C GDMA_CT1_3 32 Control Register 1 of GDMA Channel 3
1E002840 GDMA_SA_4 32 Source Address of GDMA Channel 4
xia E
1E002844 GDMA_DA_4 32 Destination Address of GDMA Channel 4
1E002848 GDMA_CT0_4 32 Control Register 0 of GDMA Channel 4
ny AT
1E00284C GDMA_CT1_4 32 Control Register 1 of GDMA Channel 4
1E002850 GDMA_SA_5 32 Source Address of GDMA Channel 5
1E002854 GDMA_DA_5 32 Destination Address of GDMA Channel 5
1E002858 GDMA_CT0_5 32 Control Register 0 of GDMA Channel 5
To DI
1E00285C GDMA_CT1_5 32 Control Register 1 of GDMA Channel 5
1E002860 GDMA_SA_6 32 Source Address of GDMA Channel 6
1E002864 GDMA_DA_6 32 Destination Address of GDMA Channel 6
1E002868 32
R E
GDMA_CT0_6 Control Register 0 of GDMA Channel 6
1E00286C GDMA_CT1_6 32 Control Register 1 of GDMA Channel 6
32
M
1E002870 GDMA_SA_7 Source Address of GDMA Channel 7
1E002874 GDMA_DA_7 32 Destination Address of GDMA Channel 7
1E002878 GDMA_CT0_7 32 Control Register 0 of GDMA Channel 7
1E00287C GDMA_CT1_7 32 Control Register 1 of GDMA Channel 7
1E002880 GDMA_SA_8 32 Source Address of GDMA Channel 8
1E002884 GDMA_DA_8 32 Destination Address of GDMA Channel 8
1E002888 GDMA_CT0_8 32 Control Register 0 of GDMA Channel 8
FO
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MT7621 PROGRAMMING GUIDE
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1E00288C GDMA_CT1_8 32 Control Register 1 of GDMA Channel 8
US L
1E002890 GDMA_SA_9 32 Source Address of GDMA Channel 9
EO
1E002894 GDMA_DA_9 32 Destination Address of GDMA Channel 9
cn IA
1E002898 GDMA_CT0_9 32 Control Register 0 of GDMA Channel 9
1E00289C GDMA_CT1_9 32 Control Register 1 of GDMA Channel 9
1E0028A0 GDMA_SA_10 32 Source Address of GDMA Channel 10
m. NT
1E0028A4 GDMA_DA_10 32 Destination Address of GDMA Channel 10
1E0028A8 GDMA_CT0_10 32 Control Register 0 of GDMA Channel 10
1E0028AC GDMA_CT1_10 32 Control Register 1 of GDMA Channel 10
1E0028B0 GDMA_SA_11 32 Source Address of GDMA Channel 11
1E0028B4 GDMA_DA_11 32 Destination Address of GDMA Channel 11
.co IDE
1E0028B8 GDMA_CT0_11 32 Control Register 0 of GDMA Channel 11
1E0028BC GDMA_CT1_11 32 Control Register 1 of GDMA Channel 11
1E0028C0 GDMA_SA_12 32 Source Address of GDMA Channel 12
1E0028C4 GDMA_DA_12 32 Destination Address of GDMA Channel 12
1E0028C8 GDMA_CT0_12 32 Control Register 0 of GDMA Channel 12
ccn NF
1E0028CC GDMA_CT1_12 32 Control Register 1 of GDMA Channel 12
1E0028D0 GDMA_SA_13 32 Source Address of GDMA Channel 13
1E0028D4 GDMA_DA_13 32 Destination Address of GDMA Channel 13
1E0028D8 GDMA_CT0_13 32 Control Register 0 of GDMA Channel 13
ase O
1E0028DC GDMA_CT1_13 32 Control Register 1 of GDMA Channel 13
1E0028E0 GDMA_SA_14 32 Source Address of GDMA Channel 14
@ KC
1E0028E4 GDMA_DA_14 32 Destination Address of GDMA Channel 14
1E0028E8 GDMA_CT0_14 32 Control Register 0 of GDMA Channel 14
1E0028EC GDMA_CT1_14 32 Control Register 1 of GDMA Channel 14
1E0028F0 GDMA_SA_15 32 Source Address of GDMA Channel 15
1E0028F4 GDMA_DA_15 32 Destination Address of GDMA Channel 15
xia E
1E0028F8 GDMA_CT0_15 32 Control Register 0 of GDMA Channel 15
1E0028FC GDMA_CT1_15 32 Control Register 1 of GDMA Channel 15
ny AT
1E002A00 GDMA_UNMASK_I 32 Unmask Fail Interrupt Status
NTSTS
1E002A04 GDMA_DONE_INT 32 Segment Done Interrupt Status
STS
1E002A20 GDMA_GCT 32 Global Control
To DI
1E002A30 GDMA_PERI_ADD 32 Peripheral Region 0 Starting Address
R_START_0
1E002A34 GDMA_PERI_ADD 32 Peripheral Region 0 End Address
R_END_0
R E
1E002A38 GDMA_PERI_ADD 32 Peripheral Region 1 Starting Address
R_START_1
M
1E002A3C GDMA_PERI_ADD 32 Peripheral Region 1 End Address
R_END_1
1E002A40 GDMA_PERI_ADD 32 Peripheral Region 2 Starting Address
R_START_2
1E002A44 GDMA_PERI_ADD 32 Peripheral Region 2 End Address
R_END_2
1E002A48 GDMA_PERI_ADD 32 Peripheral Region 3 Starting Address
R_START_3
FO
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MT7621 PROGRAMMING GUIDE
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1E002A4C GDMA_PERI_ADD 32 Peripheral Region 3 End Address
US L
R_END_3
EO
cn IA
1E002800 GDMA_SA_0 Source Address of GDMA Channel 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
.co IDE
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR
ccn NF Souce address
1E002804 GDMA_DA_0 Destination Address of GDMA Channel 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:0 DEST_ADDR Destination address
ny AT
1E002808 GDMA_CT0_0 Control Register 0 of GDMA Channel 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
R E
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
M
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
FO
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MT7621 PROGRAMMING GUIDE
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15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
US L
7 SOURCE_ADDR_MO Sets the source address mode
EO
DE 0: Incremental mode
1: Fix mode
cn IA
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
m. NT
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
.co IDE
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1
ccn NF
CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
ase O
request is asserted.
0: Hardware mode
1: Software mode
@ KC
1E00280C GDMA_CT1_0 Control Register 1 of GDMA Channel 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
xia E
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
To DI
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
R E
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
FO
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32: The source of the transfer is memory (always ready)
US L
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
EO
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
cn IA
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
m. NT
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
.co IDE
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
ccn NF this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
ase O
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
@ KC
by HW/SW.
0: Channel is not masked
1: Channel is masked
1E002810 GDMA_SA_1 Source Address of GDMA Channel 1 0000000
xia E
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ny AT
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
To DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
31:0 SOURCE_ADDR Souce address
M
1E002814 GDMA_DA_1 Destination Address of GDMA Channel 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO
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MT7621 PROGRAMMING GUIDE
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Name DEST_ADDR[15:0]
US L
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31:0 DEST_ADDR Destination address
m. NT
1E002818 GDMA_CT0_1 Control Register 0 of GDMA Channel 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.co IDE
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
ccn NF CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
@ KC
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
xia E
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
ny AT
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
To DI
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
R E
0: Disable
1: Enable
M
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E00281C GDMA_CT1_1 Control Register 1 of GDMA Channel 1 0000000
cn IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
.co IDE
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
ase O
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
@ KC
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
xia E
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
ny AT
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
To DI
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
R E
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
M
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
by HW/SW.
US L
0: Channel is not masked
EO
1: Channel is masked
cn IA
1E002820 GDMA_SA_2 Source Address of GDMA Channel 2 0000000
0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ccn NF
1E002824 GDMA_DA_2 Destination Address of GDMA Channel 2 0000000
0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:0 DEST_ADDR Destination address
ny AT
1E002828 GDMA_CT0_2 Control Register 0 of GDMA Channel 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
M
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
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MT7621 PROGRAMMING GUIDE
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31:16 TARGET_BYTE_CNT The number of bytes to be transferred
US L
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
EO
7 SOURCE_ADDR_MO Sets the source address mode
cn IA
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
m. NT
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
.co IDE
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
ccn NF 1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
ase O
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
@ KC
0: Hardware mode
1: Software mode
1E00282C GDMA_CT1_2 Control Register 1 of GDMA Channel 2 0000000
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
ny AT
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
To DI
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
R E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
FO
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MT7621 PROGRAMMING GUIDE
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1: DMA_REQ1
2: DMA_REQ2
US L
EO
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
cn IA
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
m. NT
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
.co IDE
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2
ccn NF
COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
ase O
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
@ KC
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
xia E
1E002830 GDMA_SA_3 Source Address of GDMA Channel 3 0000000
0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
To DI
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
M
1E002834 GDMA_DA_3 Destination Address of GDMA Channel 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
FO
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MT7621 PROGRAMMING GUIDE
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Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name DEST_ADDR[15:0]
Type RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
m. NT
1E002838 GDMA_CT0_3 Control Register 0 of GDMA Channel 3 0000000
0
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ccn NF ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
ase O
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
xia E
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
ny AT
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
To DI
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
R E
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
M
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
FO
PGMT7621_V.1.0_130607 Page 166 of 349
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MT7621 PROGRAMMING GUIDE
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NL
0: Hardware mode
1: Software mode
US L
EO
cn IA
1E00283C GDMA_CT1_3 Control Register 1 of GDMA Channel 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
.co IDE
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO
ccn NF
RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
ase O
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
@ KC
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
xia E
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
ny AT
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
To DI
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
R E
0: Channel 0
1: Channel 1
n: Channel n
M
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
FO
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MT7621 PROGRAMMING GUIDE
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NL
1: Enable
US L
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
EO
by HW/SW.
0: Channel is not masked
cn IA
1: Channel is masked
m. NT
1E002840 GDMA_SA_4 Source Address of GDMA Channel 4 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
31:0 SOURCE_ADDR Souce address
ase O
1E002844 GDMA_DA_4 Destination Address of GDMA Channel 4 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
31:0 DEST_ADDR Destination address
1E002848 GDMA_CT0_4 Control Register 0 of GDMA Channel 4 0000000
To DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
M
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
Bit(s) Name Description
EO
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
cn IA
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
m. NT
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
.co IDE
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
ccn NF
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
ase O
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
@ KC
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
xia E
1E00284C GDMA_CT1_4 Control Register 1 of GDMA Channel 4 0000000
0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
To DI
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
R E
DE_ AIL
ED INT K
EN _IN
_EN
T_E
M
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
21:16 SOURCE_DMA_REQ Selects the source DMA request
US L
0: DMA_REQ0
EO
1: DMA_REQ1
2: DMA_REQ2
cn IA
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
m. NT
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
.co IDE
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
ccn NF 1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
ase O
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
@ KC
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
xia E
ny AT
1E002850 GDMA_SA_5 Source Address of GDMA Channel 5 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
To DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
M
31:0 SOURCE_ADDR Souce address
1E002854 GDMA_DA_5 Destination Address of GDMA Channel 5 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Name DEST_ADDR[31:16]
US L
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:0 DEST_ADDR Destination address
.co IDE
1E002858 GDMA_CT0_5 Control Register 0 of GDMA Channel 5 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
ase O
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
xia E
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
ny AT
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
To DI
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
R E
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
M
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
US L
EO
0: Hardware mode
1: Software mode
cn IA
1E00285C GDMA_CT1_5 Control Register 1 of GDMA Channel 5 0000000
m. NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
ccn NF T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
@ KC
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
xia E
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
ny AT
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
To DI
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
R E
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
M
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
FO
PGMT7621_V.1.0_130607 Page 172 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
US L
0: Disable
EO
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
cn IA
by HW/SW.
0: Channel is not masked
1: Channel is masked
m. NT
1E002860 GDMA_SA_6 Source Address of GDMA Channel 6 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.co IDE
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ase O
1E002864 GDMA_DA_6 Destination Address of GDMA Channel 6 0000000
@ KC
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
xia E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:0 DEST_ADDR Destination address
To DI
1E002868 GDMA_CT0_6 Control Register 0 of GDMA Channel 6 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
FO
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MT7621 PROGRAMMING GUIDE
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Type RO RW RW RW RW RW RW
Reset
US L
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
cn IA
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
m. NT
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
.co IDE
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
ccn NF
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
ase O
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
@ KC
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
xia E
ny AT
1E00286C GDMA_CT1_6 Control Register 1 of GDMA Channel 6 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
To DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
R E
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
M
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
US L
EO
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
cn IA
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
m. NT
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
.co IDE
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
ccn NF channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
ase O
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
@ KC
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
xia E
0: Channel is not masked
1: Channel is masked
ny AT
1E002870 GDMA_SA_7 Source Address of GDMA Channel 7 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
1E002874 GDMA_DA_7 Destination Address of GDMA Channel 7 0000000
FO
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MT7621 PROGRAMMING GUIDE
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NL
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name DEST_ADDR[31:16]
Type RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
.co IDE
1E002878 GDMA_CT0_7 Control Register 0 of GDMA Channel 7 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ST_ SW
ase O
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
@ KC
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
ny AT
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
To DI
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
R E
3: 8 DWs
4: 16 DWs
5: Undefined
M
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
1: Enable
US L
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
EO
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
cn IA
0: Hardware mode
1: Software mode
m. NT
1E00287C GDMA_CT1_7 Control Register 1 of GDMA Channel 7 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
.co IDE
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV
ccn NF NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset
ase O
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
xia E
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
ny AT
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
To DI
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
R E
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
M
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
1: Enable
US L
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
EO
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
cn IA
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
m. NT
1: Channel is masked
1E002880 GDMA_SA_8 Source Address of GDMA Channel 8 0000000
.co IDE
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ase O
@ KC
1E002884 GDMA_DA_8 Destination Address of GDMA Channel 8 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
ny AT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
To DI
1E002888 GDMA_CT0_8 Control Register 0 of GDMA Channel 8 0000000
R E
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO DE SE
SW
UR ST_ GM
_M
CE_ AD EN CH
CURR_SEGMENT BURST_SIZE OD
AD DR T_D _EN
E_E
DR _M ON
N
_M OD E_I
FO
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MT7621 PROGRAMMING GUIDE
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NL
OD E NT_
US L
E EN
EO
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
m. NT
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
.co IDE
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
ccn NF
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
ase O
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
@ KC
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
xia E
1: Software mode
ny AT
1E00288C GDMA_CT1_8 Control Register 1 of GDMA Channel 8 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
R E
_U
CO
CO NM
RE HE CH
NT_ AS
M
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
US L
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
EO
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
cn IA
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
m. NT
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
.co IDE
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
ccn NF CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
ase O
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
@ KC
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
xia E
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
ny AT
1: Channel is masked
1E002890 GDMA_SA_9 Source Address of GDMA Channel 9 0000000
To DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
M
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
FO
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MT7621 PROGRAMMING GUIDE
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1E002894 GDMA_DA_9 Destination Address of GDMA Channel 9 0000000
US L
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:0 DEST_ADDR Destination address
1E002898 GDMA_CT0_9 Control Register 0 of GDMA Channel 9 0000000
0
Bit 31
ccn NF
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ase O
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
@ KC
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
ny AT
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
To DI
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
R E
1: 2 DWs
2: 4 DWs
3: 8 DWs
M
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
FO
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MT7621 PROGRAMMING GUIDE
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bytes transfferred reaches the TARGET_BYTE_CNT
US L
0: Disable
EO
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
cn IA
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
m. NT
1E00289C GDMA_CT1_9 Control Register 1 of GDMA Channel 9 0000000
0
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
ccn NF
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
ase O
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
xia E
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
ny AT
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
To DI
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
R E
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
M
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
FO
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MT7621 PROGRAMMING GUIDE
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this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
US L
0: Disable
EO
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
cn IA
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
m. NT
by HW/SW.
0: Channel is not masked
1: Channel is masked
.co IDE
1E0028A0 GDMA_SA_10 Source Address of GDMA Channel 10 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
@ KC
1E0028A4 GDMA_DA_10 Destination Address of GDMA Channel 10 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
xia E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
31:0 DEST_ADDR Destination address
R E
1E0028A8 GDMA_CT0_1 Control Register 0 of GDMA Channel 10 0000000
0 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO DE SE SW
UR ST_ GM CH _M
CURR_SEGMENT BURST_SIZE
CE_ AD EN _EN OD
AD DR T_D E_E
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MT7621 PROGRAMMING GUIDE
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DR _M ON N
US L
_M OD E_I
EO
OD E NT_
E EN
cn IA
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
.co IDE
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
ccn NF
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
ase O
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
@ KC
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
xia E
request is asserted.
0: Hardware mode
1: Software mode
ny AT
1E0028AC GDMA_CT1_1 Control Register 1 of GDMA Channel 10 0000000
0 0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
M
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
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US L
Bit(s) Name Description
EO
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
cn IA
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
m. NT
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
.co IDE
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
ccn NF
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
ase O
0: Channel 0
1: Channel 1
n: Channel n
@ KC
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
xia E
0: Disable
1: Enable
ny AT
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
To DI
1E0028B0 GDMA_SA_11 Source Address of GDMA Channel 11 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name SOURCE_ADDR[31:16]
Type RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
FO
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MT7621 PROGRAMMING GUIDE
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US L
EO
1E0028B4 GDMA_DA_11 Destination Address of GDMA Channel 11 0000000
cn IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:0 DEST_ADDR Destination address
1E0028B8
ccn NF
GDMA_CT0_1 Control Register 0 of GDMA Channel 11 0000000
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
DE
@ KC
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
To DI
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
R E
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
M
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
FO
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MT7621 PROGRAMMING GUIDE
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1: Enable
US L
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
EO
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
cn IA
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
m. NT
0: Hardware mode
1: Software mode
1E0028BC GDMA_CT1_1 Control Register 1 of GDMA Channel 11 0000000
.co IDE
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ase O
ED INT K
EN _IN
_EN
T_E
N
@ KC
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
xia E
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
ny AT
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
To DI
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
R E
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
M
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
FO
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MT7621 PROGRAMMING GUIDE
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2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
US L
the last write to destination to avoid data coherent problem. Note: DO NOT set
EO
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
cn IA
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
m. NT
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
.co IDE
1E0028C0 GDMA_SA_12 Source Address of GDMA Channel 12 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
31:0 SOURCE_ADDR Souce address
1E0028C4 GDMA_DA_12 Destination Address of GDMA Channel 12 0000000
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
ny AT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:0 DEST_ADDR Destination address
R E
M
1E0028C8 GDMA_CT0_1 Control Register 0 of GDMA Channel 12 0000000
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO DE SE CH SW
CURR_SEGMENT BURST_SIZE
UR ST_ GM _EN _M
FO
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MT7621 PROGRAMMING GUIDE
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CE_ AD EN OD
US L
AD DR T_D E_E
EO
DR _M ON N
_M OD E_I
cn IA
OD E NT_
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
.co IDE
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
ccn NF
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
ase O
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
@ KC
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
xia E
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
ny AT
0: Hardware mode
1: Software mode
To DI
1E0028CC GDMA_CT1_1 Control Register 1 of GDMA Channel 12 0000000
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
R E
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
FO
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MT7621 PROGRAMMING GUIDE
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Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit(s) Name Description
cn IA
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
m. NT
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
.co IDE
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
ccn NF 2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
ase O
channel itself.
0: Channel 0
1: Channel 1
@ KC
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
xia E
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
ny AT
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
To DI
1E0028D0 GDMA_SA_13 Source Address of GDMA Channel 13 0000000
0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
M
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
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MT7621 PROGRAMMING GUIDE
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31:0 SOURCE_ADDR Souce address
US L
EO
cn IA
1E0028D4 GDMA_DA_13 Destination Address of GDMA Channel 13 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
ccn NF
1E0028D8 GDMA_CT0_1 Control Register 0 of GDMA Channel 13 0000000
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
ase O
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
xia E
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
To DI
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
R E
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
M
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
FO
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T_EN segment is done.
US L
0: Disable
EO
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
cn IA
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
m. NT
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
.co IDE
1E0028DC GDMA_CT1_1 Control Register 1 of GDMA Channel 13 0000000
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0
ccn NF0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
ase O
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
@ KC
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
xia E
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
ny AT
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
To DI
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
R E
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
M
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
FO
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MT7621 PROGRAMMING GUIDE
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1: Channel 1
n: Channel n
US L
EO
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
cn IA
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
m. NT
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
.co IDE
1: Channel is masked
1E0028E0 GDMA_SA_14 Source Address of GDMA Channel 14 0000000
0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
xia E
1E0028E4 GDMA_DA_14 Destination Address of GDMA Channel 14 0000000
0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
To DI
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
31:0 DEST_ADDR Destination address
M
1E0028E8 GDMA_CT0_1 Control Register 0 of GDMA Channel 14 0000000
4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name SO SE
DE
EO
UR GM
ST_ SW
CE_ EN
AD _M
cn IA
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
m. NT
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
.co IDE
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
ccn NF 1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
ase O
4: 16 DWs
5: Undefined
6: Undefined
@ KC
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
xia E
0: Disable
1: Enable
ny AT
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
To DI
1E0028EC GDMA_CT1_1 Control Register 1 of GDMA Channel 14 0000000
4 0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
M
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CO
CH
CO _U
RE HE CH
NT_ NM
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK AS
RV NT_ AS
DE_ K_F
ED INT K
EN AIL
_EN
_IN
FO
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MT7621 PROGRAMMING GUIDE
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T_E
US L
N
EO
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
m. NT
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
.co IDE
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8
ccn NF
DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
ase O
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
@ KC
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
xia E
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
ny AT
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
To DI
0: Channel is not masked
1: Channel is masked
R E
1E0028F0 GDMA_SA_15 Source Address of GDMA Channel 15 0000000
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
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US L
Bit(s) Name Description
EO
31:0 SOURCE_ADDR Souce address
cn IA
1E0028F4 GDMA_DA_15 Destination Address of GDMA Channel 15 0000000
m. NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
ccn NF
1E0028F8 GDMA_CT0_1 Control Register 0 of GDMA Channel 15 0000000
5 0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
@ KC
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
xia E
_M E_E
_M E_I
OD N
OD NT_
E
E EN
ny AT
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
To DI
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
R E
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
M
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
FO
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MT7621 PROGRAMMING GUIDE
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7: Undefined
US L
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
EO
T_EN segment is done.
0: Disable
cn IA
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
m. NT
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
.co IDE
1E0028FC GDMA_CT1_1 Control Register 1 of GDMA Channel 15 0000000
5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ccn NF
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
ase O
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
@ KC
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
ny AT
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
To DI
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
R E
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
M
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
FO
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MT7621 PROGRAMMING GUIDE
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channel itself.
US L
0: Channel 0
EO
1: Channel 1
n: Channel n
cn IA
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
m. NT
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
.co IDE
by HW/SW.
0: Channel is not masked
1: Channel is masked
1E002A00 GDMA_UNMA Unmask Fail Interrupt Status 0000000
ccn NF
SK_INTSTS 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name UNMASK_FAIL_INTSTS[31:16]
Type W1C
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name UNMASK_FAIL_INTSTS[15:0]
Type
@ KC
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 UNMASK_FAIL_INTST This field is the bit-map of unmask fail interrupt status of each channel. The
S unmask fail interrupt will assert when HW detect the CH_MASK field of
NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
xia E
ny AT
1E002A04 GDMA_DONE Segment Done Interrupt Status 0000000
_INTSTS 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEGMENT_DONE_INTSTS[31:16]
To DI
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEGMENT_DONE_INTSTS[15:0]
Type W1C
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 SEGMENT_DONE_IN This field is the bit-map of segment done interrupt status of each channel. The
TSTS segment done interrupt will assert when each segment is transferred completely.
1E002A20 GDMA_GCT Global Control 0000000
E
FO
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Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RESERVED[26:11]
EO
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AR
TOTAL_C B_
RESERVED[10:0] IP_VER
H_NUM MO
DE
m. NT
Type RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
Bit(s) Name Description
4:3 TOTAL_CH_NUM Total channel number supported
.co IDE
0: 8 channels
1: 16 channels
2: 32 channels
3: Undefined
2:1 IP_VER GDMA core version
0 ARB_MODE Arbitration mode selection
ccn NF 0: channel 0 has highest priority and others are round-robin
1: All channel are round-robin
ase O
1E002A30 GDMA_PERI_ Peripheral Region 0 Starting Address 1C00000
ADDR_START 0
_0
@ KC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_0[31:16]
Type RW
Reset 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_0[15:0]
Type RW
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
0 PERI_ADDR_START_x & < PERI_ADDR_END_x
To DI
1E002A34 GDMA_PERI_ Peripheral Region 0 End Address 2000000
ADDR_END_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name PERI_ADDR_END_0[31:16]
Type RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_END_0 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
FO
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MT7621 PROGRAMMING GUIDE
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US L
EO
1E002A38 GDMA_PERI_ Peripheral Region 1 Starting Address 1C00000
cn IA
ADDR_START 0
_1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_1[31:16]
m. NT
Type RW
Reset 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_1[15:0]
Type RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
1 ccn NF PERI_ADDR_START_x & < PERI_ADDR_END_x
1E002A3C GDMA_PERI_ Peripheral Region 1 End Address 2000000
ADDR_END_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name PERI_ADDR_END_1[31:16]
Type RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:0 PERI_ADDR_END_1 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
ny AT
1E002A40 GDMA_PERI_ Peripheral Region 2 Starting Address 6000000
ADDR_START 0
_2
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_2[31:16]
Type RW
Reset 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_2[15:0]
Type RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
2 PERI_ADDR_START_x & < PERI_ADDR_END_x
FO
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1E002A44 GDMA_PERI_ Peripheral Region 2 End Address 7000000
US L
EO
ADDR_END_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name PERI_ADDR_END_2[31:16]
Type RW
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name PERI_ADDR_END_2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:0 PERI_ADDR_END_2 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
1E002A48 GDMA_PERI_ Peripheral Region 3 Starting Address 6000000
ADDR_START 0
ccn NF
_3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_3[31:16]
Type RW
Reset
ase O
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_3[15:0]
Type RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
3 PERI_ADDR_START_x & < PERI_ADDR_END_x
xia E
ny AT
1E002A4C GDMA_PERI_ Peripheral Region 3 End Address 7000000
ADDR_END_3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_END_3[31:16]
Type RW
To DI
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_3[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
M
31:0 PERI_ADDR_END_3 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
FO
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2.12 SPI Controller
EO
2.12.1 Features
cn IA
Supports up to 2 SPI master operations
Programmable clock polarity
Programmable interface clock rate
m. NT
Programmable bit ordering
Firmware-controlled SPI enable
Programmable payload (address + data) length
Supports 1/2/4 multi-IO SPI flash memory
Supports command/user mode operation
.co IDE
Supports SPI direct access
Extends the addressable range from 24 bits to 32 bits for memory size larger than 128 Mb.
2.12.2 Block Diagram
ccn NF
clock
reset TX_FIFO Clock
SPICLK
from System Generator
ase O
Controller
@ KC
CPU SO/SIO1
CPU Interface SERDES
from PalmBus Interface WP/SIO2
Controller
xia E
ny AT
GDMA RX_FIFO SPI Control
FSM
To DI
Figure 2-6 SPI Controller Block Diagram
R E
M
FO
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2.12.3 Registers
EO
SPI Changes LOG
cn IA
Revision Date Author Change Log
0.1 2012/8/29 Lancelot Initialization
0.2 2012/11/6 Lancelot 1. Remove 0x38 SW_RST 2. Add CS_POLAR at 0x38
m. NT
0.3 2012/11/23 Lancelot Fix default value
Module name: SPI Base address: (+1E000B00h)
.co IDE
Address Name Widt Register Function
h
1E000B00 SPI_TRANS 32 SPI transaction control/status register
1E000B04 SPI_OP_ADDR 32 SPI opcode/address register
1E000B08 SPI_DIDO_0 32 SPI DI/DO data #0 register
1E000B0C SPI_DIDO_1 32 SPI DI/DO data #1 register
ccn NF
1E000B10 SPI_DIDO_2 32 SPI DI/DO data #2 register
1E000B14 SPI_DIDO_3 32 SPI DI/DO data #3 register
1E000B18 SPI_DIDO_4 32 SPI DI/DO data #4 register
1E000B1C SPI_DIDO_5 32 SPI DI/DO data #5 register
ase O
1E000B20 SPI_DIDO_6 32 SPI DI/DO data #6 register
1E000B24 SPI_DIDO_7 32 SPI DI/DO data #7 register
@ KC
1E000B28 SPI_MASTER 32 SPI master mode register
1E000B2C SPI_MORE_BUF 32 SPI more buf control register
1E000B30 SPI_QUEUE_CTL 32 SPI flash queue control register
1E000B34 SPI_STATUS 32 SPI controller status register
1E000B38 SPI_CS_POLAR 32 SPI chip select polarity
xia E
1E000B3C SPI_SPACE 32 SPI flash space control register
ny AT
1E000B00 SPI_TRANS SPI transaction control/status register 0016000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name spi
_m
spi_addr_s ast
spi_addr_ext Reserved0 Reserved1
ize er_
bus
R E
y
Type RW RO RW RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spi
_m
ast
Reserved2 miso_byte_cnt mosi_byte_cnt
er_
star
t
Type RO WO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
FO
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Bit(s) Name Description
EO
31:24 spi_addr_ext SPI address extention
cn IA
Address extenstion for 32-bit SPI address size. Usually this field specifies the first byte
of the address phase to transmit to SPI device when more_buf_mode = 0 and
spi_addr_size = 3. And spi_addr[31:24], spi_addr[23:16], and spi_addr[15:0] are
respectively the second, third and fourth byte of the address phase
20:19 spi_addr_size SPI address size.
m. NT
0: reserved.
1: spi_addr[15:0] of SPI DI data register are valid (16-bit size).
2: spi_addr[23:0] of SPI DI data register are valid (24-bit size).
3: {spi_addr_ext[7:0], spi_addr[23:0]} of SPI DI data register are valid
(32-bit size)
Note: The spi_addr_size is valid only when more_buf_mode = 0.
.co IDE
16 spi_master_busy Transaction busy indication (Read-only). Writes to this bit are ignored.
0: No SPI transaction is ongoing. Software may start a new SPI transaction by writing
to the SPI transaction start bit within this register.
1: An SPI transaction presently is underway. Software must not try to start a new SPI
transaction. Software may not alter the value of any field of the SPI master control
registers.
8 spi_master_start SPI transaction start. Only writes to this field are meaningful, reads always return
ccn NF
0.
Writes:
0: No effect
1: Starts SPI transaction.
7:4 miso_byte_cnt SPI MISO (rx) byte count.
ase O
Determines the number of bytes received from the SPI device from the SPI
opcode/address register and the SPI DI/DO data #0 register. Values of 0 ~ 8 are valid,
other values are illegal.
@ KC
Note: The miso_byte_cnt is valid only when more_buf_mode = 0.
3:0 mosi_byte_cnt SPI MOSI (tx) byte count.
Determines the number of bytes transmitted from the SPI opcode/address register and
the SPI DI/DO data #0 register to the SPI device. Values of 1 ~ 8 are valid, other values
are illegal.
Note: The mosi_byte_cnt is valid only when more_buf_mode = 0. The transmitted data
sequence is as follows: spi_opcode, spi_addr (conditional) and d0_byte ~ d3_byte
xia E
(conditional).
ny AT
1E000B04 SPI_OP_ADD SPI opcode/address register 0000000
R 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
To DI
spi_addr[23:8]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spi_addr[7:0] spi_opcode
R E
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:8 spi_addr SPI address. Usually this field specifies the 24-bits address to transmit to the SPI
device when more_buf_mode = 0.
1: (16-bits SPI address size), spi_addr[23:16] is the 1st byte of the address phase and
spi_addr[15:8] is the 2nd byte of the address phase.
2: (24-bits SPI address size), spi_addr[31:24] is the 1st byte of the address phase and
spi_addr[23:16] is the 2nd byte of the address phase and spi_addr[15:8] is the 3rd byte
of the address phase.
3: (32-bits SPI address size), spi_addr[31:24] is the 2nd byte of the address phase and
FO
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spi_addr[23:16] is the 3rd byte of the address phase and spi_addr[15:8] is the 4th byte
of the address phase
US L
EO
Note: For SPI read transaction and more_buf_mode = 0
Field [15:8] is also used to store the 6-th byte of data read phase.
Field [23:16] is also used to store the 7-th byte of data read phase.
cn IA
Field [31:24] is also used to store the 8-th byte of data read phase.
7:0 spi_opcode SPI opcode. Usually this field specifies the 8-bits opcode (instruction) to transmit
to the SPI device as the first byte of a SPI transaction when more_buf_mode = 0.
Note: For SPI read transaction and more_buf_mode = 0, this byte is also used to store
m. NT
the 5-th byte of data read phase according to the rx byte count miso_byte_cnt.
1E000B08 SPI_DIDO_0 SPI DI/DO data #0 register 0000000
.co IDE
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
ccn NF
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
@ KC
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B0C SPI_DIDO_1 SPI DI/DO data #1 register 0000000
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
ny AT
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
R E
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
M
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B10 SPI_DIDO_2 SPI DI/DO data #2 register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
FO
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Type RW RW
Reset
US L
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
cn IA
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
.co IDE
1E000B14 SPI_DIDO_3 SPI DI/DO data #3 register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
ccn NF
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
xia E
1E000B18 SPI_DIDO_4 SPI DI/DO data #4 register 0000000
ny AT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
M
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B1C SPI_DIDO_5 SPI DI/DO data #5 register 0000000
FO
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0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name d3_byte d2_byte
Type RW RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
.co IDE
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B20 SPI_DIDO_6 SPI DI/DO data #6 register 0000000
ccn NF
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset
ase O
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
xia E
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
ny AT
1E000B24 SPI_DIDO_7 SPI DI/DO data #7 register 0000000
0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name d1_byte d0_byte
Type RW RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
FO
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EO
1E000B28 SPI_MASTER SPI master mode register 000D888
cn IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name clk_
rs_slave_sel mo rs_clk_sel
m. NT
de
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name full spi spi
mor
bidi lsb e_b
.co IDE
_du int_ _st _pr cph cpo serial_mod
cs_dsel_cnt r_m _fir uf_
ple en art_ efet a l e
ode st mo
x sel ch
de
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
31:29 rs_slave_sel select SPI device
0: select SPI device 0 (default is flash)
1: select SPI device 1
...
7: select SPI device 7
ase O
28 clk_mode This register is used to specify that period of SCLK HIGH is longer or period of
SCLK LOW is longer when clock divisor(clk_sel) is odd.
0: period of SCLK LOW is longer.
@ KC
1: period of SCLL HIGH is longer.
27:16 rs_clk_sel Register Space SPI clock frequency select.
0: SPI clock frequency is hclk/2. (50% duty cycle, duty cycle is the ratio of the output
high time to the total cycle time)
1: SPI clock frequency is hclk/3. (33.33% or 66.67% duty cycle)
2: SPI clock frequency is hclk/4. (50% duty cycle)
3: SPI clock frequency is hclk/5. (40% or 60% duty cycle)
xia E
4095: SPI clock frequency is hclk/4097.
15:11 cs_dsel_cnt De-select time of SPI chip select is configured to occupy the number of cycles of
ny AT
AHB clock
10 full_duplex Full duplex or half duplex mode.
0: half duplex mode.
1: full duplex mode.
Full duplex timing diagram
Note: The full_duplex is valid only when more_buf_mode = 1. The transmission is
To DI
always as half duplex when more_buf_mode = 0;
9 int_en Interrupt enable.
0: disable SPI interrupt.
1: enable SPI interrupt.
R E
8 spi_start_sel The interval between spi_cs_n and spi_sclk.
0: 3 clk
1: 6 clk
M
7 spi_prefetch SPI pre-fetch buffer enable
0: disable pre-fetch buffer.
1: enable pre-fetch buffer.
6 bidir_mode Bi-direction mode. In this mode, the SPI uses only one serial data pin for
interface with external devices. The MOSI pin becomes the serial data I/O pin for
the SPI transaction and MISO pin is not used. Bi-direction mode is used for the
application with only 1 bi-direction serial pin for SPI transaction.
0: normal mode (both MOSI and MISO pins are used).
FO
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1: bi-direction mode (only MOSI pin is used). SPI host controller must operate in half
duplex mode if bidir_mode = 1.
US L
EO
Note: The bidir_mode is valid only when more_buf_mode = 1.
5 cpha (CPHA, clock phase). Initial SPI clock phase for SPI transaction.
cn IA
There are four SPI modes used to latch data. These SPI modes latch data in one of
four ways, and are defined by the logic state combinations of the CLK Polarity (CPOL)
in relation to the CLK Phase (CPHA). The valid logic combinations identify and
determine the SPI modes supported by the SPI device.
m. NT
SPI mode
At CPOL=0 the base value of the clock is zero
For CPHA=0 (mode 0), data is read on the clock's rising edge and data is changed on
a falling edge.
For CPHA=1 (mode 1), data is read on the clock's falling edge and data is changed on
.co IDE
a rising edge.
At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
For CPHA=0 (mode 2), data is read on clock's falling edge and data is changed on a
rising edge.
For CPHA=1 (mode 3), data is read on clock's rising edge and data is changed on a
falling edge.
4 cpol cpol (CPOL, clock polarity). Initial SPI clock polarity for SPI transaction.
3
ccn NF
lsb_first 0: MSB(most significant bit) is transferred first for SPI transaction.
1: LSB(least significant bit) is transferred first for SPI transaction.
2 more_buf_mode Select 2 words buffer or 8 words buffer for SPI transaction.
0: SPI transfer data buffer size is only 2 words. In this mode, SPI DI/DO data #0
register and SPI opcode/address register are the data buffer for SPI transaction. And,
ase O
SPI master follows mosi_byte_cnt and miso_byte_cnt to complete the transmission and
reception, respectively. This kind of transaction must operate in half duplex mode.
1: SPI transfer data buffer size is 8 words. In this mode, SPI opcode/address register
are the data buffer for SPI transaction and follows cmd_bit_cnt to complete the
@ KC
transaction. SPI DI/DO data #0~#7 register are the data buffer for SPI transaction and
follows do_bit_cnt and di_bit_cnt to complete the transmission and reception,
respectively. In half duplex mode, transmitted data are loaded from SPI
opcode/address register and SPI DI/DO data #0~#7 registers. And, the received data
will overwrite the SPI DI/DO data #0~#7 registers. In full duplex mode, SPI DI/DO data
#0~#3 registers are used for transmission and SPI DI/DO #4~#7 registers are used for
receipt.
xia E
1:0 serial_mode This mode is designed for Winbond SPI flash W25Q80/16/32 and
W25X10/20/40/80/16/32/64 series.
0: standard serial.
ny AT
1: dual serial.
2: quad serial.
3: reserved.
Note: The serial_mode is valid only when more_buf_mode = 0. The transaction mode is
always as standard serial when more_buf_mode = 1.
To DI
1E000B2C SPI_MORE_B SPI more buf control register 0000000
UF 0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved0 cmd_bit_cnt Reserved1 miso_bit_cnt[8:4]
M
Type RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name miso_bit_cnt[3:0] Reserved2 mosi_bit_cnt
Type RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
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29:24 cmd_bit_cnt SPI command phase MOSI (tx) bit count. Determines the number of command
US L
bits transmitted from the SPI opcode/address register to the SPI device. Values
EO
of 0 ~ 32 are valid, but other values are illegal.
Note: The cmd_bit_cnt is valid only when more_buf_mode = 1 and the SPI
cn IA
opcode/address register is treated as a command register.
20:12 miso_bit_cnt SPI data phase MISO (rx) bit count. Determines the number of bits received from
the SPI device into the SPI DI/DO data #0~#7 register. Values of 0 ~ 256 are valid,
but other values are illegal. Maximum value is 256 for half duplex mode and 128
for full duplex mode. Please note that do_bit_cnt must be equal to di_bit_cnt in
m. NT
full duplex mode.
Note: The miso_bit_cnt is valid only when more_buf_mode = 1.
8:0 mosi_bit_cnt SPI data phase MOSI (tx) bit count. Determines the number of data bits
transmitted from the SPI DI/DO data #0~#7 register to the SPI device. Values of 0
~ 256 are valid, but other values are illegal. Maximum value is 256 for half duplex
.co IDE
mode and 128 for full duplex mode.
Note: The mosi_bit_cnt is valid only when more_buf_mode = 1.
1E000B30 SPI_QUEUE_ SPI flash queue control register 00000A4
CTL 0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name fs_page_sel Reserved0[12:3]
Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name fs_ Res
fs_addr_si fs_addr_si
Reserved0[2:0] bus fs_di_ph_byc erv fast_spi_sel
ze_r ze
y ed1
@ KC
Type RO RO RO RW RW RO RW
Reset 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0
Bit(s) Name Description
31:26 fs_page_sel Flash Space Page Selection.
0: (Page 0 space) 0x0000_0000 - 0x03ff_ffff
xia E
1: (Page 1 space) 0x0400_0000 - 0x07ff_ffff
...
63: (Page 63 space) 0xffc0_0000 - 0xffff_ffff
ny AT
12 fs_busy Transaction busy indication (Read-only) in flash space. Writes to this bit are
ignored.
0: No SPI flash space access is ongoing. Software may change the configuration
related to flash space.
1: SPI flash space access presently is underway. Software may not alter the
configuration related to flash space.
To DI
11:10 fs_addr_size_r Latched fs_addr_size indication from internal spimc logic
9:8 fs_addr_size SPI address. This field specifies the 24-bits/16-bits address to transmit to the SPI
device for SPI Flash Space Read operation only.
0: 25-bit SPI address size
R E
1: 16-bit SPI address size Reserved.
2: 24-bit SPI address size (default for 3B SPI flash)
3: 26-bit SPI address size (default for 4B SPI flash)
M
If the change of the fs_addr_size is needed, the sequence below must be followed.
Otherwise, the new fs_addr_size configuration will not be updated to the internal spimc
logic .
Step 1: Set new fs_addr_size.
Step 2: Transmit mode change command (ex. En4B or Ex4B of
MX25L25635E)
Note: 1. The value fs_addr_size is not valid in Register Space.
2. The Spimc now only supports 3-Byte mode (24 bits) and 4-Byte
mode (25 or 26 bits) switch.
FO
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7:4 fs_di_ph_byc Determines the number of data bytes transmitted from the SPI master controller
US L
to the SPI device for SPI Flash Space Read operation. This field is similar to
EO
mosi_byte_cnt in STCSR but is used for setting of flash space access control
path.
cn IA
Note: this field should
(if fs_addr_size_r = 2, 24-bit fs_addr_size)
= 4 (OP + ADDR) if fast_spi_sel = 0 (0x03)
= 5 (OP + ADDR + dummy) if fast_spi_sel = 1 (0x0b)
= 5 (OP + ADDR + dummy) if fast_spi_sel = 2 (0x3b)
m. NT
= 5 (OP + ADDR + M7-0) if fast_spi_sel = 3 (0xbb)
= 5 (OP + ADDR + dummy) if fast_spi_sel = 4 (0x6b)
= 7 (OP + ADDR + M7-0 + dummy) if fast_spi_sel = 5 (0xeb)
= 5 (OP + ADDR + M7-0) if fast_spi_sel = 6 (0xe3)
(if fs_addr_size_r = 0 or 3, 25 or 26-bit fs_addr_size)
.co IDE
= 5 (OP + ADDR) if fast_spi_sel = 0 (0x03)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 1 (0x0b)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 2 (0x3b)
= 6 (OP + ADDR + M7-0) if fast_spi_sel = 3 (0xbb)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 4 (0x6b)
= 8 (OP + ADDR + M7-0 + dummy) if fast_spi_sel = 5 (0xeb)
= 6 (OP + ADDR + M7-0) if fast_spi_sel = 6 (0xe3)
2:0 fast_spi_sel Select SPI flash read instruction for Flash Space
ccn NF
0: standard read data instruction (0x03).
1: standard fast read data instruction (0x0b).
2: fast read dual output instruction defined in Winbond W25Qxx series SPI flash
(0x03b).
3: fast read dual I/O instruction defined in Winbond W25Qxx series SPI flash (0xbb).
4: fast read quad output instruction defined in Winbond W25Qxx series SPI flash
ase O
(0x6b).
5: fast read quad I/O instruction defined in Winbond W25Qxx series SPI flash (0xeb).
6: burst read quad I/O instruction defined in Winbond W25Qxx series SPI flash (0xe3).
@ KC
Note: serial_mode and more_buf_mode are don't care for this flash space access
control path.
1E000B34 SPI_STATUS SPI controller status register 0000003
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved0[25:10]
ny AT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spi_flash_ spi
Reserved0[9:0] Reserved1
mode _ok
Type RO RO RO RC
To DI
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Bit(s) Name Description
R E
5:4 spi_flash_mode 0: no SPI flash.
1: standard SPI flash.
2: specific SPI flash with dual interface capability.
M
3: specific SPI flash with quad interface capability.
0 spi_ok When SPI transaction complete, SPI master controller will set this bit and assert
SPI interrupt to notify software. Reading this register will clear this bit and de-
assert SPI interrupt.
1E000B38 SPI_CS_POL SPI chip select polarity 0000000
FO
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AR 0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name Reserved[23:8]
Type RO
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Reserved[7:0] cs_polar
Type RO RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
7:0 cs_polar Chip select default polarity
set cs_polar[n]=1'b0 for cs[n] low active (SPI Flash)
.co IDE
set cs_polar[n]=1'b1 for cs[n] high active
1E000B3C SPI_SPACE SPI flash space control register 0000003
0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved[16:1]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name Res
erv
fs_slave_sel fs_clk_sel
ed[
0:0]
@ KC
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Bit(s) Name Description
14:12 fs_slave_sel (Flash Space Slave Select)
0: select SPI device #0. (default is flash)
xia E
1: select SPI device #1.
...
7: select SPI device #7.
ny AT
11:0 fs_clk_sel Flash Space SPI clock frequency select.
0: SPI clock frequency is hclk/2. (50% duty cycle, duty cycle is the ratio of the output
high time to the total cycle time)
1: SPI clock frequency is hclk/3. (33.33% or 66.67% duty cycle)
2: SPI clock frequency is hclk/4. (50% duty cycle)
3: SPI clock frequency is hclk/5. (40% or 60% duty cycle)
To DI
4095: SPI clock frequency is hclk/4097.
R E
M
FO
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US L
2.13 I2S Controller
EO
2.13.1 Features
cn IA
I2S transmitter/receiver, which can be configured as master or slave.
Supports 16-bit data, sampling rates of 8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, and 48 kHz
Support stereo audio data transfer.
m. NT
32-byte FIFO are available for data transmission.
Supports GDMA access
Supports 12 Mhz bit clock from external source (when in slave mode)
2.13.2 Block Diagram
.co IDE
2
The I S transmitter block diagram is shown as below.
RBUS
CPU SDRAM
ccn NF
RBUS
I2S Design RBUS
ase O
CSR
Async interface
SD
Parallel-
@ KC
PBUS RBUS
WS to-serial FIFO GDMA
Control
converter PBUS
SCLK
xia E
2
Figure 2-7 I S Transmitter Block Diagram
ny AT
2
The I S interface consists of two separate cores, a transmitter and a receiver. Both can operate in either master
or slave mode. The transmitter is only shown here in master or slave mode.
To DI
2 2
I S Signal Timing For I S Data Format
R E
M
FO
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US L
EO
cn IA
m. NT
.co IDE
Figure 2-8 I2S Transmit/Receive
Serial data is transmitted in 2’s complement with the MSB first. The transmitter always sends the MSB of the
next word one clock period after the WS changes. Serial data sent by the transmitter may be synchronized
ccn NF
with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the
serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are
some restrictions when transmitting data that is synchronized with the leading edge.
The word select line indicates the channel being transmitted:
ase O
WS = 0; channel 1 (left)
WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be symmetrical. In
@ KC
the slave, this signal is latched on the leading edge of the clock signal. The WS line changes one clock period
before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data
that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear
the input for the next Word.
xia E
ny AT
To DI
R E
M
FO
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US L
2.13.3 Registers
EO
cn IA
Address Name Width Register Function
1E000A00 I2S_CFG 32 I2S Configuration
I2S Tx/Rx Configuration Register
m. NT
1E000A04 INT_STATUS 32 Interrupt Status
I2S Interrupt Status
1E000A08 INT_EN 32 Interrupt Enable
I2S Interrupt Enable Control Register
1E000A0C FF_STATUS 32 FIFO Status
.co IDE
I2S Tx/Rx FIFO Status
1E000A10 TX_FIFO_WREG 32 Transmit FIFO Write to Register
Tx Write Data Buffer
1E000A14 RX_FIFO_RREG 32 Receive FIFO Read Register
DRAM PAD CONTROL 3
1E000A18 I2S_CFG1 32 I2S Configuration 1
ccn NF
I2S Loopback Test Control Register
1E000A20 DIVCOMP_CFG 32 Integer Part of the Dividor Register 1
Integer Part of the Dividor Register
1E000A28 DIVINT_CFG 32 Integer Part of the Dividor Register 2
ase O
Integer Part of the Dividor Register
@ KC
1E000A00 I2S_CFG I2S Configuration 0001404
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SL
BY
DM AV
I2S TE_ TX_ RX_
xia E
A_E E_
_EN SW EN EN
N MO
AP
DE
ny AT
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_FF_THRES TX_FF_THRES
Type RW RW
Reset 1 0 0 1 0 0
To DI
Bit(s) Name Description
31 I2S_EN I2S Enable
Enables I2S. When disabled, all I2S control registers are cleared to their initial values.
R E
0: Disable
1: Enable
M
30 DMA_EN DMA Enable
Enables DMA access.
0: Disable
1: Enable
28 BYTE_SWAP Swaps the order of data bytes in each 16-bit channel.
0: No data swap
1: Data byte swap
24 TX_EN Transmitter on/off control
0: Disable
FO
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MT7621 PROGRAMMING GUIDE
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1: Enable
US L
20 RX_EN Receiver on/off control
EO
0: Disable
1: Enable
cn IA
16 SLAVE_MODE Sets master or slave mode.
0: Master: using internal clock
1: Slave: using external clock
14:12 RX_FF_THRES Rx FIFO Threshold
m. NT
When the threshold is reached, the host/DMA is notified to fill FIFO.
2<RX_FF_THRES<6
(unit: word)
6:4 TX_FF_THRES Tx FIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO.
.co IDE
2<TX_FF_THRES<6
(unit: word)
1E000A04 INT_STATUS Interrupt Status 0000000
0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name RX_
RX_ RX_ RX_
TX_
TX_ TX_ TX_
DM DM
OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
@ KC
AU AU
N N S N N S
LT LT
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7 RX_DMA_FAULT Rx DMA Fault Detected Interrupt
xia E
Asserts when a fault is detected in Rx DMA signals.
6 RX_OVRUN Rx Overrun Interrupt
ny AT
Asserts when the Rx FIFO is overrun.
5 RX_UNRUN Rx Underrun Interrupt
Asserts when the Rx FIFO is underrun.
4 RX_THRES Rx FIFO Below Threshold Interrupt
Asserts when the Rx FIFO is lower than the defined threshold.
To DI
3 TX_DMA_FAULT Tx DMA Fault Detected Interrupt
Asserts when a fault is detected in Tx DMA signals.
2 TX_OVRUN Tx FIFO Overrun Interrupt
R E
Asserts when the Tx FIFO is overrun.
1 TX_UNRUN Tx FIFO Underrun Interrupt
M
Asserts when the Tx FIFO is underrun.
0 TX_THRES Tx FIFO Below Threshold Interrupt
Asserts when the FIFO is lower than the defined threshold.
1E000A08 INT_EN Interrupt Enable 0000000
0
FO
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Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name
EO
Type
Reset
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_ RX_ RX_ RX_ TX_ TX_ TX_ TX_
INT INT INT INT INT INT INT INT
3_E 2_E 1_E 0_E 3_E 2_E 1_E 0_E
N N N N N N N N
m. NT
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7 RX_INT3_EN INT_STATUS[7] Enable
.co IDE
Enables the Rx DMA Fault Detected Interrupt. This interrupt asserts when a fault is
detected in Rx DMA signals.
6 RX_INT2_EN INT_STATUS[6] Enable
Enables the Rx Overrun Interrupt. This interrupt asserts when the Rx FIFO is overrun.
5 RX_INT1_EN INT_STATUS[5] Enable
Enables the Rx Underrun Interrupt. This interrupt asserts when the Rx FIFO is
ccn NF underrun.
4 RX_INT0_EN INT_STATUS[4] Enable
Enables the Rx FIFO Below Threshold Interrupt. This interrupt asserts when the Rx
FIFO is lower than the defined threshold.
3 TX_INT3_EN INT_STATUS[3] Enable
ase O
Enables the Tx DMA Fault Detected Interrupt. This interrupt asserts when a fault is
detected in Tx DMA signals.
2 TX_INT2_EN INT_STATUS[2] Enable
@ KC
Enables the Tx FIFO Overrun Interrupt. This interrupt asserts when the Tx FIFO is
overrun.
1 TX_INT1_EN INT_STATUS[1] Enable
Enables the Tx FIFO Underrun Interrupt. This interrupt asserts when the Tx FIFO is
underrun.
0 TX_INT0_EN INT_STATUS[0] Enable
xia E
Enables the Tx FIFO Below Threshold Interrupt. This interrupt asserts when the FIFO is
lower than the defined threshold.
ny AT
1E000A0C FF_STATUS FIFO Status 0000000
8
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name RX_AVCNT TX_EPCNT
Type RO RO
Reset 0 0 0 0 1 0 0 0
M
Bit(s) Name Description
7:4 RX_AVCNT Rx FIFO Available Space Count
Counts the available space for reads in Rx FIFO.
(unit: word)
3:0 TX_EPCNT Tx FIFO Available Space Count
Counts the available space for writes in Tx FIFO.
FO
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MT7621 PROGRAMMING GUIDE
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(unit: word)
US L
EO
cn IA
1E000A10 TX_FIFO_WR Transmit FIFO Write to Register 0000000
EG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_FIFO_WDATA[31:16]
m. NT
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_FIFO_WDATA[15:0]
Type WO
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 TX_FIFO_WDATA Tx FIFO Write Data Buffer
ccn NF Buffers data to be written to the Tx FIFO.
1E000A14 RX_FIFO_RR Receive FIFO Read Register 0000000
EG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name RX_FIFO_RDATA[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_FIFO_RDATA[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:0 RX_FIFO_RDATA Rx FIFO Read Data Buffer
Buffers data read from the Rx FIFO.
ny AT
1E000A18 I2S_CFG1 I2S Configuration 1 0000000
0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name EXT
LB
_LB
K_E
K_E
N
N
R E
Type RW RW
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name
Type
Reset
Bit(s) Name Description
31 LBK_EN Enables loopback mode.
0: Normal mode
1: Loopback mode
FO
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ASYNC_TXFIFIO -> Tx -> Rx -> ASYNC_RXFIFIO
US L
30 EXT_LBK_EN Enables external loopback.
EO
0: Normal mode
1: Enables external loop back.
cn IA
External A/D -> Rx -> Tx -> External D/A
m. NT
1E000A20 DIVCOMP_CF Integer Part of the Dividor Register 1 0000000
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL
K_E
.co IDE
N
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DIVCOMP
Type RW
Reset 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
31 CLK_EN Enables setting of the I2S clock based on DIVCOMP and DIVINT parameters.
0: Disable
1: Enable
ase O
8:0 DIVCOMP A parameter in an equation which determines FREQOUT. See DIVINT_CFG.
@ KC
1E000A28 DIVINT_CFG Integer Part of the Dividor Register 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
xia E
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ny AT
DIVINT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
9:0 DIVINT Integer Divider
A parameter in an equation which determines FREQOUT:
FREQOUT = FREQIN *(1/2) *
{1 / [DIVINT+DIVCOMP/(512)]}
FREQIN is always fixed to 40 MHz.
R E
M
FO
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2.14 SPDIF TX
EO
cn IA
m. NT
.co IDE
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
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2.14.1 Registers
US L
SPDIFTX Changes LOG
EO
cn IA
Revision Date Author Change Log
1.0 20120825 Jiechao Wei Initial Revision by RegisterMap_v1p4
1.1 20120919 Jiechao Wei Update for final RISC(PBUS) interface
1.2 20121009 Jiechao Wei Update default value
m. NT
1.3 20121216 Jiechao Wei Update for DRAM ping-pong structure
Module name: SPDIFTX Base address: (+1E000700h)
.co IDE
Address Name Widt Register Function
h
1E000700 IEC_CTRL 32 IEC CONTROL REGISTER
1E000704 IEC_BUF0_BS_SB 32 IEC BITSTREAM BUFFER START BLOCK
LK
1E000708
ccn NF
IEC_BUF0_BS_EB 32 IEC BITSTREAM BUFFER END BLOCK
LK
1E00070C IEC_BUF0_NSADR 32 IEC NEXT BURST START ADDRESS
1E000710 IEC_BUF0_NEXT_ 32 IEC USER DATA NEXT START ADDRESS
UADR
ase O
1E000714 IEC_BUF0_INTR_N 32 IEC INTERRUPT SIZE
SNUM
1E000718 IEC_BUF0_PCPD_ 32 IEC NEXT BURST LENGTH
@ KC
PACK
1E00071C IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION TRIGGER
G_TRIG
1E000720 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 0
G0
1E000724 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 1
xia E
G1
1E000728 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 2
G2
ny AT
1E00072C IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 3
G3
1E000730 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 4
G4
To DI
1E000734 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 5
G5
1E000738 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 6
G6
R E
1E00073C IEC_ACLK_DIV 32 IEC AUDIO MASTER CLOCK DIVIDER
1E000740 IEC_APLL_CFG0 32 IEC AUDIO PLL CONFIGURATION 0
M
1E000744 IEC_APLL_CFG1 32 IEC AUDIO PLL CONFIGURATION 1
1E000748 IEC_APLL_CFG2 32 IEC AUDIO PLL CONFIGURATION 2
1E00074C IEC_APLL_CFG3 32 IEC AUDIO PLL CONFIGURATION 3
1E000750 IEC_APLL_DEBUG 32 IEC AUDIO PLL DEBUG INFORMATION
1E000754 IEC_BUF1_BS_SB 32 IEC BITSTREAM BUFFER START BLOCK
LK
1E000758 IEC_BUF1_BS_EB 32 IEC BITSTREAM BUFFER END BLOCK
FO
PGMT7621_V.1.0_130607 Page 221 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
LK
US L
1E00075C IEC_BUF1_NSADR 32 IEC NEXT BURST START ADDRESS
EO
1E000760 IEC_BUF1_NEXT_ 32 IEC USER DATA NEXT START ADDRESS
UADR
cn IA
1E000764 IEC_BUF1_INTR_N 32 IEC INTERRUPT SIZE
SNUM
1E000768 IEC_BUF1_PCPD_ 32 IEC NEXT BURST LENGTH
PACK
m. NT
1E00076C IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION TRIGGER
G_TRIG
1E000770 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 0
G0
.co IDE
1E000774 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 1
G1
1E000778 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 2
G2
1E00077C IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 3
G3
1E000780 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 4
ccn NF
G4
1E000784 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 5
G5
1E000788 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 6
G6
ase O
@ KC
1E000700 IEC_CTRL IEC CONTROL REGISTER 0000008
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INT
RA R_E
W_ NA
xia E
EN BL
E
Type RW RW
ny AT
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name INT
DB
MU BY RA
MU
UD DA DA
DB UF_ RA TE_
R_S TE_ TE_ W_ AT TA_ TA_
UF_ DIS DOWN_SAMPLE W_ SA
TAT SP SW SW A_E FM SR
SEL AB 24 MP
To DI
US DF AP AP N T C
LE LE
Type W1
RO RW RW RW RW RW RW RW RW RW RW
C
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0
R E
Bit(s) Name Description
M
31 RAW_EN IEC958 raw data enable
0: disable
1: enable
16 INTR_ENABLE IEC958 interrupt enable
0: disable
1: enable
15 INTR_STATUS IEC958 interrupt status
0: No interrupt
1: Interrupting
FO
PGMT7621_V.1.0_130607 Page 222 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
12 DBUF_SEL IEC958 DRAM ping-pong buffer indicator
US L
0: buffer0 is going
EO
1: buffer1 is going
11 DBUF_DISABLE IEC958 DRAM ping-pong buffer disable
cn IA
0: enable
1: disable
10:8 DOWN_SAMPLE IEC958 down sample control
0: no down sample (recommended for MT7621)
m. NT
1: 2x down sample
3: 4x down sample
7 MUTE_SPDF mute IEC output SPDF signal
0: normal
1: mute output SPDF signal
.co IDE
6 BYTE_SWAP IEC dram word data bytes switch mode
5 RAW_SWAP IEC 24bit raw data bytes switch mode
4 RAW_24 IEC raw data 24bit mode
3 MUTE_SAMPLE mute IEC output sample data
0: normal
1: mute output sample data
ccn NF
2 UDATA_EN user data enable
0: all user data are zero
1: load user data from DRAM (IEC_NEXT_UADR)
1 DATA_FMT output data format selection
0: PCM data
ase O
1: encoded data
0 DATA_SRC data source selection
0: cooked data (from PCM receiver or transmitter output)
@ KC
1: raw data (from DRAM 61937 encoded audio data or 60958 plain PCM data)
1E000704 IEC_BUF0_BS IEC BITSTREAM BUFFER START BLOCK 0000000
_SBLK 0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BS_SBLK[27:16]
Type
ny AT
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BS_SBLK[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
27:0 BS_SBLK IEC958 bitstream buffer start block (double word size)
R E
M
1E000708 IEC_BUF0_BS IEC BITSTREAM BUFFER END BLOCK 0000000
_EBLK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BS_EBLK[27:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BS_EBLK[15:0]
Type RW
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit(s) Name Description
cn IA
27:0 BS_EBLK IEC958 bitstream buffer end block (double word size)
1E00070C IEC_BUF0_NS IEC NEXT BURST START ADDRESS 0000000
m. NT
ADR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NSADR[29:16]
Type RW
Reset
.co IDE
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NSADR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
29:0 NSADR next start address for next burst raw data (byte size)
1E000710 IEC_BUF0_NE IEC USER DATA NEXT START ADDRESS 0000000
ase O
XT_UADR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Name NUSADR[29:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NUSADR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
29:0 NUSADR next start address for next user data, LSB 2 bits are ignored and considered zero
(byte size)
1E000714 IEC_BUF0_IN IEC INTERRUPT SIZE 0000000
To DI
TR_NSNUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INTR_SIZE
R E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name NSNUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 INTR_SIZE generating interrupt when how many samples remain for this burst
12:0 NSNUM next sample number represented by next burst raw data
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E000718 IEC_BUF0_PC IEC NEXT BURST LENGTH 0000000
PD_PACK 0
cn IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NB_LEN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BURST_INFO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:16 NB_LEN number of bits for next burst(Pd package)
15:0 BURST_INFO burst information for IEC(Pc package)
1E00071C
ccn NF
IEC_BUF0_CH IEC CHANNEL CONFIGURATION TRIGGER 0000000
_CFG_TRIG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH
_CF
CH2_NUM
ase O
G_T
RIG
Type RW RW
Reset 0
@ KC
0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
xia E
31 CH_CFG_TRIG channel status update trigger, write 1'b1 to trigger and read busy state or not
23:20 CH2_NUM channel 2 (W) channel number
ny AT
1E000720 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 0 0000000
_CFG0 0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG0_ CLK_ACC
SAM_FREQ CH1_NUM SRC_NUM
RESERVE URACY
Type RW RW RW RW RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CO
M
CP_ DIG
NS
CATEGORY MODE ADD_INFO RIG ITA
UM
HT L
ER
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:30 CH_CFG0_RESERVE channel status reserve bits
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
29:28 CLK_ACCURACY clock accuracy
US L
27:24 SAM_FREQ sampling frequency
EO
23:20 CH1_NUM channel 1 (B & M) channel number
cn IA
19:16 SRC_NUM source number
15:8 CATEGORY category code
7:6 MODE channel status mode 0
5:3 ADD_INFO additional information
m. NT
2 CP_RIGHT copyright information
1 DIGITAL digital (bit 1 of channel status)
0: linear PCM samples
1: other purpose
.co IDE
0 CONSUMER bit 0 of channel status
0: consumer use of channel status block
1: professional use of channel status block
1E000724 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 1 0000000
ccn NF
_CFG1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG1_RESERVE[21:6]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG1_RESERVE[5:0] CGMS_A ORIGINAL_FS WORD_LEN
Type RW RW RW RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:10 CH_CFG1_RESERVE channel status reserve bits
9:8 CGMS_A CGMS-A information
7:4 ORIGINAL_FS original sample frequency
xia E
3:0 WORD_LEN word length
ny AT
1E000728 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 2 0000000
_CFG2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name CH_CFG2_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name CH_CFG2_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 CH_CFG2_RESERVE channel status reserve bits
1E00072C IEC_BUF0_CH IEC CHANNEL CONFIGURATION 3 0000000
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
_CFG3 0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name CH_CFG3_RESERVE[31:16]
Type RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG3_RESERVE[15:0]
Type RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH_CFG3_RESERVE channel status reserve bits
.co IDE
1E000730 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 4 0000000
_CFG4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG4_RESERVE[31:16]
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG4_RESERVE[15:0]
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
31:0 CH_CFG4_RESERVE channel status reserve bits
1E000734 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 5 0000000
_CFG5 0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG5_RESERVE[31:16]
ny AT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG5_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:0 CH_CFG5_RESERVE channel status reserve bits
R E
M
1E000738 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 6 0000000
_CFG6 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG6_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG6_RESERVE[15:0]
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW
Reset
US L
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
cn IA
31:0 CH_CFG6_RESERVE channel status reserve bits
m. NT
1E00073C IEC_ACLK_DI IEC AUDIO MASTER CLOCK DIVIDER 0018241
V F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MAS_DIV
Type
.co IDE
RW
Reset 0 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IEC_DIV BIT_DIV LRC_DIV
Type RW RW RW
Reset 0
ccn NF 1 0 0 1 0 0 1 1 1 1 1
Bit(s) Name Description
23:16 MAS_DIV audio master clock divider by audio pll (default 256xfs)
14:12 IEC_DIV audio iec958 clock divider by audio master clock (default 128xfs)
11:8 BIT_DIV audio bit clock divider by audio master clock (default 64xfs)
ase O
4:0 LRC_DIV audio lrck divider by audio bit clock (default 1xfs)
@ KC
1E000740 IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 0 0000000
G0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name APLL_CFG0[31:16]
Type RW
Reset
xia E
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_CFG0[15:0]
ny AT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 APLL_CFG0 audio pll configuration register 0 (Need MT7621 update)
To DI
1E000744 IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 1 0000000
R E
G1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name APLL_CFG1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_CFG1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
PGMT7621_V.1.0_130607 Page 228 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
31:0 APLL_CFG1 audio pll configuration register 1 (Need MT7621 update)
US L
EO
cn IA
1E000748 IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 2 0000000
G2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Name APLL_CFG2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_CFG2[15:0]
Type RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 APLL_CFG2 audio pll configuration register 2 (Need MT7621 update)
ccn NF
1E00074C IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 3 0000000
G3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name APLL_CFG3[31:16]
ase O
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name APLL_CFG3[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 APLL_CFG3 audio pll configuration register 3 (Need MT7621 update)
xia E
ny AT
1E000750 IEC_APLL_DE IEC AUDIO PLL DEBUG INFORMATION 0000000
BUG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
To DI
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_DEBUG
Type RO
R E
Reset 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
7:0 APLL_DEBUG audio pll debug information (Need MT7621 update)
1E000754 IEC_BUF1_BS IEC BITSTREAM BUFFER START BLOCK 0000000
_SBLK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO
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MT7621 PROGRAMMING GUIDE
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NL
Name BS_SBLK[28:16]
US L
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name BS_SBLK[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
28:0 BS_SBLK IEC958 bitstream buffer start block (double word size)
.co IDE
1E000758 IEC_BUF1_BS IEC BITSTREAM BUFFER END BLOCK 0000000
_EBLK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BS_EBLK[28:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name BS_EBLK[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
28:0 BS_EBLK IEC958 bitstream buffer end block (double word size)
@ KC
1E00075C IEC_BUF1_NS IEC NEXT BURST START ADDRESS 0000000
ADR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NSADR[30:16]
xia E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Name NSADR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
30:0 NSADR next start address for next burst raw data (byte size)
R E
1E000760 IEC_BUF1_NE IEC USER DATA NEXT START ADDRESS 0000000
XT_UADR 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NUSADR[30:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NUSADR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit(s) Name Description
US L
30:0 NUSADR next start address for next user data, LSB 2 bits are ignored and considered zero
EO
(byte size)
cn IA
1E000764 IEC_BUF1_IN IEC INTERRUPT SIZE 0000000
TR_NSNUM 0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INTR_SIZE
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name NSNUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 INTR_SIZE generating interrupt when how many samples remain for this burst
ccn NF
12:0 NSNUM next sample number represented by next burst raw data
1E000768 IEC_BUF1_PC IEC NEXT BURST LENGTH 0000000
ase O
PD_PACK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Name NB_LEN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BURST_INFO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
31:16 NB_LEN number of bits for next burst(Pd package)
15:0 BURST_INFO burst information for IEC(Pc package)
To DI
1E00076C IEC_BUF1_CH IEC CHANNEL CONFIGURATION TRIGGER 0000000
_CFG_TRIG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH
R E
_CF
CH2_NUM
G_T
RIG
M
Type RW RW
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
FO
PGMT7621_V.1.0_130607 Page 231 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
31 CH_CFG_TRIG channel status update trigger, write 1'b1 to trigger and read busy state or not
US L
23:20 CH2_NUM channel 2 (W) channel number
EO
cn IA
1E000770 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 0 0000000
_CFG0 0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG0_ CLK_ACC
SAM_FREQ CH1_NUM SRC_NUM
RESERVE URACY
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name CP_ DIG
CO
NS
CATEGORY MODE ADD_INFO RIG ITA
UM
HT L
ER
Type RW RW RW RW RW RW
Reset 0 0
ccn NF 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:30 CH_CFG0_RESERVE channel status reserve bits
29:28 CLK_ACCURACY clock accuracy
27:24 SAM_FREQ sampling frequency
ase O
23:20 CH1_NUM channel 1 (B & M) channel number
19:16 SRC_NUM source number
15:8 CATEGORY category code
@ KC
7:6 MODE channel status mode 0
5:3 ADD_INFO additional information
2 CP_RIGHT copyright information
1 DIGITAL digital (bit 1 of channel status)
0: linear PCM samples
xia E
1: other purpose
0 CONSUMER bit 0 of channel status
0: consumer use of channel status block
ny AT
1: professional use of channel status block
1E000774 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 1 0000000
To DI
_CFG1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG1_RESERVE[21:6]
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name CH_CFG1_RESERVE[5:0] CGMS_A ORIGINAL_FS WORD_LEN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:10 CH_CFG1_RESERVE channel status reserve bits
9:8 CGMS_A CGMS-A information
7:4 ORIGINAL_FS original sample frequency
FO
PGMT7621_V.1.0_130607 Page 232 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
3:0 WORD_LEN word length
US L
EO
cn IA
1E000778 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 2 0000000
_CFG2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Name CH_CFG2_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG2_RESERVE[15:0]
Type RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH_CFG2_RESERVE channel status reserve bits
ccn NF
1E00077C IEC_BUF1_CH IEC CHANNEL CONFIGURATION 3 0000000
_CFG3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG3_RESERVE[31:16]
ase O
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name CH_CFG3_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH_CFG3_RESERVE channel status reserve bits
xia E
ny AT
1E000780 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 4 0000000
_CFG4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG4_RESERVE[31:16]
To DI
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG4_RESERVE[15:0]
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 CH_CFG4_RESERVE channel status reserve bits
1E000784 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 5 0000000
_CFG5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO
PGMT7621_V.1.0_130607 Page 233 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Name CH_CFG5_RESERVE[31:16]
US L
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name CH_CFG5_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:0 CH_CFG5_RESERVE channel status reserve bits
.co IDE
1E000788 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 6 0000000
_CFG6 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG6_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name CH_CFG6_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
31:0 CH_CFG6_RESERVE channel status reserve bits
@ KC
xia E
ny AT
To DI
R E
M
FO
PGMT7621_V.1.0_130607 Page 234 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
2.15 Memory Controller
EO
2.15.1 Features
cn IA
1 SDRAM/DDR2 (16 b) chip selection
128 MB (SDRAM)/128 MB (DDR1)/256 MB (DDR2) per chip selection
SDRAM transaction overlapping by early active and hidden pre-charge
m. NT
User SDRAM Init commands
4 banks per SDRAM chip select
SDRAM burst length: 4 (fixed)
DDR2 burst length: 4/8 (programmable)
Wrap-4 transfer
.co IDE
Bank-Raw-Column and Raw-Bank-Column address mapping
ccn NF
ase O
@ KC
xia E
ny AT
To DI
R E
M
FO
PGMT7621_V.1.0_130607 Page 235 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
2.15.2 Registers
EO
cn IA
Address Name Widt Register Function
h
1E005000 ACTIM0 32 DRAM AC TIMING SETTING 0
DRAM AC TIMING SETTING 0
m. NT
1E005004 CONF1 32 DRAM CONFIGURATION 1
DRAM CONFIGURATION 1
1E005008 CONF2 32 DRAM CONFIGURATION 2
DRAM CONFIGURATION 2
.co IDE
1E00500C PADCTL1 32 DRAM PAD CONTROL 1
DRAM PAD CONTROL 1
1E005010 PADCTL2 32 DRAM PAD CONTROL 2
DRAM PAD CONTROL 2
1E005014 PADCTL3 32 DRAM PAD CONTROL 3
DRAM PAD CONTROL 3
ccn NF
1E005018 DELDLY1 32 DQS INPUT DELAY CHAIN SETTING 1
DQS INPUT DELAY CHAIN SETTING 1
1E005020 DIFDLY1 32 DQS INPUT DELAY CHAIN OFFSET SETTING 1
DQS INPUT DELAY CHAIN OFFSET SETTING 1
ase O
1E005028 DLLCONF 32 DLL CONFIGURATION
DLL CONFIGURATION
1E00502C TESTMODE 32 TEST MODE CONFIGURATION 1
@ KC
TEST MODE CONFIGURATION 1
1E00503C TEST2_1 32 TEST AGENT 2 CONFIGURATION 1
TEST AGENT 2 CONFIGURATION 1
1E005040 TEST2_2 32 TEST AGENT 2 CONFIGURATION 2
TEST AGENT 2 CONFIGURATION 2
1E005044 TEST2_3 32 TEST AGENT 2 CONFIGURATION 3
xia E
TEST AGENT 2 CONFIGURATION 3
1E005048 TEST2_4 32 TEST AGENT 2 CONFIGURATION 4
ny AT
TEST AGENT 2 CONFIGURATION 4
1E00507C DDR2CTL 32 DDR2 CONTROL REGISTER
DDR2 CONTROL REGISTER
1E005084 ZQCS 32 ZQCS setting
To DI
ZQCS setting
1E005088 MRS 32 MRS value setting
MRS value setting
1E00508C CLK1DELAY 32 Clock 1 output delay CONTROL
R E
Clock 1 output delay CONTROL
1E005090 IOCTL 32 IO CONTROL
M
IO misc control
1E005094 DQSIEN 32 DQS INPUT RANGE FINE TUNER
DQS INPUT RANGE FINE TUNER
1E0050B8 DRVCTL0 32 PAD DRIVING CONTROL SETTING 0
PAD DRIVING CONTROL SETTING 0
1E0050BC DRVCTL1 32 PAD DRIVING CONTROL SETTING 1
PAD DRIVING CONTROL SETTING 1
FO
PGMT7621_V.1.0_130607 Page 236 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E0050C0 DLLSEL 32 DLL SELECTION SETTING
US L
DLL SELECTION SETTING
EO
1E0050CC TDSEL0 32 IO OUTPUT DUTY CONTROL 0
cn IA
IO OUTPUT DUTY CONTROL 0
1E0050D0 TDSEL1 32 IO OUTPUT DUTY CONTROL 1
IO OUTPUT DUTY CONTROL 1
1E0050D8 MCKDLY 32 MEMORY CLOCK DELAY CHAIN SETTING
m. NT
MEMORY CLOCK DELAY CHAIN SETTING
1E0050DC DQSCTL0 32 DQS INPUT RANGE CONTROL 0
DQS INPUT RANGE CONTROL 0
1E0050E0 DQSCTL1 32 DQS INPUT RANGE CONTROL 1
DQS INPUT RANGE CONTROL 1
.co IDE
1E0050E4 PADCTL4 32 PAD CONTROL 1
PAD CONTROL 4
1E0050E8 PADCTL5 32 PAD CONTROL 2
PAD CONTROL 5
1E0050EC PADCTL6 32 PAD CONTROL 3
ccn NF PAD CONTROL 6
1E0050F0 PHYCTL1 32 DDR PHY CONTROL 1
DDR PHY CONTROL 1
1E0050F4 GDDR3CTL1 32 GDDR3 CONTROL 1
GDDR3 CONTROL 1
ase O
1E0050F8 PADCTL7 32 PAD CONTROL 4
PAD CONTROL 7
@ KC
1E0050FC MISCTL0 32 MISC CONTROL 0
MISC CONTROL 0
1E005100 OCDK 32 OCD CALIBRATION CONTROL
OCD CALIBRATION CONTROL
1E005104 LBWDAT0 32 LOOP BACK DATA 0
LOOP BACK DATA 0
xia E
1E005108 LBWDAT1 32 LOOP BACK DATA 1
LOOP BACK DATA 1
ny AT
1E00510C LBWDAT2 32 LOOP BACK DATA 2
LOOP BACK DATA 2
1E005110 RKCFG 32 RANK CONFIGURATION
RANK CONFIGURATION
1E005114 CKPHDET 32 CLOCK PHASE DETECTION SETTING
To DI
CLOCK PHASE DETECTION SETTING
1E005124 DQSGCTL 32 INPUT DQS GATING CONTROL
INPUT DQS GATING CONTROL
R E
1E005130 CLKENCTL 32 DRAM CLOCK ENABLE CONTROL
DRAM CLOCK ENABLE CONTROL
1E005140 DQSGCTL1 32 DQS gating delay control 1
M
DQS gating delay control 1
1E005144 DQSGCTL2 32 DQS gating delay control 2
DQS gating delay control 2
1E005168 ARBCTL0 32 ARBITRATION CONTROL 0
ARBITRATION CONTROL 0
1E0051A8 CMDDLY0 32 Command Delay CTL0
Command Delay CTL0
FO
PGMT7621_V.1.0_130607 Page 237 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E0051AC CMDDLY1 32 Command Delay CTL1
US L
Command Delay CTL1
EO
1E0051B0 CMDDLY2 32 Command Delay CTL2
cn IA
Command Delay CTL2
1E0051B4 CMDDLY3 32 Command Delay CTL3
Command Delay CTL3
1E0051B8 CMDDLY4 32 Command Delay CTL4
m. NT
Command Delay CTL4
1E0051BC CMDDLY5 32 Command Delay CTL5
Command Delay CTL5
1E0051C0 DQSCAL0 32 DQS CAL CONTROL 0
DQS CAL CONTROL 0
.co IDE
1E0051D8 DMMonitor 32 Monitor parameter
Monitor parameter
1E0051DC DRAMC_PD_CTRL 32 PD mode parameter
PD mode parameter
1E0051E0 LPDDR2 32 LPDDR2 setting
ccn NF LPDDR2 setting
1E0051E4 SPCMD 32 Special command mode
Special command mode
1E0051E8 ACTIM1 32 DRAM AC TIMING SETTING 1
DRAM AC TIMING SETTING 1
ase O
1E0051EC PERFCTL0 32 PERFORMANCE CONTROL 0
PERFORMANCE CONTROL 0
@ KC
1E0051F0 AC_DERATING 32 AC TIME DERATING CONTROL
AC TIME DERATING CONTROL
1E0051F4 RRRATE_CTL 32 REFRESH RATE CONTROL
REFRESH RATE CONTROL
1E0051F8 WPATCMP_DAT 32 WRITE PATTERN COMPARE SETTING
WRITE PATTERN COMPARE SETTING
xia E
1E0051FC WPATCMP_CTL 32 WRITE PATTERN COMPARE CONTROL
WRITE PATTERN COMPARE CONTROL
ny AT
1E005200 DQODLY1 32 DQ output DELAY1 CHAIN setting
DQ output DELAY1 CHAIN setting
1E005204 DQODLY2 32 DQ output DELAY2 CHAIN setting
DQ output DELAY2 CHAIN setting
1E005208 DQODLY3 32 DQ output DELAY3 CHAIN setting
To DI
DQ output DELAY3 CHAIN setting
1E00520C DQODLY4 32 DQ output DELAY4 CHAIN setting
DQ output DELAY4 CHAIN setting
R E
1E005210 DQIDLY1 32 DQ input DELAY1 CHAIN setting
DQ input DELAY1 CHAIN setting
1E005214 DQIDLY2 32 DQ input DELAY2 CHAIN setting
M
DQ input DELAY2 CHAIN setting
1E005218 DQIDLY3 32 DQ input DELAY3 CHAIN setting
DQ input DELAY3 CHAIN setting
1E00521C DQIDLY4 32 DQ input DELAY4 CHAIN setting
DQ input DELAY4 CHAIN setting
1E005220 DQIDLY5 32 DQ input DELAY5 CHAIN setting
DQ input DELAY5 CHAIN setting
FO
PGMT7621_V.1.0_130607 Page 238 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E005224 DQIDLY6 32 DQ input DELAY6 CHAIN setting
US L
DQ input DELAY6 CHAIN setting
EO
1E005228 DQIDLY7 32 DQ input DELAY7 CHAIN setting
cn IA
DQ input DELAY7 CHAIN setting
1E00522C DQIDLY8 32 DQ input DELAY8 CHAIN setting
DQ input DELAY8 CHAIN setting
1E005280 R2R_page_hit_cou 32 R2R_page_hit_counter
m. NT
nter R2R_page_hit_counter
1E005284 R2R_page_miss_c 32 R2R_page_miss_counter
ounter R2R_page_miss_counter
1E005288 R2R_interbank_co 32 R2R_interbank_counter
unter R2R_interbank_counter
.co IDE
1E00528C R2W_page_hit_co 32 R2W_page_hit_counter
unter R2W_page_hit_counter
1E005290 R2W_page_miss_ 32 R2W_page_miss_counter
counter R2W_page_miss_counter
1E005294 R2W_interbank_co 32 R2W_interbank_counter
unter
ccn NF R2W_interbank_counter
1E005298 W2R_page_hit_co 32 W2R_page_hit_counter
unter W2R_page_hit_counter
1E00529C W2R_page_miss_ 32 W2R_page_miss_counter
counter W2R_page_miss_counter
ase O
1E0052A0 W2R_interbank_co 32 W2R_interbank_counter
unter W2R_interbank_counter
@ KC
1E0052A4 W2W_page_hit_co 32 W2W_page_hit_counter
unter W2W_page_hit_counter
1E0052A8 W2W_page_miss_ 32 W2W_page_miss_counter
counter W2W_page_miss_counter
1E0052AC W2W_interbank_c 32 W2W_interbank_counter
ounter W2W_interbank_counter
xia E
1E0052B0 dramc_idle_count 32 dramc_idle_counter
er dramc_idle_counter
ny AT
1E0052B4 freerun_26m_coun 32 freerun_26m_counter
ter freerun_26m_counter
1E0052B8 refresh_pop_coun 32 refresh_pop_counter
ter refresh_pop_counter
1E0052BC JMETER_ST 32 Jitter Meter Status
To DI
1E0052C0 DQ_CAL_MAX_0 32 DQ INPUT CALIBRATION per bit 3-0
DQ INPUT CALIBRATION per bit 3-0
1E0052C4 DQ_CAL_MAX_1 32 DQ INPUT CALIBRATION per bit 7-4
R E
DQ INPUT CALIBRATION per bit 7-4
1E0052C8 DQ_CAL_MAX_2 32 DQ INPUT CALIBRATION per bit 11-8
DQ INPUT CALIBRATION per bit 11-8
M
1E0052CC DQ_CAL_MAX_3 32 DQ INPUT CALIBRATION per bit 15-12
DQ INPUT CALIBRATION per bit 15-12
1E0052D0 DQ_CAL_MAX_4 32 DQ INPUT CALIBRATION per bit 19-16
DQ INPUT CALIBRATION per bit 19-16
1E0052D4 DQ_CAL_MAX_5 32 DQ INPUT CALIBRATION per bit 23-20
DQ INPUT CALIBRATION per bit 23-20
1E0052D8 DQ_CAL_MAX_6 32 DQ INPUT CALIBRATION per bit 27-34
FO
PGMT7621_V.1.0_130607 Page 239 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
DQ INPUT CALIBRATION per bit 27-24
US L
1E0052DC DQ_CAL_MAX_7 32 DQ INPUT CALIBRATION per bit 31-28
EO
DQ INPUT CALIBRATION per bit 31-28
cn IA
1E0052E0 DQS_CAL_MIN_0 32 DQS INPUT CALIBRATION per bit 3-0
DQS INPUT CALIBRATION per bit 3-0
1E0052E4 DQS_CAL_MIN_1 32 DQS INPUT CALIBRATION per bit 7-4
DQS INPUT CALIBRATION per bit 7-4
m. NT
1E0052E8 DQS_CAL_MIN_2 32 DQS INPUT CALIBRATION per bit 11-8
DQS INPUT CALIBRATION per bit 11-8
1E0052EC DQS_CAL_MIN_3 32 DQS INPUT CALIBRATION per bit 15-12
DQS INPUT CALIBRATION per bit 15-12
1E0052F0 DQS_CAL_MIN_4 32 DQS INPUT CALIBRATION per bit 19-16
.co IDE
DQS INPUT CALIBRATION per bit 19-16
1E0052F4 DQS_CAL_MIN_5 32 DQS INPUT CALIBRATION per bit 23-20
DQS INPUT CALIBRATION per bit 23-20
1E0052F8 DQS_CAL_MIN_6 32 DQS INPUT CALIBRATION per bit 27-34
DQS INPUT CALIBRATION per bit 27-24
1E0052FC
ccn NF
DQS_CAL_MIN_7 32 DQS INPUT CALIBRATION per bit 31-28
DQS INPUT CALIBRATION per bit 31-28
1E005300 DQS_CAL_MAX_0 32 DQS INPUT CALIBRATION per bit 3-0
DQS INPUT CALIBRATION per bit 3-0
1E005304 DQS_CAL_MAX_1 32 DQS INPUT CALIBRATION per bit 7-4
ase O
DQS INPUT CALIBRATION per bit 7-4
1E005308 DQS_CAL_MAX_2 32 DQS INPUT CALIBRATION per bit 11-8
@ KC
DQS INPUT CALIBRATION per bit 11-8
1E00530C DQS_CAL_MAX_3 32 DQS INPUT CALIBRATION per bit 15-12
DQS INPUT CALIBRATION per bit 15-12
1E005310 DQS_CAL_MAX_4 32 DQS INPUT CALIBRATION per bit 19-16
DQS INPUT CALIBRATION per bit 19-16
1E005314 DQS_CAL_MAX_5 32 DQS INPUT CALIBRATION per bit 23-20
xia E
DQS INPUT CALIBRATION per bit 23-20
1E005318 DQS_CAL_MAX_6 32 DQS INPUT CALIBRATION per bit 27-34
ny AT
DQS INPUT CALIBRATION per bit 27-24
1E00531C DQS_CAL_MAX_7 32 DQS INPUT CALIBRATION per bit 31-28
DQS INPUT CALIBRATION per bit 31-28
1E005350 DQICAL0 32 DQS INPUT CALIBRATION 0
DQS INPUT CALIBRATION 0
To DI
1E005354 DQICAL1 32 DQS INPUT CALIBRATION 1
DQS INPUT CALIBRATION 1
1E005358 DQICAL2 32 DQS INPUT CALIBRATION 2
DQS INPUT CALIBRATION 2
R E
1E00535C DQICAL3 32 DQS INPUT CALIBRATION 3
DQS INPUT CALIBRATION 3
M
1E005370 CMP_ERR 32 CMP ERROR
CMP ERROR
1E005374 DQSIENDLY 32 DQS INPUT GATING DELAY VALUE
DQS INPUT GATING DELAY VALUE
1E00538C STBEN0 32 DQS RING COUNTER 0
DQS RING COUNTER 0
1E005390 STBEN1 32 DQS RING COUNTER 1
FO
PGMT7621_V.1.0_130607 Page 240 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
DQS RING COUNTER 1
US L
1E005394 STBEN2 32 DQS RING COUNTER 2
EO
DQS RING COUNTER 2
cn IA
1E005398 STBEN3 32 DQS RING COUNTER 3
DQS RING COUNTER 3
1E0053A0 DQSDLY0 32 DQS INPUT DELAY SETTING 0
DQS INPUT DELAY SETTING 0
m. NT
1E0053B8 SPCMDRESP 32 SPECIAL COMMAND RESPONSE
SPECIAL COMMAND RESPONSE
1E0053BC IORGCNT 32 IO RING COUNTER
IO RING COUNTER
1E0053C0 DQSGNWCNT0 32 DQS GATING WINODW COUNTER 0
.co IDE
DQS GATING WINODW COUNTER 0
1E0053C4 DQSGNWCNT1 32 DQS GATING WINODW COUNTER 1
DQS GATING WINODW COUNTER 1
1E0053C8 DQSGNWCNT2 32 DQS GATING WINODW COUNTER 2
DQS GATING WINODW COUNTER 2
1E0053CC
ccn NF
DQSGNWCNT3 32 DQS GATING WINODW COUNTER 3
DQS GATING WINODW COUNTER 3
1E0053D0 DQSGNWCNT4 32 DQS GATING WINODW COUNTER 4
DQS GATING WINODW COUNTER 4
1E0053D4 DQSGNWCNT5 32 DQS GATING WINODW COUNTER 5
ase O
DQS GATING WINODW COUNTER 5
1E0053D8 DQSSAMPLEV 32 DQS SAMPLE VALUE
@ KC
DQS SAMPLE VALUE
1E0053DC DLLCNT0 32 DLL STATUS 0
DLL STATUS 0
1E0053E8 CKPHCNT 32 CLOCK PHASE DETECTION RESULT
CLOCK PHASE DETECTION RESULT
1E0053FC TESTRPT 32 TEST AGENT STATUS
xia E
TEST AGENT STATUS
1E005600 MEMPLL0 32 MEMPLL REGISTER SETTING 0
ny AT
MEMPLL REGISTER SETTING 0
1E005604 MEMPLL1 32 MEMPLL REGISTER SETTING 1
MEMPLL REGISTER SETTING 1
1E005608 MEMPLL2 32 MEMPLL REGISTER SETTING 2
MEMPLL REGISTER SETTING 2
To DI
1E00560C MEMPLL3 32 MEMPLL REGISTER SETTING 3
MEMPLL REGISTER SETTING 3
1E005610 MEMPLL4 32 MEMPLL REGISTER SETTING 4
MEMPLL REGISTER SETTING 4
R E
1E005614 MEMPLL5 32 MEMPLL REGISTER SETTING 5
MEMPLL REGISTER SETTING 5
M
1E005618 MEMPLL6 32 MEMPLL REGISTER SETTING 6
MEMPLL REGISTER SETTING 6
1E00561C MEMPLL7 32 MEMPLL REGISTER SETTING 7
MEMPLL REGISTER SETTING 7
1E005620 MEMPLL8 32 MEMPLL REGISTER SETTING 8
MEMPLL REGISTER SETTING 8
1E005624 MEMPLL9 32 MEMPLL REGISTER SETTING 9
FO
PGMT7621_V.1.0_130607 Page 241 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
MEMPLL REGISTER SETTING 9
US L
1E005628 MEMPLL10 32 MEMPLL REGISTER SETTING 10
EO
MEMPLL REGISTER SETTING 10
cn IA
1E00562C MEMPLL11 32 MEMPLL REGISTER SETTING 11
MEMPLL REGISTER SETTING 11
1E005630 MEMPLL12 32 MEMPLL REGISTER SETTING 12
MEMPLL REGISTER SETTING 12
m. NT
1E005634 MEMPLL13 32 MEMPLL REGISTER SETTING 13
MEMPLL REGISTER SETTING 13
1E005638 MEMPLL14 32 MEMPLL REGISTER SETTING 14
MEMPLL REGISTER SETTING 14
1E005640 MEMPLL_DIVIDER 32 MEMPLL DIVIDER REGISTER CONTROL
.co IDE
MEMPLL DIVIDER REGISTER CONTROL
1E005644 VREF 32 VREF setting
VREF setting
ccn NF
1E005000 ACTIM0 DRAM AC TIMING SETTING 0 2256015
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TRCD TRP TFAW TWR
Type RW RW RW RW
ase O
Reset 0 0 1 0 0 0 1 0 0 1 0 1 0 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CL2
@ KC
BL2 CL3 CL2 TWTR TRC TRAS
5
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0
Bit(s) Name Description
31:28 TRCD tRCD Timing setting
xia E
tRCD = (1 + TRCD) DRAMC clock cycles
Note:
DRAMC clock = 2 * DRAM clock when FDIV2 (0x7c[0]) = 1
ny AT
DRAMC clock = 1 * DRAM clock when FDIV2 (0x7c[0]) = 0
27:24 TRP tRP Timing setting
tRP = (1 + TRP) DRAMC clock cycles
23:20 TFAW tFAW Timing setting
tFAW = (8 + TFAW) DRAMC clock cycles
To DI
Note: 0x1e8[1] is added for TFAW[4]
19:16 TWR tWR Timing setting
for LPDDR2/DDR3: write command to precharge command
TWR >= WL + tDQSS + (BL)/2 + tWR
R E
for LPDDR1: last data-in to precharge command
tWR = (1 + TWR) DRAMC clock cycles
15 BL2 When FDIV2 (0x7c[0]) = 1, 1 for burst length 4
M
When FDIV2 (0x7c[0]) = 0, set this to 0
14 CL3 CAS Latency = 3 (FPGA), reserved
13 CL25 CAS Latency = 2.5 (FPGA), reserved
12 CL2 CAS Latency Timing setting for DDR1
CAS Latency = 2
11:8 TWTR tWTR Timing setting
tWTR = (1 + TWTR) DRAMC clock cycles under LPDDR1
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
(WL + BL/2 + 1 + tWTR) = (3 + TWTR) DRAMC clock cycles under LPDDR2/DDR3
Note that TWTR value must be less or equal to 3 under LPDDR1,
US L
EO
and less or equal to 'ha under other memories
7:4 TRC tRC Timing setting
cn IA
tRC = (8 + TRC) DRAMC clock cycles
Note: 0x1e8[0] is added for TRC[4]
3:0 TRAS tRAS Timing setting
tRAS = (8 + TRAS) DRAMC clock cycles
m. NT
1E005004 CONF1 DRAM CONFIGURATION 1 0000000
0
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEL DY CL ST STR RD AU
TES
FR NC KDI TCMD RV_ V_E LO TOI
TLP
EF LK S FRZ N OP NIT
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name CK CM PA
DM
FW FR2 64B
EO DH BL4 MATYPE TRRD GDI
2R W ITE
N LD S
N
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
@ KC
27 TESTLP Infinite self test loop enabling for test agent 1
0: disable loop
1: enable loop
26 SELFREF Self-refresh mode enabling
0: disable
1: eanble self-refresh
25 DYNCLK
xia E
24 CLKDIS
22:20 TCMD Test command
ny AT
TCMD[2]: RAS_
TCMD[1]: CAS_
TCMD[0]: WE_
19 STRV_FRZ
18 STRV_EN
To DI
17 RDLOOP
16 AUTOINIT
15 CKEON CKE function enabling
R E
0: disable power down function, CKE will keep high
1: enable power down function, CKE will go down when idle
13 FW2R Fast write to read turnaround time (for DDR-I only)
M
0: turnaround time is 0T
1: turnaround time is 1T
12 FR2W
11 CMDHLD
10 BL4 When FDIV2 (0x7c[0]) = 0, 1 for DRAM burst length 4, 0 for burst length 8
When FDIV2 (0x7c[0]) = 1, 1 for DRAM burst length 8, 0 is reserved
When FDIV2 (0x7c[0]) = 1, set 0x00[15] = 1 for burst length 4
FO
PGMT7621_V.1.0_130607 Page 243 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
9:8 MATYPE DRAM column address width
US L
00: 8 bits
EO
01: 9 bits
10: 10 bits
cn IA
11: 11 bits
7:6 TRRD tRRD Timing setting
tRRD = (1 + TRRD) DRAMC clock cycles
Note: 0x1e8[3] is added for TRRD[2]
m. NT
3 PAGDIS Page mode disabling
0: disable page mode, every transaction is page-miss
1: enable page mode, page will keep opening after accessing
0 DM64BITEN DDR:
When FDIV2 (0x7c[0]) = 0, 1 for 64bit DRAM, 0 for 32bit DRAM
.co IDE
When FDIV2 (0x7c[0]) = 1, 1 for 32bit DRAM, 0 for 16bit DRAM
SDR:
0 for 64bit DRAM
1 for 128bit DRAM
1E005008 CONF2 DRAM CONFIGURATION 2
ccn NF 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TES
TES TES
T2 REFTHD
T2R T1
ase O
W
Type RW RW RW RW
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name REFCNT
Type RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 TEST2W Test Agent 2 write enabling
xia E
0: Disable write cycle
1: Enable write cycle
ny AT
30 TEST2R Test Agent 2 read enabling
0: Disable read cycle
1: Enable read cycle
29 TEST1 Test Agent 1 enabling
0: Disable test agent 1
To DI
1: Enable test agent 1
26:24 REFTHD Refresh threshold value for promoting refresh request to high-priority
0 means always high-priority
7:0 REFCNT Refresh period = (REFCNT * 16) DRAMC clock cycles
R E
Setting the value according to DRAM spec and DRAMC frequency
M
1E00500C PADCTL1 DRAM PAD CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CS1DLY CLK0DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO
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MT7621 PROGRAMMING GUIDE
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NL
Name
US L
Type
EO
Reset
cn IA
Bit(s) Name Description
31:28 CS1DLY CS1 signal output delay
The larger value means larger delay, 1 step = 20ps
m. NT
27:24 CLK0DLY DRAM clock 0 signal output delay
The larger value means larger delay, 1 step = 20ps
1E005010 PADCTL2 DRAM PAD CONTROL 2 0000000
.co IDE
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name DQM3DLY DQM2DLY DQM1DLY DQM0DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
15:12 DQM3DLY DRAM DQM[3] signal output delay
The larger value means larger delay, 1 step = 20ps
@ KC
11:8 DQM2DLY DRAM DQM[2] signal output delay
The larger value means larger delay, 1 step = 20ps
7:4 DQM1DLY DRAM DQM[1] signal output delay
The larger value means larger delay, 1 step = 20ps
3:0 DQM0DLY DRAM DQM[0] signal output delay
The larger value means larger delay, 1 step = 20ps
xia E
ny AT
1E005014 PADCTL3 DRAM PAD CONTROL 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
To DI
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3ODLY DQS2ODLY DQS1ODLY DQS0ODLY
Type RW RW RW RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
M
15:12 DQS3ODLY DRAM DQS3 signal output delay
The larger value means larger delay, 1 step = 20ps
11:8 DQS2ODLY DRAM DQS2 signal output delay
The larger value means larger delay, 1 step = 20ps
7:4 DQS1ODLY DRAM DQS1 signal output delay
The larger value means larger delay, 1 step = 20ps
3:0 DQS0ODLY DRAM DQS0 signal output delay
FO
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MT7621 PROGRAMMING GUIDE
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NL
The larger value means larger delay, 1 step = 20ps
US L
EO
cn IA
1E005018 DELDLY1 DQS INPUT DELAY CHAIN SETTING 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEL3DLY DEL2DLY
m. NT
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEL1DLY DEL0DLY
Type RW RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:24 DEL3DLY DQS3 input delay line setting
Total delay in typical case = (0.03 * DEL3DLY) ns
22:16 DEL2DLY DQS2 input delay line setting
ccn NF Total delay in typical case = (0.03 * DEL2DLY) ns
14:8 DEL1DLY DQS1 input delay line setting
Total delay in typical case = (0.03 * DEL1DLY) ns
6:0 DEL0DLY DQS0 input delay line setting
Total delay in typical case = (0.03 * DEL0DLY) ns
ase O
@ KC
1E005020 DIFDLY1 DQS INPUT DELAY CHAIN OFFSET SETTING 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DIF3DLY DIF2DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DIF1DLY DIF0DLY
Type
ny AT
RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:24 DIF3DLY Offset of DQS3 input delay line setting for auto mode
To DI
total delay in typical case = (0.03 * (DIF3DLY + DLLCNT)) ns, Binary-coded
22:16 DIF2DLY Offset of DQS2 input delay line setting for auto mode
total delay in typical case = (0.03 * (DIF2DLY + DLLCNT)) ns, Binary-coded
14:8 DIF1DLY Offset of DQS1 input delay line setting for auto mode
R E
total delay in typical case = (0.03 * (DIF1DLY + DLLCNT)) ns, Binary-coded
6:0 DIF0DLY Offset of DQS0 input delay line setting for auto mode
M
total delay in typical case = (0.03 * (DIF0DLY + DLLCNT)) ns, Binary-coded
1E005028 DLLCONF DLL CONFIGURATION 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DLL MD WC
FO
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MT7621 PROGRAMMING GUIDE
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NL
FRZ QS KS
US L
EL2
EO
Type RW RW RW
Reset 0 0 0
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
m. NT
Bit(s) Name Description
30 DLLFRZ Auto-calibration value update when refresh cycle
0: disable
1: enable
.co IDE
28 MDQS Manual mode for DQS input delay setting
0: auto setting DQS input delay by DLL
1: manual setting DQS input delay by register
21 WCKSEL2 Enable MIO_CK_DIV2 clocks input for MACRO_COM1 (data byte 2, 3)
0: disable
ccn NF 1: enable
1E00502C TESTMODE TEST MODE CONFIGURATION 1 5500000
0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TESTM_PAT0
Type RW
Reset 0 1 0 1 0 1 0 1
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
xia E
31:24 TESTM_PAT0 Test-pattern 0 for test mode
ny AT
1E00503C TEST2_1 TEST AGENT 2 CONFIGURATION 1 0120000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name TEST2_PAT0 TEST2_BASE_28to5[23:16]
Type RW RW
Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
R E
TEST2_BASE_28to5[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:24 TEST2_PAT0 Test-pattern 0 for test agent 2
23:0 TEST2_BASE_28to5 Test base address for test agent 2
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
1E005040 TEST2_2 TEST AGENT 2 CONFIGURATION 2 0001000
US L
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name TEST2_PAT1 TEST2_OFF_28to5[23:16]
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name TEST2_OFF_28to5[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:24 TEST2_PAT1 Test-pattern 1 for test agent 2
23:0 TEST2_OFF_28to5 Test offset address for test agent 2
1E005044 TEST2_3 TEST AGENT 2 CONFIGURATION 3 0800000
ccn NF 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name AD AD
AG
VP VR
DMPGTIM FZD TRFC
RE EFE
IV2
ase O
EN N
Type RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name DQ MA DQ TES DQ
MA DQ
PE SU NU DL TA PST SIC
NU SIC
RBI PD DQ YA DQSICALSTP UD WR AL TESTCNT
DLL AL
T MO SU UT PA 2 UP
FRZ EN
DE PD O T D
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
31 ADVPREEN Advanced precharge function enable
When page is idle for DMPGTIM cycles, the page is closed automatically
0: Disable advanced precharge function
1: Enable advanced precharge function
30 ADVREFEN Advanced refresh function enable
To DI
Used only for DDR3, DDR3 support refresh pull-in function, please refer DDR3 spec for
detail
0: Disable advnaced precharge function
1: Enable advanced precharge function
29:24 DMPGTIM Advanced precharge function timer, use with AVDPREEN
R E
unit: DRAMC clock
22 AGFZDIV2 Agent half frequency mode enable
M
19:16 TRFC tRFC Timing setting
tRFC = (11 + TRFC[7:0]) DRAMC clock cycles
Note: 0x1e8[7:4] is added for TRFC[7:4]
15 PERBIT Per Bit HW calibration
14 DQSUPDMODE 0: Original manual mode for DQS input delay
1: Update manual DQS input delay only while MANUDQSUPD=1 and DLLFRZ
13 MANUDQSUPD On-line manual DQS input delay adjust enabling
0: disable DQS input delay adjust
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
1: enable DQS input delay adjust, new value will be updated during refresh period
US L
12 MANUDLLFRZ Manual freeze DLL counter
EO
0: DLL counter will be updated by hardware
1: DLL counter will be freezed for software reading
cn IA
11 DQDLYAUTO DQ delay auto-update during calibration
0: No update
1: Update
10:8 DQSICALSTP HW calibration step (=DQSICALSTP*2)
m. NT
7 TESTAUDPAT Select audio pattern as test pattern of test agent2
0: ISI pattern
1: audio pattern
6 PSTWR2
.co IDE
5 DQSICALUPD Update DQS input delay setting to calibrated value
0: disable update
1: enable update
4 DQSICALEN HW calibration enable
0: disable HW calibration
1: enable HW calibration
3:0 TESTCNT Test loop number of test agent2
ccn NF
loop number = 2^(TESTCNT)
1E005048 TEST2_4 TEST AGENT 2 CONFIGURATION 4 0000110
ase O
D
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Name TZQCS
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TES TES TES
TA TA T2D
UD UD TESTAUDINIT ISS TESTAUDINC
MO BITI CR
xia E
DE NV AM
Type RW RW RW RW RW
Reset 0 0 1 0 0 0 1 0 0 1 1 0 1
ny AT
Bit(s) Name Description
31:24 TZQCS tZQCS Timing setting
tZQCS = (2 + TZQCS) DRAMC clock cycles
To DI
15 TESTAUDMODE Audio pattern: write after read enabling
0: read only
1: write after read
14 TESTAUDBITINV Audio pattern bit inversion enabling
R E
0: No bit inversion
1: Bit inversion
M
12:8 TESTAUDINIT Initial bit inverse position for audio pattern
5 TEST2DISSCRAM Test agent bypass scramble function
0: not bypass scramble function
1: bypass scramble function
4:0 TESTAUDINC Bit inverse incremental value for audio pattern
FO
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MT7621 PROGRAMMING GUIDE
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NL
1E00507C DDR2CTL DDR2 CONTROL REGISTER 0000000
US L
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name RO FIX
EO
DT WLAT RO RODT TWODT
DT
E DT
Type RW RW RW RW RW RW
Reset
m. NT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ER WO RO
DD
FDI
TR2W TRTP DATLAT R2E
OT EN EN V2
N
Type RW RW RW RW RW RW RW RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 RODTE Read ODT extend 1T mode enable
0: not extend 1T
1: extend 1T
Unit: DRAM clock cycle
ccn NF
30:28 WLAT Write latency = WLAT + 1/WAT + 3 when FDIV2 = 0/1
for example, write latency = 5T, set WLAT = 4/2 when FDIV2 = 0/1
Unit: DRAM clock cycle
27 FIXRODT Fix READ cycle ODT signal
ase O
Fix the ODT signal value (to control the PAD termination) as always enabled
0: Not fix on ODT
1: Fix on ODT
@ KC
26:24 RODT Read ODT timing control for DDR2
000: For CL3
001: For CL4 and CL5
010: for CL6 and CL7
23 EODT
22:16 TWODT Write ODT latency enabling for DDR2
111111: for all cases
xia E
others: Reserved
15:12 TR2W Read to write interval time = (TR2W[3:0] + 3) DRAMC clock cycles
ny AT
TR2W values are the same when >= 'h9
10:8 TRTP tRTP = (TRTP + 1) DRAMC clock cycle
In LPDDR, tRTP = BL/2. HW design guarantees, no need to set TRTP
In LPDDR2, tRTP begins (BL/2 - 2) clock cycles after the read command
In DDR3, precharge can be issued after AL + tRTP
To DI
7 EROT Read ODT timing control for DDR2
0: for CL3, CL5, CL7
1: for CL4, CL6
6:4 DATLAT Internal read data timing control
R E
The register and 0xE4[4] (DATLAT3)
4'b0101: CL6, CL7 for DDR2
4'b0100: CL4, CL5 for DDR2
M
4'b0111: CL9, CL10 for GDDR3
4'b1000: CL11, CL12 for GDDR3
3 WOEN Write ODT enabling
0: disable Write ODT
1: enable Write ODT
2 ROEN Read ODT enabling
0: disable Read ODT
1: enable Read ODT
FO
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MT7621 PROGRAMMING GUIDE
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1 DDR2EN DDR2 enabling
US L
0: disable DDR2 function
EO
1: enable DDR2 function
0 FDIV2 Half frequency mode
cn IA
0: DRAMC clock cycle = DRAM clock cycle
1: DRAMC clock cycle = 2 * DRAM clock cycle
m. NT
1E005084 ZQCS ZQCS setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
.co IDE
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ZQCSAD ZQCSOP
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
15:8 ZQCSAD
7:0 ZQCSOP
ase O
1E005088 MRS MRS value setting 0000000
@ KC
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OC
DA MRSOP
DJ
Type RW RW
Reset 0 0 0 0 0 0 0 0 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MRSBA MRSMA
ny AT
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 OCDADJ
To DI
23:16 MRSOP For LPDDR2 MRW's OP (MRS_OP[7:0])
15:13 MRSBA For non-LPDDR2 MRW bank address
12:0 MRSMA For MRR/MRW address
R E
M
1E00508C CLK1DELAY Clock 1 output delay CONTROL 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OCDPAT CLK1DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIF
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
OL
US L
EN1
EO
Type RW
Reset 0
cn IA
Bit(s) Name Description
31:24 OCDPAT
19:16 CLK1DLY DRAM clock 1 signal output delay
m. NT
The larger value means larger delay, 1 step = 20ps
1 FIFOLEN1 Read FIFO length in DDRPHY
0: 8-level
1: 4-level
.co IDE
1E005090 IOCTL IO CONTROL 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SIO
ccn NF
EN
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ase O
Type
Reset
@ KC
Bit(s) Name Description
31 SIOEN DQS singal output enable
0: Differentail output
1: Single-end output
xia E
1E005094 DQSIEN DQS INPUT RANGE FINE TUNER 0000000
0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3IEN DQS2IEN
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
To DI
Name DQS1IEN DQS0IEN
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
30:24 DQS3IEN DQS3 gating delay control
M
DRAMC uses the gated DQS to sample DQ.
To get the right gated DQS, the gating signal need to be adjust to match DRAM, PCB,
and others components. 1 step = 20ps.
22:16 DQS2IEN DQS2 gating delay control
14:8 DQS1IEN DQS1 gating delay control
6:0 DQS0IEN DQS0 gating delay control
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
1E0050B8 DRVCTL0 PAD DRIVING CONTROL SETTING 0 AA22AA
US L
EO
22
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name DQ DQ
SR SR
DQSDRVP DQSDRVN DSODTP DSODTN
TTB TTB
PJ NJ
Type RW RW RW RW RW RW
m. NT
Reset 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ
DQ
RTT
DQDRVP DQDRVN RTT DQODTP DQODTN
BN
BPJ
.co IDE
J
Type RW RW RW RW RW RW
Reset 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0
Bit(s) Name Description
31:28 DQSDRVP DQS P driving control, refer IBIST model for driving strength
27:24 DQSDRVN DQS N driving control, refer IBIST model for driving strength
ccn NF
23 DQSRTTBPJ DQS PAD RTTBPJ port control
22:20 DSODTP DQSODT P driving control, refer IBIST model for driving strength
19 DQSRTTBNJ DQS PAD RTTBNJ port control
18:16 DSODTN DQSODT N driving control, refer IBIST model for driving strength
ase O
15:12 DQDRVP DQ P driving control, refer IBIST model for driving strength
11:8 DQDRVN DQ N driving control, refer IBIST model for driving strength
@ KC
7 DQRTTBPJ DQ PAD RTTBPJ port control
6:4 DQODTP DQODT P driving control, refer IBIST model for driving strength
3 DQRTTBNJ DQ PAD RTTBNJ port control
2:0 DQODTN DQODT N driving control, refer IBIST model for driving strength
xia E
1E0050BC DRVCTL1 PAD DRIVING CONTROL SETTING 1 AA22AA
ny AT
00
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL CL
KR KR
CLKDRVP CLKDRVN CKODTP CKODTN
TTB TTB
PJ NJ
To DI
Type RW RW RW RW RW RW
Reset 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMDDRVP CMDDRVN
R E
Type RW RW
Reset 1 0 1 0 1 0 1 0
M
Bit(s) Name Description
31:28 CLKDRVP CLK P driving control, refer IBIST model for driving strength
27:24 CLKDRVN CLK N driving control, refer IBIST model for driving strength
23 CLKRTTBPJ CLK PAD RTTBPJ port control
22:20 CKODTP CLK ODT P driving control, refer IBIST model for driving strength
19 CLKRTTBNJ CLK PAD RTTBNJ port control
FO
PGMT7621_V.1.0_130607 Page 253 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
18:16 CKODTN CLK ODT N driving control, refer IBIST model for driving strength
US L
15:12 CMDDRVP CMD P driving control, refer IBIST model for driving strength
EO
11:8 CMDDRVN CMD N driving control, refer IBIST model for driving strength
cn IA
1E0050C0 DLLSEL DLL SELECTION SETTING 0000000
m. NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CM CM
CM CM
DLLCNTS AUTOKMO PD PD
DLL67SEL DLL45SEL DLL23SEL DLL01SEL PE PC
EL DE RV RV
N AL
NE PE
.co IDE
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CM
CM
OD
CMPDRVP CMPDRVN OD CMPODTP CMPODTN
TN
TPE
E
Type
ccn NF RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:30 DLL67SEL DLL6 and DLL7 counter selection
ase O
29:28 DLL45SEL DLL4 and DLL5 counter selection
27:26 DLL23SEL DLL2 and DLL3 counter selection
@ KC
25:24 DLL01SEL DLL0 and DLL1 counter selection
23:22 DLLCNTSEL DLL counter selection
Refer the previous bit fields for meaning
21:20 AUTOKMODE OCD/ODT calibration mode selection
00: disable auto calibration
01: DRVP mode
xia E
10: DRVN mode
11: ODTP mode
19 CMPEN Compensation counter enabling
ny AT
0: disable
1: enable
18 CMPCAL Connect to CMP pad CALP
17 CMPDRVNE Connect to CMP pad DRVNE
16 CMPDRVPE Connect to CMP pad DRVPE
To DI
15:12 CMPDRVP Connect to CMP pad DRVP[3:0]
11:8 CMPDRVN Connect to CMP pad DRVN[3:0]
7 CMODTPE CMP PAD ODTPE port
R E
6:4 CMPODTP CMP ODT P driving control
3 CMODTNE CMP PAD ODTNE port
M
2:0 CMPODTN CMP ODT N driving control
1E0050CC TDSEL0 IO OUTPUT DUTY CONTROL 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3TDSEL DQS2TDSEL
FO
PGMT7621_V.1.0_130607 Page 254 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW RW
Reset
US L
0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMDTDSEL CLKTDSEL
cn IA
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
27:24 DQS3TDSEL DQS3 output duty control
19:16 DQS2TDSEL DQS2 output duty control
11:8 CMDTDSEL Command output duty control
3:0 CLKTDSEL DRAM clock output duty control
.co IDE
1E0050D0 TDSEL1 IO OUTPUT DUTY CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1TDSEL DQS0TDSEL
ccn NF
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQB3TDSEL DQB2TDSEL DQB1TDSEL DQB0TDSEL
Type RW RW RW RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
27:24 DQS1TDSEL DQS1 output duty control
19:16 DQS0TDSEL DQS0 output duty control
15:12 DQB3TDSEL DQ byte3 output duty control
11:8 DQB2TDSEL DQ byte2 output duty control
7:4 DQB1TDSEL DQ byte1 output duty control
xia E
3:0 DQB0TDSEL DQ byte0 output duty control
ny AT
1E0050D8 MCKDLY MEMORY CLOCK DELAY CHAIN SETTING 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name _16
OD
BIT
PINMUX TR DISDQIEN
FUL
EN
L
Type RW RW RW RW
R E
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIXDQIEN
M
Type RW
Reset 0 0 0 0
Bit(s) Name Description
31:30 PINMUX PINMUX function
00: DDR3 (PCB4L)/LPDDR2-POP (PCB8L)
01: DDR3 (PCB6L)
10:LPDDR2 (PCB6L)
FO
PGMT7621_V.1.0_130607 Page 255 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
11: Reserve
US L
28 _16BITFULL DRAM bus is 16-bit and FDIV2 = 0
EO
22 ODTREN Write ODT turn on when reading
cn IA
0: disable
1: enable
19:16 DISDQIEN Disable DQ input enable
0: DQ input enable when necessary
1: DQ input disable
m. NT
15:12 FIXDQIEN DQ input enable fixed mode
0: DQ input enable when necessary
1: Keep DQ input always on
.co IDE
1E0050DC DQSCTL0 DQS INPUT RANGE CONTROL 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1CTL[11:4]
Type RW
Reset
ccn NF 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1CTL[3:0] DQS0CTL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
23:12 DQS1CTL DQS1 input range control, 1 hot encoding
@ KC
Unit: 1/2 DRAM clock cycle
11:0 DQS0CTL DQS0 input range control, 1 hot encoding
Unit: 1/2 DRAM clock cycle
xia E
1E0050E0 DQSCTL1 DQS INPUT RANGE CONTROL 1 0000000
0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ
SIE
NM DQSINCTL DQS3CTL[11:4]
OD
E
To DI
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3CTL[3:0] DQS2CTL
Type RW RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
28 DQSIENMODE DQS gating mode selection
0: pulse mode
1: burst mode
26:24 DQSINCTL DQS input range control by M_CK
0/1/ .../7 = delay 0/1/ .../7T
Unit: DRAMC clock cycle
23:12 DQS3CTL DQS3 input range control, 1hot encoding
FO
PGMT7621_V.1.0_130607 Page 256 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Unit: 1/2 DRAM clock cycle
US L
11:0 DQS2CTL DQS2 input range control, 1hot encoding
EO
Unit: 1/2 DRAM clock cycle
cn IA
1E0050E4 PADCTL4 PAD CONTROL 1 0000000
0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CLKPADCTL CMDPADCTL DQSPADCTL DQPADCTL
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name DD ZQ BC DA
CK CK GD
EFI EFI DR
DQSRTT DQRTT R3E CS 4OT TLA
XO XO 3RS
N EN F T3
FF N T
Type RW RW RW RW RW RW RW RW RW
Reset 0
ccn NF 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:28 CLKPADCTL Clock pad control
27:24 CMDPADCTL CMD pad control
23:20 DQSPADCTL DQS pad control
ase O
19:16 DQPADCTL DQ pad control
14:12 DQSRTT DQS termination control
10:8 DQRTT DQ termination control
@ KC
7 DDR3EN enable DDR3 mode
0: Not enable DDR3
1: Enable
6 ZQCSEN ZQCS enable (ZQ calibration short), for DDR3 only
0: disable
1: enable
xia E
5 BC4OTF Burst chop 4 on the fly mode
0: disable
ny AT
1: enable
4 DATLAT3 Read data latch timing control bit 3
3 CKEFIXOFF CKE always off
0: CKE hardware control
1: CKE always off
To DI
2 CKEFIXON CKE always on
0: CKE hardware control
1: CKE always on
1 GDDR3RST GDDR3/DDR3 reset pin enable
R E
0: reset disable
1: reset enable
M
1E0050E8 PADCTL5 PAD CONTROL 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3RDSEL DQS2RDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name DQS1RDSEL DQS0RDSEL
EO
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
29:24 DQS3RDSEL DQS 3 RDSEL (duty cycle control)
Unit: 50ps
m. NT
21:16 DQS2RDSEL DQS 2 RDSEL (duty cycle control)
Unit: 50ps
13:8 DQS1RDSEL DQS 1 RDSEL (duty cycle control)
Unit: 50ps
.co IDE
5:0 DQS0RDSEL DQS 0 RDSEL (duty cycle control)
Unit: 50ps
1E0050EC PADCTL6 PAD CONTROL 3 0000000
0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3RDSEL DQ2RDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name DQ1RDSEL DQ0RDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
29:24 DQ3RDSEL DQ Byte 3 RDSEL (duty cycle control)
Unit: 50ps
21:16 DQ2RDSEL DQ Byte 2 RDSEL (duty cycle control)
Unit: 50ps
xia E
13:8 DQ1RDSEL DQ Byte 1 RDSEL (duty cycle control)
Unit: 50ps
ny AT
5:0 DQ0RDSEL DQ Byte 0 RDSEL (duty cycle control)
Unit: 50ps
To DI
1E0050F0 PHYCTL1 DDR PHY CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name DQ
PH
FIX
4B DQ
YR
MU SIE
ST
M
X N
Type RW RW RW
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
31 DQ4BMUX DQ 4-bit multiplex for DDR3
US L
0: Disable
EO
1: Enable
28 PHYRST PHY reset enable
cn IA
0: disable
1: enable
24 FIXDQSIEN DQS input enable always on
0: Hardware control
m. NT
1: always on
1E0050F4 GDDR3CTL1 GDDR3 CONTROL 1 0000000
.co IDE
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PH RD
_8B
YS AT
KE
YN RS
N
CM T
Type RW RW RW
ccn NF
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
ase O
Bit(s) Name Description
28 PHYSYNCM SYNC MODE using inverted PHY_M_CK
@ KC
25 RDATRST Read data counter reset
0: disable
1: enable reset
24 _8BKEN 8-bank device enable
0: for 4-bank device
1: for 8-bank device
xia E
ny AT
1E0050F8 PADCTL7 PAD CONTROL 4 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
To DI
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DR
AM LBT
R E
OE EST
N
Type RW RW
M
Reset 0 0
Bit(s) Name Description
9 DRAMOEN DRAM pin output enable
0: disable, DRAM pin will be Hi-Z
1: enable
8 LBTEST Loop-back test mode enable
0: disable
FO
PGMT7621_V.1.0_130607 Page 259 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: enable
US L
EO
cn IA
1E0050FC MISCTL0 MISC CONTROL 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RE RE PB
m. NT
AS
FP_ FA_ C_ MO
YN INT
TXP AR AR AR DE1
CE LBT
B_E B_E B_E 8V
N
N N N
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
ccn NF
30:28 TXP tXP Timing setting
tXP = (2 + TXP) DRAMC clock cycles
26 REFP_ARB_EN Per-bank refresh blocks EMI arbitration
0: disable
1: enable
ase O
25 REFA_ARB_EN All-bank refresh blocks EMI arbitration
0: disable
1: enable
@ KC
24 PBC_ARB_EN Block page-miss requests in EMI arbitration
0: disable
1: enable
20 ASYNCEN Asynchronous mode enabling between DRAMC & DDRPHY
0: synchronous mode
1: asynchronous mode
xia E
17 INTLBT IO internal loop back
0: disable
1: enable
ny AT
16 MODE18V IO voltage operating condition
0: 1.2V
1: 1.8V
To DI
1E005100 OCDK OCD CALIBRATION CONTROL 0000000
0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WD WD WD WD WD WD WD WD
WD DR
AT AT AT AT AT AT AT AT INTREF_S
ATI VR
M
KE KE KE KE KE KE KE KE EL
TLV EF
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DR AU
DE TO
LS DRDELSWSEL CA AUTOKCNT
WE LD
N RV
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW RW RW RW
Reset
US L
0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
cn IA
31 WDATKEY7 Data encryption key bit 7
30 WDATKEY6 Data encryption key bit 6
28 WDATITLV Data scramble enable
m. NT
0: disable
1: enable
27 WDATKEY5 Data encryption key bit 5
26 WDATKEY4 Data encryption key bit 4
24 DRVREF Driving change only when refresh cycle
.co IDE
0: disable, change will be apply directly
1: enable, change will be apply during refresh
23 WDATKEY3 Data encryption key bit 3
22 WDATKEY2 Data encryption key bit 2
19 WDATKEY1 Data encryption key bit 1
18 WDATKEY0 Data encryption key bit 0
ccn NF
17:16 INTREF_SEL Calibration I/O PAD VREF selection
00: 0.5*VDDQ
01: 0.6*VDDQ
10: 0.7*VDDQ
11: 0.8*VDDQ
ase O
15 DRDELSWEN Enable DQS input delay switching for different ranks
0: disable
1: enable
@ KC
11:9 DRDELSWSEL Timing control of DQS input delay switching for different ranks
Unit: DRAMC clock
8 AUTOCALDRV OCD calibration
0: calibration disable
1: calibration enable
7:0 AUTOKCNT Auto calibration counter
xia E
Set timer for calibration cycle
Unit: DRAMC clock
ny AT
1E005104 LBWDAT0 LOOP BACK DATA 0 0000000
0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name LBWDATA0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name LBWDATA0[15:0]
Type RW
Reset
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 LBWDATA0 Loop-back test mode data 0
1E005108 LBWDAT1 LOOP BACK DATA 1 0000000
FO
PGMT7621_V.1.0_130607 Page 261 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name LBWDATA1[31:16]
Type RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LBWDATA1[15:0]
Type RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 LBWDATA1 Loop-back test mode data 1
.co IDE
1E00510C LBWDAT2 LOOP BACK DATA 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name LBWDATA2[31:16]
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LBWDATA2[15:0]
Type RW
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
31:0 LBWDATA2 Loop-back test mode data 2
1E005110 RKCFG RANK CONFIGURATION 0305110
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RKSIZE XRTW2W XRTW2R
ny AT
Type RW RW RW
Reset 0 1 1 0 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PB
MR RK
RE
XRTR2W XRTR2R S2R SW RKMODE
FE
K AP
To DI
N
Type RW RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 0 0 0 0
R E
Bit(s) Name Description
26:24 RKSIZE Rank address selection
000: ADDR[31]
M
001: ADDR[30]
010: ADDR[29]
011: ADDR[28]
100: ADDR[27]
101: ADDR[26]
110: ADDR[25]
111: ADDR[24]
19:18 XRTW2W cross rank timing W2W
Unit: DRAM controller clock
FO
PGMT7621_V.1.0_130607 Page 262 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
17:16 XRTW2R cross rank timing W2R
US L
Unit: DRAM controller clock
EO
14:12 XRTR2W cross rank timing R2W; note that XRTR2W = 6/7 have the same setting
cn IA
Unit: DRAM controller clock
10:8 XRTR2R cross rank timing R2R
Unit: DRAM controller clock
7 PBREFEN Per-bank refresh enable for LPDDR2
m. NT
0: disable
1: enable
4 MRS2RK MRS commands are sent to 2 ranks simulataneously
0: disable
1: enable
.co IDE
3 RKSWAP swap CS<->CS1
0: disable
1: enable
2:0 RKMODE Multi-rank mode support
Set to non-zero for multi-rank
ccn NF
1E005114 CKPHDET CLOCK PHASE DETECTION SETTING 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name CK
PH
CN
TE
@ KC
N
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CKPHCHKCYC
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
23 CKPHCNTEN MEMPLL in/out clock phase detection counter enabling
0: disable
1: enable
15:0 CKPHCHKCYC MEMPLL in/out clock phase detection counter cycle
Unit: DRAMC clock
To DI
1E005124 DQSGCTL INPUT DQS GATING CONTROL 8000000
R E
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name BY BY
PA PA
NE DM
SS_ SS_
WD YP
DM DM
QS AD
PA PA
G_ _RX
D_ D_
SEL SEL
CO CO
M1 M0
Type RW RW RW RW
Reset 1 0 0 0
FO
PGMT7621_V.1.0_130607 Page 263 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name DQSG_CO DQSG_CO
EO
DQSG_FINE_DLY_COM1 DQSG_FINE_DLY_COM0 ARSE_DL ARSE_DL
Y_COM1 Y_COM0
cn IA
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
31 NEWDQSG_SEL DQS gating control method
0: old
1: new
18 BYPASS_DMPAD_CO Bypass dummy PAD for DQS2/3 gating signal
M1 0: not bypass
.co IDE
1: bypass
17 BYPASS_DMPAD_CO Bypass dummy PAD for DQS0/1 gating signal
M0 0: not bypass
1: bypass
16 DMYPAD_RXSEL Select O/O1 pin of dummy PAD for gating signal input
0: O pin
1: O1 pin
ccn NF
15:12 DQSG_FINE_DLY_CO Fine tune delay setting for DQS2/3 gating signal before dummy PAD
M1 Unit: 20ps
11:8 DQSG_FINE_DLY_CO Fine tune delay setting for DQS1/0 gating signal before dummy PAD
M0 Unit: 20ps
ase O
5:4 DQSG_COARSE_DLY Coarse tune delay setting for DQS2/3 gating signal before dummy PAD
_COM1 Unit: 0.25/0.5T of DRAMC clock under 2X/1X mode
1:0 DQSG_COARSE_DLY Coarse tune delay setting for DQS0/1 gating signal before dummy PAD
@ KC
_COM0 Unit: 0.25/0.5T of DRAMC clock under 2X/1X mode
1E005130 CLKENCTL DRAM CLOCK ENABLE CONTROL 1000000
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL CL
ny AT
K1E K0E
N N
Type RW RW
Reset 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
To DI
Type
Reset
Bit(s) Name Description
R E
29 CLK1EN DRAM clock 1 enable
0: disable
1: enable
M
28 CLK0EN DRAM clock 0 enable
0: disable
1: enable
1E005140 DQSGCTL1 DQS gating delay control 1 0000000
FO
PGMT7621_V.1.0_130607 Page 264 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name DQSIPRE1DLY DQSIPOS1DLY
Type RW RW
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQSIPRE0DLY DQSIPOS0DLY
Type RW RW
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:24 DQSIPRE1DLY DQS PRE delay control for DQS1
22:16 DQSIPOS1DLY DQS POS delay control for DQS1
.co IDE
14:8 DQSIPRE0DLY DQS PRE delay control for DQS0
6:0 DQSIPOS0DLY DQS POS delay control for DQS0
1E005144 DQSGCTL2 DQS gating delay control 2 0000000
ccn NF
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQSIPRE3DLY DQSIPOS3DLY
Type RW RW
Reset
ase O
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQSIPRE2DLY DQSIPOS2DLY
Type RW RW
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:24 DQSIPRE3DLY DQS PRE delay control for DQS3
22:16 DQSIPOS3DLY DQS POS delay control for DQS3
xia E
14:8 DQSIPRE2DLY DQS PRE delay control for DQS2
6:0 DQSIPOS2DLY DQS POS delay control for DQS2
ny AT
1E005168 ARBCTL0 ARBITRATION CONTROL 0 0000000
0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name MAXPENDCNT
Type RW
M
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7:0 MAXPENDCNT Maximum pending number to block the arbitration
1E0051A8 CMDDLY0 Command Delay CTL0 0000000
FO
PGMT7621_V.1.0_130607 Page 265 of 349
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MT7621 PROGRAMMING GUIDE
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NL
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name RA3DLY RA2DLY
Type RW RW
cn IA
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RA1DLY RA0DLY
Type RW RW
m. NT
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 RA3DLY RA output delay chain setting for bit3
Unit: 20ps
.co IDE
19:16 RA2DLY RA output delay chain setting for bit2
Unit: 20ps
11:8 RA1DLY RA output delay chain setting for bit1
Unit: 20ps
3:0 RA0DLY RA output delay chain setting for bit0
Unit: 20ps
ccn NF
1E0051AC CMDDLY1 Command Delay CTL1 0000000
0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RA7DLY RA6DLY
@ KC
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RA5DLY RA4DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
27:24 RA7DLY RA output delay chain setting for bit7
ny AT
Unit: 20ps
19:16 RA6DLY RA output delay chain setting for bit6
Unit: 20ps
11:8 RA5DLY RA output delay chain setting for bit5
Unit: 20ps
To DI
3:0 RA4DLY RA output delay chain setting for bit4
Unit: 20ps
R E
1E0051B0 CMDDLY2 Command Delay CTL2 0000000
M
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RA11DLY RA10DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RA9DLY RA8DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
FO
PGMT7621_V.1.0_130607 Page 266 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
Bit(s) Name Description
EO
27:24 RA11DLY RA output delay chain setting for bit11
cn IA
Unit: 20ps
19:16 RA10DLY RA output delay chain setting for bit10
Unit: 20ps
11:8 RA9DLY RA output delay chain setting for bit9
m. NT
Unit: 20ps
3:0 RA8DLY RA output delay chain setting for bit8
Unit: 20ps
.co IDE
1E0051B4 CMDDLY3 Command Delay CTL3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BA2DLY BA1DLY
Type RW RW
Reset
ccn NF 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BA0DLY RA12DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
27:24 BA2DLY BA output delay chain setting for bit2
@ KC
Unit: 20ps
19:16 BA1DLY BA output delay chain setting for bit1
Unit: 20ps
11:8 BA0DLY BA output delay chain setting for bit0
Unit: 20ps
3:0 RA12DLY RA output delay chain setting for bit12
xia E
Unit: 20ps
ny AT
1E0051B8 CMDDLY4 Command Delay CTL4 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
To DI
Name CASDLY RASDLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name CS CS
MO MO
CKEDLY CSDLY
NS NE
M
EL N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:24 CASDLY CAS output delay chain setting
Unit: 20ps
20:16 RASDLY RAS output delay chain setting
FO
PGMT7621_V.1.0_130607 Page 267 of 349
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MT7621 PROGRAMMING GUIDE
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NL
Unit: 20ps
US L
12:8 CKEDLY CKE output delay chain setting
EO
Unit: 20ps
cn IA
6 CSMONSEL DQSIEN monitor through CS select (only for 6517)
5 CSMONEN DQSIEN monitor through CS enable (only for 6517)
4:0 CSDLY CS output delay chain setting
Unit: 20ps
m. NT
1E0051BC CMDDLY5 Command Delay CTL5 0000000
0
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CS CS
XM XM
OTDLY RA13DLY
ON ON
SEL EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15
ccn NF
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WEDLY
Type RW
Reset 0 0 0 0 0
ase O
Bit(s) Name Description
30 CSXMONSEL DQSIEN monitor through CS1 select (only for 6517)
29 CSXMONEN DQSIEN monitor through CS1 enable (only for 6517)
@ KC
28:24 OTDLY OTD output delay chain setting
Unit: 20ps
20:16 RA13DLY RA output delay chain setting for bit13
Unit: 20ps
12:8 WEDLY WE output delay chain setting
Unit: 20ps
xia E
ny AT
1E0051C0 DQSCAL0 DQS CAL CONTROL 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ST
To DI
BC
RA14DLY
AL
EN
Type RW RW
Reset 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ
DQ
M
SIE
SIE
NH
DQSIENHLMT NLL DQSIENLLMT
LM
MT
TE
EN
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
PGMT7621_V.1.0_130607 Page 268 of 349
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MT7621 PROGRAMMING GUIDE
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NL
31 STBCALEN DQS strobe calibration enable
US L
0: disable
EO
1: enable
28:24 RA14DLY RA output delay chain setting for bit14
cn IA
Unit: 20ps
15 DQSIENHLMTEN DQS strobe calibration high-limit enable
0: disable
1: enable
m. NT
14:8 DQSIENHLMT DQS strobe calibration high-limit value
7 DQSIENLLMTEN DQS strobe calibration low-limit enable
0: disable
1: enable
.co IDE
6:0 DQSIENLLMT DQS strobe calibration low-limit value
1E0051D8 DMMonitor Monitor parameter NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name JMTRCNT
ccn NF
Type RW
Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BU MO
SM NP JM
ase O
DSMONSEL ON AU TR_
EN_ SE_ EN
SW SW
Type RW RW RW RW
@ KC
Reset 10b' 10b' 10b' 10b' 10b' 10b' 10b' 10b' 10b' 10b'
000 000 000 000 000 000 000 000 000 000
000 000 000 000 000 000 000 000 000 000 0 0 0
000 000 000 000 000 000 000 000 000 000
0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:16 JMTRCNT Set monitor Period for Jitter Meter
13:4 DSMONSEL DQSIEN monitor signal selection (only for 6517)
ny AT
3 BUSMONEN_SW Bus monitor enable. Can't use with BUSMONEN_HW at the same time.
0: disable
1: enable
2 MONPAUSE_SW Pause Bus monitor Counter. Can't use with MONPAUSE_HW at the same time.
0: disable
To DI
1: enable
0 JMTR_EN Jitter meter enable
0: disable
1: enable
R E
M
1E0051DC DRAMC_PD_ PD mode parameter 0062284
CTRL 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MIO
REF
CK DC
FRE
CT ME REFCNT_FR_CLK
RU
RL N
N
OF
FO
PGMT7621_V.1.0_130607 Page 269 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
F
US L
Type RW RW RW RW
EO
Reset 0 0 0 0 1 1 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name TXREFCNT DCMDLYREF
Type RW RW
Reset 0 0 1 0 1 0 0 0 1 0 0
m. NT
Bit(s) Name Description
26 MIOCKCTRLOFF dram clk gating parameter
1 : always no gating
0 : controlled by dramc
25 DCMEN DRAMC non-freerun clock gating function
.co IDE
0: disable
1: enable
24 REFFRERUN Using FREE-RUN CLK to count reflesh period
23:16 REFCNT_FR_CLK Refresh period = (REFCNT_FR_CLK) DRAMC FREE-RUN clock cycles
Setting the value according to DRAM spec and DRAMC FREE-RUN frequency
15:8 TXREFCNT tXSR
ccn NF 258T/3T~258T for DDR3/LPDDR2
6:4 DCMDLYREF Number of delay cycles to wake up DCM by the refresh command, which is
counted by the FREE-RUN clock
Note that this value can't be set to 3'b000!
ase O
1E0051E0 LPDDR2 LPDDR2 setting 0000000
@ KC
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name AD SEL
DD
LP WD
FA DD DD DD DD DD DD DD
DD
RD O1 DD AT RB
RA ST RC RO RC RC RR RC RW
EC AS R2E RG A[2:
14 OE S1 DT KE S AS AS E
EN O N O 2]
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Name DDRBA[1:
DDRA
0]
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
31 ADRDECEN DRAM address decode
0: by EMI
1: by DRAMC
R E
30 SELO1ASO Select IO O1 as output
0: select O
1: select O1
M
29 DDRA14 DDR mode for A[14] pin (LPDDR2 DDR command rate)
0: disable
1: enable
28 LPDDR2EN LPDDR2 enable
0: disable
1: enable
27 WDATRGO Enable register output data by DRAMC
0: disable
FO
PGMT7621_V.1.0_130607 Page 270 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: enable
US L
26 FASTOE Fast IO output enable
EO
0: disable
1: enable
cn IA
24 DDRCS1 DDR mode for CS1 pin (LPDDR2 DDR command rate)
0: disable
1: enable
22 DDRODT DDR mode for ODT pin (LPDDR2 DDR command rate)
m. NT
0: disable
1: enable
21 DDRCKE DDR mode for CKE pin (LPDDR2 DDR command rate)
0: disable
1: enable
.co IDE
20 DDRCS DDR mode for CS pin (LPDDR2 DDR command rate)
0: disable
1: enable
19 DDRRAS DDR mode for RAS pin (LPDDR2 DDR command rate)
0: disable
1: enable
18
ccn NF
DDRCAS DDR mode for CAS pin (LPDDR2 DDR command rate)
0: disable
1: enable
17 DDRWE DDR mode for WE pin (LPDDR2 DDR command rate)
0: disable
ase O
1: enable
16:14 DDRBA DDR mode for BA[2:0] pin (LPDDR2 DDR command rate)
0: disable
@ KC
1: enable
13:0 DDRA DDR mode for A[13:0] pin (LPDDR2 DDR command rate)
0: disable
1: enable
xia E
1E0051E4 SPCMD Special command mode 0000000
0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PADRG_RDSEL ZQCSCNT
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
To DI
Name DQ DQ
CM SG SG TC ZQ AR PR MR MR
PP CN CN MD CE EFE EA RE WE
D TR TE EN N N EN N N
ST N
R E
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:28 PADRG_RDSEL PAD Ring RDSEL (only for 6517)
23:16 ZQCSCNT Every refresh number to issue ZQCS commands, only for DDR3
13 CMPPD Power down control of CMP IO
9 DQSGCNTRST DQS gating window counter Reset
8 DQSGCNTEN DQS gating window counter Enable
FO
PGMT7621_V.1.0_130607 Page 271 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
5 TCMDEN Test command enable
US L
0: disable
EO
1: enable
4 ZQCEN ZQ calibration enable
cn IA
0: disable
1: enable
3 AREFEN Auto Refresh command enable
0: disable
m. NT
1: enable
2 PREAEN Precharge all command enable
0: disable
1: enable
1 MRREN Mode register read command enable
.co IDE
0: disable
1: enable
0 MRWEN Mode register write command enable
0: disable
ccn NF 1: enable
1E0051E8 ACTIM1 DRAM AC TIMING SETTING 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ase O
Name TRPAB REFRCNT
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TR TFA TR
RD W_ C_
TRFCPB TRFC_BIT7_4
_BI BIT BIT
T2 4 4
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
25:24 TRPAB All-bank precharge timing for LPDDR2
tRPAB = TRP + TRPAB
23:16 REFRCNT Every refresh number to issue MRR commands for refresh rates, only for
LPDDR2
15:8 TRFCPB tRFCPB Timing setting
To DI
tRFCPB = (11 + TRFCPB[7:0]) DRAMC clock cycles
7:4 TRFC_BIT7_4 tRFC Timing setting for bit 7 ~ 4
3 TRRD_BIT2 tRRD Timing setting for bit 2
1 TFAW_BIT4 tFAW Timing setting for bit 4
R E
0 TRC_BIT4 tRC Timing setting for bit 4
M
1E0051EC PERFCTL0 PERFORMANCE CONTROL 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DIS
DM
OE
DIS
FO
PGMT7621_V.1.0_130607 Page 272 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW
Reset
US L
0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RW RW RW RW
DU
cn IA
CS2 AL
AG LLA HP OF
RA RWOFOWNUM SC
EE TE RIE OE
NK HE
N N N N
N
Type RW RW RW RW RW RW RW
m. NT
Reset 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
16 DISDMOEDIS For power saving, the self-refresh may disable the IO output enable
0: enable the power saving function
.co IDE
1: disable the power saving function
12 CS2RANK CS0 is also applied to CS1
0: disable
1: enable
10 RWAGEEN Support EMI read/write aging tag
0: Not support
ccn NF 1: Support
9 RWLLATEN Support EMI read/write low-latency
0: Not support
1: Support
8 RWHPRIEN Support EMI read/write high-priority
ase O
0: Not support
1: Support
7:5 RWOFOWNUM Coniinous write transactions allowed
@ KC
4 RWOFOEN Enable read/write out of order control
0: disable
1: enable
0 DUALSCHEN Enable dual schedulers, only effective under FDIV2 = 1
0: disable
1: enable
xia E
ny AT
1E0051F0 AC_DERATIN AC TIME DERATING CONTROL 0000000
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TRPAB_D
TRRD_DERATE TRP_DERATE TRAS_DERATE
ERATE
To DI
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AC
R E
DE
TRC_DERATE TRCD_DERATE RA
TEE
M
N
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:28 TRRD_DERATE tRRD de-rate timing setting
tRRD = (1 + TRRD_DERATE) DRAMC clock cycles
25:24 TRPAB_DERATE All-bank precharge de-rate timing for LPDDR2
FO
PGMT7621_V.1.0_130607 Page 273 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
tRPAB = TRP_DERATE + TRPAB_DERATE
US L
23:20 TRP_DERATE tRP de-rate timing setting
EO
tRP = (1 + TRP_DERATE) DRAMC clock cycles
cn IA
19:16 TRAS_DERATE tRAS de-rate timing setting
tRAS = (8 + TRAS_DERATE) DRAMC clock cycles
12:8 TRC_DERATE tRC de-rate timing setting
tRC = (8 + TRC_DERATE) DRAMC clock cycles
m. NT
7:4 TRCD_DERATE tRCD de-rate timing setting
tRCD = (1 + TRCD_DERATE) DRAMC clock cycles
0 ACDERATEEN Enable LPDDR2 AC timing de-rating control, effective when REFRESH_RATE >=
6
0: disable
.co IDE
1: enable
1E0051F4 RRRATE_CTL REFRESH RATE CONTROL 0002010
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ccn NF
Name RR_BIT2_SEL
Type RW
Reset 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RR_BIT1_SEL RR_BIT0_SEL
ase O
Type RW RW
Reset 0 0 0 0 1 0 0 0 0 0
@ KC
Bit(s) Name Description
20:16 RR_BIT2_SEL Refresh rate data bit 2 selection from 32-bit input read data
00000: select bit 0
00001: select bit 1
00010: select bit 2
.
11111: select bit 31
xia E
12:8 RR_BIT1_SEL Refresh rate data bit 1 selection from 32-bit input read data
00000: select bit 0
ny AT
00001: select bit 1
00010: select bit 2
.
11111: select bit 31
4:0 RR_BIT0_SEL Refresh rate data bit 0 selection from 32-bit input read data
00000: select bit 0
To DI
00001: select bit 1
00010: select bit 2
.
11111: select bit 31
R E
M
1E0051F8 WPATCMP_D WRITE PATTERN COMPARE SETTING 0000000
AT 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WPATCMP[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WPATCMP[15:0]
FO
PGMT7621_V.1.0_130607 Page 274 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW
Reset
US L
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
cn IA
31:0 WPATCMP Write data pattern to be compared for interrupting write commands
m. NT
1E0051FC WPATCMP_C WRITE PATTERN COMPARE CONTROL 0000000
TL 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WP
.co IDE
AT_
WPAT_BL
ST
KCYC
CL
R
Type RW RW
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WPAT_INVEN WPAT_CMPEN
ccn NF
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
20 WPAT_STCLR Clear the write pattern hit counter WPAT_HIT_CNT (REG.3FC[7:0])
ase O
17:16 WPAT_BLKCYC Block write command cycles during interruption
0/1/2/3: 1/2/3/4T
@ KC
15:8 WPAT_INVEN Inversion control for 8 sets of 32-bit write compare data WPATCMP
7:0 WPAT_CMPEN Enable write data compare sequence
bit 0: PAT0, PAT1, PAT2, PAT3, PAT4, PAT5, PAT6, PAT7
bit 1: PAT7, PAT0, PAT1, PAT2, PAT3, PAT4, PAT5, PAT6
bit 2: PAT6, PAT7, PAT0, PAT1, PAT2, PAT3, PAT4, PAT5
.
bit7: PAT1, PAT2, PAT3, PAT4, PAT5, PAT6, PAT7, PAT0
xia E
ny AT
1E005200 DQODLY1 DQ output DELAY1 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ7DLY DQ6DLY DQ5DLY DQ4DLY
To DI
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ3DLY DQ2DLY DQ1DLY DQ0DLY
Type RW RW RW RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:28 DQ7DLY DQ output delay chain setting for bit7
Unit: 20ps
27:24 DQ6DLY DQ output delay chain setting for bit6
Unit: 20ps
23:20 DQ5DLY DQ output delay chain setting for bit5
Unit: 20ps
FO
PGMT7621_V.1.0_130607 Page 275 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
19:16 DQ4DLY DQ output delay chain setting for bit4
US L
Unit: 20ps
EO
15:12 DQ3DLY DQ output delay chain setting for bit3
cn IA
Unit: 20ps
11:8 DQ2DLY DQ output delay chain setting for bit2
Unit: 20ps
7:4 DQ1DLY DQ output delay chain setting for bit1
m. NT
Unit: 20ps
3:0 DQ0DLY DQ output delay chain setting for bit0
Unit: 20ps
.co IDE
1E005204 DQODLY2 DQ output DELAY2 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ15DLY DQ14DLY DQ13DLY DQ12DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ11DLY DQ10DLY DQ9DLY DQ8DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
31:28 DQ15DLY DQ output delay chain setting for bit15
@ KC
Unit: 20ps
27:24 DQ14DLY DQ output delay chain setting for bit14
Unit: 20ps
23:20 DQ13DLY DQ output delay chain setting for bit13
Unit: 20ps
19:16 DQ12DLY DQ output delay chain setting for bit12
xia E
Unit: 20ps
15:12 DQ11DLY DQ output delay chain setting for bit11
ny AT
Unit: 20ps
11:8 DQ10DLY DQ output delay chain setting for bit10
Unit: 20ps
7:4 DQ9DLY DQ output delay chain setting for bit9
Unit: 20ps
To DI
3:0 DQ8DLY DQ output delay chain setting for bit8
Unit: 20ps
R E
1E005208 DQODLY3 DQ output DELAY3 CHAIN setting 0000000
M
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ23DLY DQ22DLY DQ21DLY DQ20DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ19DLY DQ18DLY DQ17DLY DQ16DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
PGMT7621_V.1.0_130607 Page 276 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
Bit(s) Name Description
EO
31:28 DQ23DLY DQ output delay chain setting for bit23
cn IA
Unit: 20ps
27:24 DQ22DLY DQ output delay chain setting for bit22
Unit: 20ps
23:20 DQ21DLY DQ output delay chain setting for bit21
m. NT
Unit: 20ps
19:16 DQ20DLY DQ output delay chain setting for bit20
Unit: 20ps
15:12 DQ19DLY DQ output delay chain setting for bit19
Unit: 20ps
.co IDE
11:8 DQ18DLY DQ output delay chain setting for bit18
Unit: 20ps
7:4 DQ17DLY DQ output delay chain setting for bit17
Unit: 20ps
3:0 DQ16DLY DQ output delay chain setting for bit16
Unit: 20ps
ccn NF
1E00520C DQODLY4 DQ output DELAY4 CHAIN setting 0000000
0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ31DLY DQ30DLY DQ29DLY DQ28DLY
@ KC
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ27DLY DQ26DLY DQ25DLY DQ24DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
31:28 DQ31DLY DQ output delay chain setting for bit31
ny AT
Unit: 20ps
27:24 DQ30DLY DQ output delay chain setting for bit30
Unit: 20ps
23:20 DQ29DLY DQ output delay chain setting for bit29
Unit: 20ps
To DI
19:16 DQ28DLY DQ output delay chain setting for bit28
Unit: 20ps
15:12 DQ27DLY DQ output delay chain setting for bit27
R E
Unit: 20ps
11:8 DQ26DLY DQ output delay chain setting for bit26
Unit: 20ps
M
7:4 DQ25DLY DQ output delay chain setting for bit25
Unit: 20ps
3:0 DQ24DLY DQ output delay chain setting for bit24
Unit: 20ps
FO
PGMT7621_V.1.0_130607 Page 277 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E005210 DQIDLY1 DQ input DELAY1 CHAIN setting 0000000
US L
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name DQ3DEL DQ2DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name DQ1DEL DQ0DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
27:24 DQ3DEL DQ input delay chain setting for bit3
Unit: 20ps
19:16 DQ2DEL DQ input delay chain setting for bit2
Unit: 20ps
11:8 DQ1DEL DQ input delay chain setting for bit1
Unit: 20ps
ccn NF
3:0 DQ0DEL DQ input delay chain setting for bit0
Unit: 20ps
ase O
1E005214 DQIDLY2 DQ input DELAY2 CHAIN setting 0000000
0
@ KC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ7DEL DQ6DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ5DEL DQ4DEL
Type RW RW
Reset
xia E
0 0 0 0 0 0 0 0
Bit(s) Name Description
ny AT
27:24 DQ7DEL DQ input delay chain setting for bit7
Unit: 20ps
19:16 DQ6DEL DQ input delay chain setting for bit6
Unit: 20ps
To DI
11:8 DQ5DEL DQ input delay chain setting for bit5
Unit: 20ps
3:0 DQ4DEL DQ input delay chain setting for bit4
Unit: 20ps
R E
M
1E005218 DQIDLY3 DQ input DELAY3 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ11DEL DQ10DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ9DEL DQ8DEL
FO
PGMT7621_V.1.0_130607 Page 278 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW RW
Reset
US L
0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
cn IA
27:24 DQ11DEL DQ input delay chain setting for bit11
Unit: 20ps
19:16 DQ10DEL DQ input delay chain setting for bit10
m. NT
Unit: 20ps
11:8 DQ9DEL DQ input delay chain setting for bit9
Unit: 20ps
3:0 DQ8DEL DQ input delay chain setting for bit8
Unit: 20ps
.co IDE
1E00521C DQIDLY4 DQ input DELAY4 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ccn NF DQ15DEL DQ14DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ13DEL DQ12DEL
Type RW RW
ase O
Reset 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
27:24 DQ15DEL DQ input delay chain setting for bit15
Unit: 20ps
19:16 DQ14DEL DQ input delay chain setting for bit14
Unit: 20ps
11:8 DQ13DEL DQ input delay chain setting for bit13
xia E
Unit: 20ps
3:0 DQ12DEL DQ input delay chain setting for bit12
ny AT
Unit: 20ps
1E005220 DQIDLY5 DQ input DELAY5 CHAIN setting 0000000
0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ19DEL DQ18DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ17DEL DQ16DEL
M
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 DQ19DEL DQ input delay chain setting for bit19
Unit: 20ps
19:16 DQ18DEL DQ input delay chain setting for bit18
Unit: 20ps
FO
PGMT7621_V.1.0_130607 Page 279 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
11:8 DQ17DEL DQ input delay chain setting for bit17
US L
Unit: 20ps
EO
3:0 DQ16DEL DQ input delay chain setting for bit16
cn IA
Unit: 20ps
1E005224 DQIDLY6 DQ input DELAY6 CHAIN setting 0000000
m. NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ23DEL DQ22DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ21DEL DQ20DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
27:24 DQ23DEL DQ input delay chain setting for bit23
Unit: 20ps
19:16 DQ22DEL DQ input delay chain setting for bit22
Unit: 20ps
11:8 DQ21DEL DQ input delay chain setting for bit21
ase O
Unit: 20ps
3:0 DQ20DEL DQ input delay chain setting for bit20
@ KC
Unit: 20ps
1E005228 DQIDLY7 DQ input DELAY7 CHAIN setting 0000000
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ27DEL DQ26DEL
Type RW RW
ny AT
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ25DEL DQ24DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
27:24 DQ27DEL DQ input delay chain setting for bit27
Unit: 20ps
R E
19:16 DQ26DEL DQ input delay chain setting for bit26
Unit: 20ps
M
11:8 DQ25DEL DQ input delay chain setting for bit25
Unit: 20ps
3:0 DQ24DEL DQ input delay chain setting for bit24
Unit: 20ps
1E00522C DQIDLY8 DQ input DELAY8 CHAIN setting 0000000
FO
PGMT7621_V.1.0_130607 Page 280 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name DQ31DEL DQ30DEL
Type RW RW
cn IA
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ29DEL DQ28DEL
Type RW RW
m. NT
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 DQ31DEL DQ input delay chain setting for bit31
Unit: 20ps
.co IDE
19:16 DQ30DEL DQ input delay chain setting for bit30
Unit: 20ps
11:8 DQ29DEL DQ input delay chain setting for bit29
Unit: 20ps
3:0 DQ28DEL DQ input delay chain setting for bit28
Unit: 20ps
ccn NF
1E005280 R2R_page_hit R2R_page_hit_counter 0000000
_counter 0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2R_page_hit_counter[31:16]
@ KC
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2R_page_hit_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
31:0 R2R_page_hit_counter R2R_page_hit_counter
ny AT
1E005284 R2R_page_mi R2R_page_miss_counter 0000000
ss_counter 0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2R_page_miss_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2R_page_miss_counter[15:0]
Type RO
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 R2R_page_miss_count R2R_page_miss_counter
er
FO
PGMT7621_V.1.0_130607 Page 281 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E005288 R2R_interban R2R_interbank_counter 0000000
US L
EO
k_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name R2R_interbank_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name R2R_interbank_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:0 R2R_interbank_counte R2R_interbank_counter
r
1E00528C R2W_page_hi R2W_page_hit_counter 0000000
t_counter 0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2W_page_hit_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name R2W_page_hit_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:0 R2W_page_hit_counte R2W_page_hit_counter
r
xia E
1E005290 R2W_page_mi R2W_page_miss_counter 0000000
ny AT
ss_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2W_page_miss_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2W_page_miss_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
31:0 R2W_page_miss_coun R2W_page_miss_counter
M
ter
1E005294 R2W_interban R2W_interbank_counter 0000000
k_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2W_interbank_counter[31:16]
FO
PGMT7621_V.1.0_130607 Page 282 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RO
Reset
US L
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2W_interbank_counter[15:0]
cn IA
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
31:0 R2W_interbank_counte R2W_interbank_counter
r
.co IDE
1E005298 W2R_page_hi W2R_page_hit_counter 0000000
t_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2R_page_hit_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ccn NF
Name W2R_page_hit_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ase O
31:0 W2R_page_hit_counte W2R_page_hit_counter
r
@ KC
1E00529C W2R_page_mi W2R_page_miss_counter 0000000
ss_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
xia E
W2R_page_miss_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2R_page_miss_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
To DI
31:0 W2R_page_miss_coun W2R_page_miss_counter
ter
R E
1E0052A0 W2R_interban W2R_interbank_counter 0000000
M
k_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2R_interbank_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2R_interbank_counter[15:0]
Type RO
FO
PGMT7621_V.1.0_130607 Page 283 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit(s) Name Description
cn IA
31:0 W2R_interbank_counte W2R_interbank_counter
r
m. NT
1E0052A4 W2W_page_hi W2W_page_hit_counter 0000000
t_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2W_page_hit_counter[31:16]
Type
.co IDE
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2W_page_hit_counter[15:0]
Type RO
Reset 0 0
ccn NF 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 W2W_page_hit_counte W2W_page_hit_counter
r
ase O
1E0052A8 W2W_page_m W2W_page_miss_counter 0000000
iss_counter 0
@ KC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2W_page_miss_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2W_page_miss_counter[15:0]
Type
xia E
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:0 W2W_page_miss_cou W2W_page_miss_counter
nter
To DI
1E0052AC W2W_interba W2W_interbank_counter 0000000
nk_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name W2W_interbank_counter[31:16]
Type RO
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2W_interbank_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 W2W_interbank_count W2W_interbank_counter
er
FO
PGMT7621_V.1.0_130607 Page 284 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E0052B0 dramc_idle_c dramc_idle_counter 0000000
cn IA
ounter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dramc_idle_counter[31:16]
Type RO
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dramc_idle_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:0 dramc_idle_counter dramc_idle_counter
1E0052B4
ccn NF
freerun_26m_ freerun_26m_counter 0000000
counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name freerun_26m_counter[31:16]
Type RO
ase O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name freerun_26m_counter[15:0]
@ KC
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 freerun_26m_counter freerun_26m_counter
xia E
1E0052B8 refresh_pop_ refresh_pop_counter 0000000
ny AT
counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name refresh_pop_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name refresh_pop_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R E
Bit(s) Name Description
M
31:0 refresh_pop_counter refresh_pop_counter
1E0052BC JMETER_ST Jitter Meter Status 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name JM ONES_CNT
FO
PGMT7621_V.1.0_130607 Page 285 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
TR_
US L
DO
EO
NE
Type RO RO
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ZEROS_CNT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31 JMTR_DONE Jitter meter result is updated.
0: not ready
1: update result.
.co IDE
30:16 ONES_CNT ones counter result
14:0 ZEROS_CNT zeros counter result
1E0052C0 DQ_CAL_MA DQ INPUT CALIBRATION per bit 3-0 0000000
ccn NF
X_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ0_3_DLY_MAX DQ0_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ0_1_DLY_MAX DQ0_0_DLY_MAX
Type RO RO
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ0_3_DLY_MAX DQ bit3 input maximum delay
23:16 DQ0_2_DLY_MAX DQ bit2 input maximum delay
xia E
15:8 DQ0_1_DLY_MAX DQ bit1 input maximum delay
7:0 DQ0_0_DLY_MAX DQ bit0 input maximum delay
ny AT
1E0052C4 DQ_CAL_MA DQ INPUT CALIBRATION per bit 7-4 0000000
X_1 0
To DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ0_7_DLY_MAX DQ0_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R E
Name DQ0_5_DLY_MAX DQ0_4_DLY_MAX
Type RO RO
Reset
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ0_7_DLY_MAX DQ bit7 input maximum delay
23:16 DQ0_6_DLY_MAX DQ bit6 input maximum delay
15:8 DQ0_5_DLY_MAX DQ bit5 input maximum delay
7:0 DQ0_4_DLY_MAX DQ bit4 input maximum delay
FO
PGMT7621_V.1.0_130607 Page 286 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E0052C8 DQ_CAL_MA DQ INPUT CALIBRATION per bit 11-8 0000000
cn IA
X_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ1_3_DLY_MAX DQ1_2_DLY_MAX
Type RO RO
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ1_1_DLY_MAX DQ1_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit(s) Name Description
31:24 DQ1_3_DLY_MAX DQ bit11 input maximum delay
23:16 DQ1_2_DLY_MAX DQ bit10 input maximum delay
15:8 DQ1_1_DLY_MAX DQ bit9 input maximum delay
7:0 DQ1_0_DLY_MAX DQ bit8 input maximum delay
ccn NF
1E0052CC DQ_CAL_MA DQ INPUT CALIBRATION per bit 15-12 0000000
X_3 0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ1_7_DLY_MAX DQ1_6_DLY_MAX
@ KC
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ1_5_DLY_MAX DQ1_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
31:24 DQ1_7_DLY_MAX DQ bit15 input maximum delay
ny AT
23:16 DQ1_6_DLY_MAX DQ bit14 input maximum delay
15:8 DQ1_5_DLY_MAX DQ bit13 input maximum delay
7:0 DQ1_4_DLY_MAX DQ bit12 input maximum delay
To DI
1E0052D0 DQ_CAL_MA DQ INPUT CALIBRATION per bit 19-16 0000000
X_4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R E
Name DQ2_3_DLY_MAX DQ2_2_DLY_MAX
Type RO RO
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ2_1_DLY_MAX DQ2_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ2_3_DLY_MAX DQ bit19 input maximum delay
FO
PGMT7621_V.1.0_130607 Page 287 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
23:16 DQ2_2_DLY_MAX DQ bit18 input maximum delay
US L
15:8 DQ2_1_DLY_MAX DQ bit17 input maximum delay
EO
7:0 DQ2_0_DLY_MAX DQ bit16 input maximum delay
cn IA
1E0052D4 DQ_CAL_MA DQ INPUT CALIBRATION per bit 23-20 0000000
m. NT
X_5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ2_7_DLY_MAX DQ2_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ2_5_DLY_MAX DQ2_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ2_7_DLY_MAX DQ bit23 input maximum delay
ccn NF
23:16 DQ2_6_DLY_MAX DQ bit22 input maximum delay
15:8 DQ2_5_DLY_MAX DQ bit21 input maximum delay
7:0 DQ2_4_DLY_MAX DQ bit20 input maximum delay
ase O
1E0052D8 DQ_CAL_MA DQ INPUT CALIBRATION per bit 27-34 0000000
@ KC
X_6 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3_3_DLY_MAX DQ3_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
xia E
Name DQ3_1_DLY_MAX DQ3_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit(s) Name Description
31:24 DQ3_3_DLY_MAX DQ bit27 input maximum delay
23:16 DQ3_2_DLY_MAX DQ bit26 input maximum delay
To DI
15:8 DQ3_1_DLY_MAX DQ bit25 input maximum delay
7:0 DQ3_0_DLY_MAX DQ bit24 input maximum delay
R E
1E0052DC DQ_CAL_MA DQ INPUT CALIBRATION per bit 31-28 0000000
X_7 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3_7_DLY_MAX DQ3_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ3_5_DLY_MAX DQ3_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
PGMT7621_V.1.0_130607 Page 288 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
Bit(s) Name Description
EO
31:24 DQ3_7_DLY_MAX DQ bit31 input maximum delay
cn IA
23:16 DQ3_6_DLY_MAX DQ bit30 input maximum delay
15:8 DQ3_5_DLY_MAX DQ bit29 input maximum delay
7:0 DQ3_4_DLY_MAX DQ bit28 input maximum delay
m. NT
1E0052E0 DQS_CAL_MI DQS INPUT CALIBRATION per bit 3-0 0000000
N_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.co IDE
Name DQS0_3_DLY_MIN DQS0_2_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS0_1_DLY_MIN DQS0_0_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
31:24 DQS0_3_DLY_MIN DQS bit3 input minimum delay
23:16 DQS0_2_DLY_MIN DQS bit2 input minimum delay
ase O
15:8 DQS0_1_DLY_MIN DQS bit1 input minimum delay
7:0 DQS0_0_DLY_MIN DQS bit0 input minimum delay
@ KC
1E0052E4 DQS_CAL_MI DQS INPUT CALIBRATION per bit 7-4 0000000
N_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
xia E
DQS0_7_DLY_MIN DQS0_6_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS0_5_DLY_MIN DQS0_4_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:24 DQS0_7_DLY_MIN DQS bit7 input minimum delay
23:16 DQS0_6_DLY_MIN DQS bit6 input minimum delay
15:8 DQS0_5_DLY_MIN DQS bit5 input minimum delay
R E
7:0 DQS0_4_DLY_MIN DQS bit4 input minimum delay
M
1E0052E8 DQS_CAL_MI DQS INPUT CALIBRATION per bit 11-8 0000000
N_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1_3_DLY_MIN DQS1_2_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
PGMT7621_V.1.0_130607 Page 289 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name DQS1_1_DLY_MIN DQS1_0_DLY_MIN
EO
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
31:24 DQS1_3_DLY_MIN DQS bit11 input minimum delay
23:16 DQS1_2_DLY_MIN DQS bit10 input minimum delay
m. NT
15:8 DQS1_1_DLY_MIN DQS bit9 input minimum delay
7:0 DQS1_0_DLY_MIN DQS bit8 input minimum delay
.co IDE
1E0052EC DQS_CAL_MI DQS INPUT CALIBRATION per bit 15-12 0000000
N_3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1_7_DLY_MIN DQS1_6_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_5_DLY_MIN DQS1_4_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
31:24 DQS1_7_DLY_MIN DQS bit15 input minimum delay
@ KC
23:16 DQS1_6_DLY_MIN DQS bit14 input minimum delay
15:8 DQS1_5_DLY_MIN DQS bit13 input minimum delay
7:0 DQS1_4_DLY_MIN DQS bit12 input minimum delay
xia E
1E0052F0 DQS_CAL_MI DQS INPUT CALIBRATION per bit 19-16 0000000
N_4 0
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS2_3_DLY_MIN DQS2_2_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS2_1_DLY_MIN DQS2_0_DLY_MIN
To DI
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R E
31:24 DQS2_3_DLY_MIN DQS bit19 input minimum delay
23:16 DQS2_2_DLY_MIN DQS bit18 input minimum delay
M
15:8 DQS2_1_DLY_MIN DQS bit17 input minimum delay
7:0 DQS2_0_DLY_MIN DQS bit16 input minimum delay
1E0052F4 DQS_CAL_MI DQS INPUT CALIBRATION per bit 23-20 0000000
N_5 0
FO
PGMT7621_V.1.0_130607 Page 290 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name DQS2_7_DLY_MIN DQS2_6_DLY_MIN
EO
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cn IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS2_5_DLY_MIN DQS2_4_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. NT
Bit(s) Name Description
31:24 DQS2_7_DLY_MIN DQS bit23 input minimum delay
23:16 DQS2_6_DLY_MIN DQS bit22 input minimum delay
15:8 DQS2_5_DLY_MIN DQS bit21 input minimum delay
.co IDE
7:0 DQS2_4_DLY_MIN DQS bit20 input minimum delay
1E0052F8 DQS_CAL_MI DQS INPUT CALIBRATION per bit 27-34 0000000
N_6 0
ccn NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_3_DLY_MIN DQS3_2_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ase O
Name DQS3_1_DLY_MIN DQS3_0_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ KC
Bit(s) Name Description
31:24 DQS3_3_DLY_MIN DQS bit27 input minimum delay
23:16 DQS3_2_DLY_MIN DQS bit26 input minimum delay
15:8 DQS3_1_DLY_MIN DQS bit25 input minimum delay
xia E
7:0 DQS3_0_DLY_MIN DQS bit24 input minimum delay
ny AT
1E0052FC DQS_CAL_MI DQS INPUT CALIBRATION per bit 31-28 0000000
N_7 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_7_DLY_MIN DQS3_6_DLY_MIN
To DI
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3_5_DLY_MIN DQS3_4_DLY_MIN
R E
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:24 DQS3_7_DLY_MIN DQS bit31 input minimum delay
23:16 DQS3_6_DLY_MIN DQS bit30 input minimum delay
15:8 DQS3_5_DLY_MIN DQS bit29 input minimum delay
7:0 DQS3_4_DLY_MIN DQS bit28 input minimum delay
FO
PGMT7621_V.1.0_130607 Page 291 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1E005300 DQS_CAL_M DQS INPUT CALIBRATION per bit 3-0 0000000
US L
EO
AX_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name DQS0_3_DLY_MAX DQS0_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. NT
Name DQS0_1_DLY_MAX DQS0_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.co IDE
31:24 DQS0_3_DLY_MAX DQS bit3 input maximum delay
23:16 DQS0_2_DLY_MAX DQS bit2 input maximum delay
15:8 DQS0_1_DLY_MAX DQS bit1 input maximum delay
7:0 DQS0_0_DLY_MAX DQS bit0 input maximum delay
ccn NF
1E005304 DQS_CAL_M DQS INPUT CALIBRATION per bit 7-4 0000000
AX_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS0_7_DLY_MAX DQS0_6_DLY_MAX
ase O
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ KC
Name DQS0_5_DLY_MAX DQS0_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS0_7_DLY_MAX DQS bit7 input maximum delay
xia E
23:16 DQS0_6_DLY_MAX DQS bit6 input maximum delay
15:8 DQS0_5_DLY_MAX DQS bit5 input maximum delay
ny AT
7:0 DQS0_4_DLY_MAX DQS bit4 input maximum delay
1E005308 DQS_CAL_M DQS INPUT CALIBRATION per bit 11-8 0000000
To DI
AX_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1_3_DLY_MAX DQS1_2_DLY_MAX
Type RO RO
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_1_DLY_MAX DQS1_0_DLY_MAX
M
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS1_3_DLY_MAX DQS bit11 input maximum delay
23:16 DQS1_2_DLY_MAX DQS bit10 input maximum delay
15:8 DQS1_1_DLY_MAX DQS bit9 input maximum delay
FO
PGMT7621_V.1.0_130607 Page 292 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
7:0 DQS1_0_DLY_MAX DQS bit8 input maximum delay
US L
EO
cn IA
1E00530C DQS_CAL_M DQS INPUT CALIBRATION per bit 15-12 0000000
AX_3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Name DQS1_7_DLY_MAX DQS1_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_5_DLY_MAX DQS1_4_DLY_MAX
Type RO RO
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS1_7_DLY_MAX DQS bit15 input maximum delay
23:16 DQS1_6_DLY_MAX DQS bit14 input maximum delay
15:8 DQS1_5_DLY_MAX DQS bit13 input maximum delay
ccn NF
7:0 DQS1_4_DLY_MAX DQS bit12 input maximum delay
1E005310 DQS_CAL_M DQS INPUT CALIBRATION per bit 19-16 0000000
ase O
AX_4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Name DQS2_3_DLY_MAX DQS2_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS2_1_DLY_MAX DQS2_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
ny AT
31:24 DQS2_3_DLY_MAX DQS bit19 input maximum delay
23:16 DQS2_2_DLY_MAX DQS bit18 input maximum delay
15:8 DQS2_1_DLY_MAX DQS bit17 input maximum delay
7:0 DQS2_0_DLY_MAX DQS bit16 input maximum delay
To DI
1E005314 DQS_CAL_M DQS INPUT CALIBRATION per bit 23-20 0000000
AX_5 0
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS2_7_DLY_MAX DQS2_6_DLY_MAX
M
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS2_5_DLY_MAX DQS2_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO
PGMT7621_V.1.0_130607 Page 293 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
31:24 DQS2_7_DLY_MAX DQS bit23 input maximum delay
US L
23:16 DQS2_6_DLY_MAX DQS bit22 input maximum delay
EO
15:8 DQS2_5_DLY_MAX DQS bit21 input maximum delay
cn IA
7:0 DQS2_4_DLY_MAX DQS bit20 input maximum delay
m. NT
1E005318 DQS_CAL_M DQS INPUT CALIBRATION per bit 27-34 0000000
AX_6 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_3_DLY_MAX DQS3_2_DLY_MAX
Type RO RO
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3_1_DLY_MAX DQS3_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
31:24 DQS3_3_DLY_MAX DQS bit27 input maximum delay
23:16 DQS3_2_DLY_MAX DQS bit26 input maximum delay
15:8 DQS3_1_DLY_MAX DQS bit25 input maximum delay
7:0 DQS3_0_DLY_MAX DQS bit24 input maximum delay
ase O
@ KC
1E00531C DQS_CAL_M DQS INPUT CALIBRATION per bit 31-28 0000000
AX_7 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_7_DLY_MAX DQS3_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3_5_DLY_MAX DQS3_4_DLY_MAX
Type RO RO
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS3_7_DLY_MAX DQS bit31 input maximum delay
To DI
23:16 DQS3_6_DLY_MAX DQS bit30 input maximum delay
15:8 DQS3_5_DLY_MAX DQS bit29 input maximum delay
7:0 DQS3_4_DLY_MAX DQS bit28 input maximum delay
R E
1E005350 DQICAL0 DQS INPUT CALIBRATION 0 0000000
M
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3_DLY_MAX DQ2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ1_DLY_MAX DQ0_DLY_MAX
Type RO RO
FO
PGMT7621_V.1.0_130607 Page 294 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
EO
Bit(s) Name Description
cn IA
30:24 DQ3_DLY_MAX DQ byte3 input maximum delay
22:16 DQ2_DLY_MAX DQ byte2 input maximum delay
14:8 DQ1_DLY_MAX DQ byte1 input maximum delay
6:0 DQ0_DLY_MAX DQ byte0 input maximum delay
m. NT
1E005354 DQICAL1 DQS INPUT CALIBRATION 1 0000000
0
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_DLY_MIN DQS2_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_DLY_MIN DQS0_DLY_MIN
Type RO RO
ccn NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:24 DQS3_DLY_MIN DQS3 input minimum delay
ase O
22:16 DQS2_DLY_MIN DQS2 input minimum delay
14:8 DQS1_DLY_MIN DQS1 input minimum delay
6:0 DQS0_DLY_MIN DQS0 input minimum delay
@ KC
1E005358 DQICAL2 DQS INPUT CALIBRATION 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
xia E
Name DQS3_DLY_MAX DQS2_DLY_MAX
Type RO RO
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_DLY_MAX DQS0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
30:24 DQS3_DLY_MAX DQS3 input maximum delay
22:16 DQS2_DLY_MAX DQS2 input maximum delay
R E
14:8 DQS1_DLY_MAX DQS1 input maximum delay
6:0 DQS0_DLY_MAX DQS0 input maximum delay
M
1E00535C DQICAL3 DQS INPUT CALIBRATION 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_DLY_AVG DQS2_DLY_AVG
Type RO RO
FO
PGMT7621_V.1.0_130607 Page 295 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name DQS1_DLY_AVG DQS0_DLY_AVG
Type RO RO
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:24 DQS3_DLY_AVG DQS3 input delay average
m. NT
22:16 DQS2_DLY_AVG DQS2 input delay average
14:8 DQS1_DLY_AVG DQS1 input delay average
6:0 DQS0_DLY_AVG DQS0 input delay average
.co IDE
1E005370 CMP_ERR CMP ERROR 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CMP_ERR[31:16]
Type RO
ccn NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMP_ERR[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
@ KC
31:0 CMP_ERR bitwise auto test fail
1E005374 DQSIENDLY DQS INPUT GATING DELAY VALUE 0000000
0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3IENDLY DQS2IENDLY
Type RO RO
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1IENDLY DQS0IENDLY
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
30:24 DQS3IENDLY DQS input gating delay for DQS3
22:16 DQS2IENDLY DQS input gating delay for DQS2
R E
14:8 DQS1IENDLY DQS input gating delay for DQS1
6:0 DQS0IENDLY DQS input gating delay for DQS0
M
1E00538C STBEN0 DQS RING COUNTER 0 0000000
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name STBEN0[31:16]
Type RO
FO
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MT7621 PROGRAMMING GUIDE
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NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name STBEN0[15:0]
Type RO
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit(s) Name Description
31:0 STBEN0 DQS0 ring counter
m. NT
1E005390 STBEN1 DQS RING COUNTER 1 0000000
3
.co IDE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name STBEN1[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STBEN1[15:0]
Type RO
ccn NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit(s) Name Description
31:0 STBEN1 DQS1 ring counter
ase O
@ KC
1E005394 STBEN2 DQS RING COUNTER 2 0000000
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name STBEN2[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STBEN2[15:0]
Type RO
ny AT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit(s) Name Description
31:0 STBEN2 DQS2 ring counter
To DI
1E005398 STBEN3 DQS RING COUNTER 3 0000000
3
R E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name STBEN3[31:16]
M
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STBEN3[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit(s) Name Description
FO
PGMT7621_V.1.0_130607 Page 297 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
31:0 STBEN3 DQS3 ring counter
US L
EO
cn IA
1E0053A0 DQSDLY0 DQS INPUT DELAY SETTING 0 0F0F0F0
F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. NT
Name DEL3DLY DEL2DLY
Type RO RO
Reset 0 0 0 1 1 1 1 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEL1DLY DEL0DLY
Type RO RO
.co IDE
Reset 0 0 0 1 1 1 1 0 0 0 1 1 1 1
Bit(s) Name Description
30:24 DEL3DLY DQS input delay for DQS3
22:16 DEL2DLY DQS input delay for DQS2
14:8 DEL1DLY DQS input delay for DQS1
ccn NF
6:0 DEL0DLY DQS input delay for DQS0
1E0053B8 SPCMDRESP SPECIAL COMMAND RESPONSE 0000030
ase O
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ KC
Name SR
EF_
ST
AT
E
Type RO
Reset 0
xia E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TC ZQ AR PR MR MR
MD C_ EF_ EA_ R_ W_
ny AT
_RE RE RE RE RE RE
REFRESH_RATE
SP SP SP SP SP SP
ON ON ON ON ON ON
SE SE SE SE SE SE
Type RO RO RO RO RO RO RO
Reset 0 1 1 0 0 0 0 0 0
To DI
Bit(s) Name Description
16 SREF_STATE Self-refresh status
0: not enter
R E
1: enter
10:8 REFRESH_RATE Refresh rate reading from LPDDR2
M
001: 4 x tREFI
010: 2 x tREFI
011: 1 x tREFI
101: 0.25 x tREFI
110: 2.25 x tREFI
Others: Refer to LPDDR2 spec.
5 TCMD_RESPONSE TCMD command response
4 ZQC_RESPONSE ZQC command response
3 AREF_RESPONSE AREF command response
FO
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MT7621 PROGRAMMING GUIDE
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NL
2 PREA_RESPONSE PREA command response
US L
1 MRR_RESPONSE MRR command response
EO
0 MRW_RESPONSE MRW command response
cn IA
1E0053BC IORGCNT IO RING COUNTER 0000000
m. NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name IO_RING_COUNTER
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co IDE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IO_RING_COUNTER_K
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 IO_RING_COUNTER 270 degree I/O clock offset counter for group 5
ccn NF
15:0 IO_RING_COUNTER_ 180 degree I/O clock offset counter for group 5
K
ase O
1E0053C0 DQSGNWCNT DQS GATING WINODW COUNTER 0 0000000
0 0
@ KC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs1r_gating_counter dqs1f_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs0r_gating_counter dqs0f_gating_counter
Type RO RO
xia E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ny AT
31:24 dqs1r_gating_counter rsing dqs gating counter for group 1
23:16 dqs1f_gating_counter falling dqs gating counter for group 1
15:8 dqs0r_gating_counter rsing dqs gating counter for group 0
7:0 dqs0f_gating_counter falling dqs gating counter for group 0
To DI
1E0053C4 DQSGNWCNT DQS GATING WINODW COUNTER 1 0000000
R E
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name dqs3r_gating_counter dqs3f_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs2r_gating_counter dqs2f_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO
PGMT7621_V.1.0_130607 Page 299 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Bit(s) Name Description
US L
31:24 dqs3r_gating_counter rsing dqs gating counter for group 3
EO
23:16 dqs3f_gating_counter falling dqs gating counter for group 3
cn IA
15:8 dqs2r_gating_counter rsing dqs gating counter for group 2
7:0 dqs2f_gating_counter falling dqs gating counter for group 2
m. NT
1E0053C8 DQSGNWCNT DQS GATING WINODW COUNTER 2 0000000
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs0r_pre_gating_counter dqs0f_pre_gating_counter
.co IDE
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs0r_pos_gating_counter dqs0f_pos_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit(s) Name Description
31:24 dqs0r_pre_gating_cou rsing pre dqs gating counter for group 0
nter
23:16 dqs0f_pre_gating_coun falling pre dqs gating counter for group 0
ase O
ter
15:8 dqs0r_pos_gating_cou rsing pos dqs gating counter for group 0
nter
@ KC
7:0 dqs0f_pos_gating_cou falling pos dqs gating counter for group 0
nter
1E0053CC DQSGNWCNT DQS GATING WINODW COUNTER 3 0000000
3 0
xia E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs1r_pre_gating_counter dqs1f_pre_gating_counter
ny AT
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs1r_pos_gating_counter dqs1f_pos_gating_counter
Type RO RO
Reset
To DI
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 dqs1r_pre_gating_cou rsing pre dqs gating counter for group 1
R E
nter
23:16 dqs1f_pre_gating_coun falling pre dqs gating counter for group 1
ter
M
15:8 dqs1r_pos_gating_cou rsing pos dqs gating counter for group 1
nter
7:0 dqs1f_pos_gating_cou falling pos dqs gating counter for group 1
nter
1E0053D0 DQSGNWCNT DQS GATING WINODW COUNTER 4 0000000
FO
PGMT7621_V.1.0_130607 Page 300 of 349
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MT7621 PROGRAMMING GUIDE
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4 0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name dqs2r_pre_gating_counter dqs2f_pre_gating_counter
Type RO RO
cn IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs2r_pos_gating_counter dqs2f_pos_gating_counter
Type RO RO
m. NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 dqs2r_pre_gating_cou rsing pre dqs gating counter for group 2
nter
.co IDE
23:16 dqs2f_pre_gating_coun falling pre dqs gating counter for group 2
ter
15:8 dqs2r_pos_gating_cou rsing pos dqs gating counter for group 2
nter
7:0 dqs2f_pos_gating_cou falling pos dqs gating counter for group 2
nter
ccn NF
1E0053D4 DQSGNWCNT DQS GATING WINODW COUNTER 5 0000000
5 0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs3r_pre_gating_counter dqs3f_pre_gating_counter
Type RO RO
@ KC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs3r_pos_gating_counter dqs3f_pos_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
31:24 dqs3r_pre_gating_cou rsing pre dqs gating counter for group 3
nter
ny AT
23:16 dqs3f_pre_gating_coun falling pre dqs gating counter for group 3
ter
15:8 dqs3r_pos_gating_cou rsing pos dqs gating counter for group 3
nter
7:0 dqs3f_pos_gating_cou falling pos dqs gating counter for group 3
To DI
nter
R E
1E0053D8 DQSSAMPLE DQS SAMPLE VALUE 0000000
V 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name sa sa sa sa
mpl mpl mpl mpl
CMPCNT e_o e_o e_o e_o
ut1 ut1 ut1 ut1
_D _D _D _D
FO
PGMT7621_V.1.0_130607 Page 301 of 349
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MT7621 PROGRAMMING GUIDE
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QS QS QS QS
US L
3 2 1 0
EO
Type RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0
cn IA
Bit(s) Name Description
9:4 CMPCNT CMP counter value
3 sample_out1_DQS3 Sampled value for DQS3
m. NT
0: late
1: early
2 sample_out1_DQS2 Sampled value for DQS2
0: late
1: early
.co IDE
1 sample_out1_DQS1 Sampled value for DQS1
0: late
1: early
0 sample_out1_DQS0 Sampled value for DQS0
0: late
1: early
ccn NF
1E0053DC DLLCNT0 DLL STATUS 0 0000000
0
ase O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CM
PO
@ KC
T
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
xia E
Bit(s) Name Description
ny AT
31 CMPOT CMP pad calibration result
1E0053E8 CKPHCNT CLOCK PHASE DETECTION RESULT 0000000
To DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
R E
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CKPHCHKCNT
M
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:0 CKPHCHKCNT MEMPLL in/out clock phase detection result counter
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
1E0053FC TESTRPT TEST AGENT STATUS 0000000
US L
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name CA
LI_ LB_ DLE
DO CM _CN
NE_ P_F T_O
MO AIL K
m. NT
N
Type RO RO RO
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DM DM
.co IDE
_C _C
MP MP WPAT_HIT_CNT
_ER _CP
R T
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
28 CALI_DONE_MON calibration result is updated, SW can disable calibration
24 LB_CMP_FAIL Loop-back test mode compare fail
18 DLE_CNT_OK DLE counter is right for test agent 2
14 DM_CMP_ERR Read data compare error for test agent 2
ase O
10 DM_CMP_CPT Read data compare ready for test agent 2
7:0 WPAT_HIT_CNT Write pattern hit counter. Clear by WPAT_STCLR (REG.1FC[20])
@ KC
1E005600 MEMPLL0 MEMPLL REGISTER SETTING 0 D000000
F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
xia E
Name RG RG
RG RG RG
RG _M _M
_M RG RG _M _M
_M EM EM
ny AT
RG_MEMP EM _M _M EM EM
EM PLL PLL
LL_FBDIV PLL EM EM PLL RG_MEMPLL_DIVEN PLL
PLL _LV _M
2 _A PLL PLL _F _M
_B RO ON
CC _LF _BP ME ON
R DE CK
EN N EN
N EN
Type RW RW RW RW RW RW RW RW RW RW
To DI
Reset 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG
_M _M
RG_MEMP RG_MEMP RG_MEMP
EM EM
R E
LL_POSDI LL_PREDI LL_CKCTR RG_MEMPLL_FBDIV
PLL PLL
V V L
_RS _P
T WD
M
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit(s) Name Description
31:30 RG_MEMPLL_FBDIV2 Feedback clock select
2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
FO
PGMT7621_V.1.0_130607 Page 303 of 349
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MT7621 PROGRAMMING GUIDE
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29 RG_MEMPLL_ACCEN Fast Slew Enable
US L
1'b0: Disable
EO
1'b1: Enable
28 RG_MEMPLL_LF Frequency Band Control
cn IA
always set 1
27 RG_MEMPLL_BR Resistance adjustment for Bandwidth
1'b0: BW = Fref/10
1'b1: BW = Fref/20
m. NT
26 RG_MEMPLL_BP Capacitance adjustment for Bandiwdth
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
25 RG_MEMPLL_FMEN PLL REF/FB monitor clock enable
1'b0: disable
.co IDE
1'b1: enable
24 RG_MEMPLL_LVROD REGV12 LVR overdrive enable
EN 1'b0: disable
1'b1: enable
23:18 RG_MEMPLL_DIVEN Time domain cap multiplication ratio
3'd0: x1
ccn NF 3'd1: x2
3'd6: x64
17 RG_MEMPLL_MONCK Monitor clock enable
EN 1'b0: Disable
1'b1: Enable
ase O
16 RG_MEMPLL_MONEN Control voltage monitor enable
1'b0: Disable
1'b1: Enable
@ KC
14 RG_MEMPLL_RST PLL reset control
1'b0: reset disable
1'b1: reset enable
13:12 RG_MEMPLL_POSDI Post-divider ratio for single-phase output
V 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
xia E
11:10 RG_MEMPLL_PREDIV Pre-divider ratio
2'b00: Fref = Fin/1
ny AT
2'b01: Fref = Fin/2
2'b11: Fref = Fin/4
9:8 RG_MEMPLL_CKCTR Fast Slew Time Control
L 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
2'b10: 2^7 * Tin
To DI
2'b11: 2^6 * Tin
7:1 RG_MEMPLL_FBDIV Feedback divide ratio
7'd0: /1
7'd1: /2
R E
7'd127: /128
0 RG_MEMPLL_PWD Power Down
M
1'b0: Power On
1'b1: Power Down
(toggle from 1->0 to initialize)
1E005604 MEMPLL1 MEMPLL REGISTER SETTING 1 C000000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO
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MT7621 PROGRAMMING GUIDE
Y
NL
Name RG_DMSS_PCW_NCPO[22:7]
US L
Type RW
EO
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cn IA
Name RG
_D
RG
MS
_M
S_P
RG_MEMP EM
CW
m. NT
RG_DMSS_PCW_NCPO[6:0] LL_RST_D PLL
_N
LY _V
CP
OD
O_
EN
CH
G
Type RW RW RW RW
.co IDE
Reset 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:9 RG_DMSS_PCW_NC DDS NCPO PCW
PO
8 RG_DMSS_PCW_NC DDS PCW change asynchrounous clock
ccn NF
PO_CHG
2:1 RG_MEMPLL_RST_D ICO reset signal
LY 2'b00: reset delay min
2'b11: reset delay max
0 RG_MEMPLL_VODEN CHP OverDrive Enable
ase O
1'b0: Disable
1'b1: Enable
@ KC
1E005608 MEMPLL2 MEMPLL REGISTER SETTING 2 4AC6001
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
RG RG RG
xia E
RG _D
_D _D _D
_D MS
MS MS MS
MS S_
RG_DMSS_SSC_DELTA1 S_S S_S RG_DMSS_PI_C S_P
ny AT
S_S MO
SC_ SC_ I_R
SC_ NC
PHI TRI ST_
EN K_E
NI _EN SEL
N
Type RW RW RW RW RW RW RW
Reset 0 1 0 0 1 0 1 0 1 1 0 0 0 1 1 0
To DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
_D
RG RG RG RG
RG MS RG RG
_D _D _D _M
_D S_F _D _D
R E
MS MS MS EM
MS IFO MS MS
S_P S_P S_N PLL RG_DMSS_PCW_NCPO
S_H _ST S_R S_P
I_P RE CP _D
F_E AR ST WD
M
L_E DIV O_ DS
N T_ B B
N 2 EN EN
MA
N
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
Bit(s) Name Description
31:24 RG_DMSS_SSC_DEL DDS SSC first spread disturbance amplitude
TA1
FO
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MT7621 PROGRAMMING GUIDE
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NL
23 RG_DMSS_SSC_PHI FNPLL SSC initial spreading direction
US L
NI 1'b0: Upward
EO
1'b1: Downward
22 RG_DMSS_SSC_TRI_ DDS SSC modulation type
cn IA
EN 1'b0: Square wave
1'b1: Triangular wave
21 RG_DMSS_SSC_EN DDS SSC enable
1'b0: Disable
m. NT
1'b1: Enable
20 RG_DMSS_MONCK_E DDS monitor clock enable
N 1'b0: Disable
1'b1: Enable
19:17 RG_DMSS_PI_C DMSS PI cap select
.co IDE
0: 165f
1: 150f
2: 135f
3: 120f
4: 105f
5: 90f
6: 75f
7: 60f
ccn NF
16 RG_DMSS_PI_RST_S DDS PI reset selection
EL 0:analog reset
1:digital reset
15 RG_DMSS_PI_PL_EN DDS PI pull low function enable bar
ase O
1'b0: Enable
1'b1: Disable
14 RG_DMSS_HF_EN DDS high frequency mode enable
@ KC
1'b0: When RG_LC_DDS_PREDIV2=1'b0
1'b1: When RG_LC_DDS_PREDIV2=1'b1
13 RG_DMSS_PREDIV2 DDS predivider
1'b0: /1
1'b1: /2
12 RG_DMSS_FIFO_STA DDS FIFO enable
RT_MAN 1'b0: Disable
xia E
1'b1: Enable
11 RG_DMSS_NCPO_EN DDS NCPO enable
ny AT
1'b0: Disable
1'b1: Enable
10 RG_DMSS_RSTB DDS NCPO reset bar
1'b0: Reset
1'b1: Enable
To DI
9 RG_DMSS_PWDB DDS power down bar
1'b0: Power down
1'b1: Power on
8 RG_MEMPLL_DDSEN PLL DDS feedback enable
R E
1'b0: Integer-N mode
1'b1: Fractional-N mode
7:0 RG_DMSS_PCW_NC DDS NCPO PCW
M
PO
1E00560C MEMPLL3 MEMPLL REGISTER SETTING 3 90004A0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_DMSS_SSC_PRD RG_DMSS_SSC_DELTA[15:8]
FO
PGMT7621_V.1.0_130607 Page 306 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
Type RW RW
Reset
US L
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_DMSS_SSC_DELTA[7:0] RG_DMSS_SSC_DELTA1
cn IA
Type RW RW
Reset 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
m. NT
31:24 RG_DMSS_SSC_PRD DDS SSC modulation period
23:8 RG_DMSS_SSC_DEL DDS SSC disturbance amplitude
TA
7:0 RG_DMSS_SSC_DEL DDS SSC first spread disturbance amplitude
TA1
.co IDE
1E005610 MEMPLL4 MEMPLL REGISTER SETTING 4 000D080
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ccn NF RG
_M
EM
RG_DMSS_REV PLL RG_MEMPLL_DIV
_DI
V_E
ase O
N
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
@ KC
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG RG
RG RG
_D _D _D
_D _D
MS MS MS
RG_DMSS_FRAC MS MS
S_L S_P S_C RG_DMSS_SSC_PRD
_MUTE S_S S_L
VR OS LK_
EL_ PF_
OD TDI PH_
EXT EN
EN V2 INV
xia E
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
ny AT
Bit(s) Name Description
31:24 RG_DMSS_REV dummy reg
23 RG_MEMPLL_DIV_EN Enable the Divider for (APLL+DDS)
22:16 RG_MEMPLL_DIV Control bits of Divider for (APLL+DDS)
To DI
RG_MEMPLL_DIV[6]=1: /1
RG_MEMPLL_DIV[5:0]: /(N+2)
15 RG_DMSS_LVRODEN REGV12 LVR overdrive enable
1'b0: disable
R E
1'b1: enable
14:12 RG_DMSS_FRAC_MU REV
TE
M
11 RG_DMSS_SEL_EXT DDS output pulse width
0: 1T
1: 2T
10 RG_DMSS_POSTDIV2 DMSS output clock div by 2
0: disable
1: enable
9 RG_DMSS_CLK_PH_I DMSS phase inverter
NV 0: normal
FO
PGMT7621_V.1.0_130607 Page 307 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1: inverter
US L
8 RG_DMSS_LPF_EN DMSS regualtor low pass filter enable
EO
0: disable
1: enable
cn IA
7:0 RG_DMSS_SSC_PRD DDS SSC modulation period
m. NT
1E005614 MEMPLL5 MEMPLL REGISTER SETTING 5 5000801
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG RG
RG RG
RG
RG RG RG _M _M
.co IDE
_M _M _M
_M _M _M EM EM
RG_MEMP EM EM EM
EM EM EM PLL PLL
LL2_FBDI PLL PLL RG_MEMPLL2_DIVEN PLL
PLL PLL PLL 2_L 2_M
V2 2_A 2_F 2_M
2_L 2_B 2_B VR ON
CC ME ON
F R P OD CK
EN N EN
EN EN
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
ccn NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
_M
RG RG
EM
_M _M
PLL RG_MEMP RG_MEMP RG_MEMP
EM EM
ase O
2_E LL2_POSD LL2_PRED LL2_CKCT RG_MEMPLL2_FBDIV
PLL PLL
XF IV IV RL
2_R 2_P
BDI
ST WD
V_E
@ KC
N
Type RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
Bit(s) Name Description
31:30 RG_MEMPLL2_FBDIV Feedback clock select
xia E
2 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
ny AT
29 RG_MEMPLL2_ACCE Fast Slew Enable
N 1'b0: Disable
1'b1: Enable
28 RG_MEMPLL2_LF Frequency Band Control
always set 1
To DI
27 RG_MEMPLL2_BR Resistance adjustment for Bandwidth
1'b0: BW = Fref/10
1'b1: BW = Fref/20
26 RG_MEMPLL2_BP Capacitance adjustment for Bandiwdth
R E
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
M
25 RG_MEMPLL2_FMEN PLL REF/FB monitor clock enable
1'b0: disable
1'b1: enable
24 RG_MEMPLL2_LVRO REGV12 LVR overdrive enable
DEN 1'b0: disable
1'b1: enable
23:18 RG_MEMPLL2_DIVEN Time domain cap multiplication ratio
3'd0: x1
3'd1: x2
FO
PGMT7621_V.1.0_130607 Page 308 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
3'd6: x64
US L
17 RG_MEMPLL2_MONC Monitor clock enable
EO
KEN 1'b0: Disable
1'b1: Enable
cn IA
16 RG_MEMPLL2_MONE Control voltage monitor enable
N 1'b0: Disable
1'b1: Enable
15 RG_MEMPLL2_EXFB Mux For Feeback clock
m. NT
DIV_EN 1'b0: VCO loop
2'b1:outer loop
14 RG_MEMPLL2_RST PLL reset control
1'b0: reset disable
1'b1: reset enable
.co IDE
13:12 RG_MEMPLL2_POSDI Post-divider ratio for single-phase output
V 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
11:10 RG_MEMPLL2_PREDI not use
V
9:8 RG_MEMPLL2_CKCT Fast Slew Time Control
ccn NF
RL 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
2'b10: 2^7 * Tin
2'b11: 2^6 * Tin
7:1 RG_MEMPLL2_FBDIV Feedback divide ratio
ase O
7'd0: /1
7'd1: /2
7'd127: /128
@ KC
0 RG_MEMPLL2_PWD Power Down
1'b0: Power On
1'b1: Power Down
(toggle from 1->0 to initialize)
xia E
1E005618 MEMPLL6 MEMPLL REGISTER SETTING 6 0000100
1
ny AT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_MEMPLL2_REV
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
To DI
Name RG
RG RG
_M
_M _M RG
EM
EM EM _M
PLL
RG_MEMP PLL RG_MEMP PLL RG_MEMP EM
2_L
R E
LL2_TEST 2_F LL2_M4PD 2_M RG_MEMPLL2_SEL_MON LL2_RST_ PLL
DO
_DIV B_ IV 8PD DLY 2_V
_LV
MC IVM OD
RO
M
K_S ON EN
DE
EL _EN
N
Type RW RW RW RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:16 RG_MEMPLL2_REV dummy reg
14:13 RG_MEMPLL2_TEST_ Monitor clock divider for testmode
FO
PGMT7621_V.1.0_130607 Page 309 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
DIV 2'b00: /1
2'b01: /2
US L
EO
2'b10: forbidden
2'b11: /4
cn IA
12 RG_MEMPLL2_FB_M Mux For Feeback clock
CK_SEL 1'b0: internal loop
2'b1:outer loop
11 RG_MEMPLL2_LDO_L REGV12 LVR overdrive enable
m. NT
VRODEN 1'b0: disable
1'b1: enable
10:9 RG_MEMPLL2_M4PDI Multi-phase divider ratio for 4-phase output
V 2'b00: VCO/2
2'b01: VCO/4
2'b10: VCO/8
.co IDE
8 RG_MEMPLL2_M8PDI
VMON_EN
7:3 RG_MEMPLL2_SEL_
MON
2:1 RG_MEMPLL2_RST_ ICO reset signal
DLY 2'b00: reset delay min
ccn NF 2'b11: reset delay max
0 RG_MEMPLL2_VODE CHP OverDrive Enable
N 1'b0: Disable
1'b1: Enable
ase O
1E00561C MEMPLL7 MEMPLL REGISTER SETTING 7 1300000
@ KC
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
_M
EM
RG_MEMPLL3_FBDIV RG_MEMPLL2_DL_REV
PLL
3_P
xia E
WD
Type RW RW RW
Reset 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
ny AT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_MEMPLL2_FB_DL RG_MEMPLL2_REF_DL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To DI
Bit(s) Name Description
31:25 RG_MEMPLL3_FBDIV Feedback divide ratio
7'd0: /1
7'd1: /2
R E
7'd127: /128
24 RG_MEMPLL3_PWD Power Down
M
1'b0: Power On
1'b1: Power Down
(toggle from 1->0 to initialize)
23:16 RG_MEMPLL2_DL_R REV reg
EV
15:8 RG_MEMPLL2_FB_DL MEMPLL2 skew adjust between reference clock and feedback clock
7:0 RG_MEMPLL2_REF_ MEMPLL2 skew adjust between reference clock and feedback clock
DL
FO
PGMT7621_V.1.0_130607 Page 310 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
US L
EO
1E005620 MEMPLL8 MEMPLL REGISTER SETTING 8 0150008
cn IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG RG RG
RG
RG RG RG _M
m. NT
_M _M _M
_M _M _M EM
RG_MEMP EM RG_MEMP EM EM
EM EM EM PLL
RG_MEMPLL3_SEL_MON LL3_RST_ PLL LL3_FBDI PLL PLL
PLL PLL PLL 3_L
DLY 3_V V2 3_A 3_F
3_L 3_B 3_B VR
OD CC ME
F R P OD
EN EN N
EN
.co IDE
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG
RG _M
_M RG
_M EM
EM _M
EM PLL RG_MEMP RG_MEMP RG_MEMP
PLL EM
RG_MEMPLL3_DIVEN PLL 3_E LL3_POSD LL3_PRED LL3_CKCT
ccn NF 3_M PLL
3_M XF IV IV RL
ON 3_R
ON BDI
CK ST
EN V_E
EN
N
Type RW RW RW RW RW RW RW RW
ase O
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit(s) Name Description
@ KC
31:27 RG_MEMPLL3_SEL_
MON
26:25 RG_MEMPLL3_RST_ ICO reset signal
DLY 2'b00: reset delay min
2'b11: reset delay max
24 RG_MEMPLL3_VODE CHP OverDrive Enable
xia E
N 1'b0: Disable
1'b1: Enable
23:22 RG_MEMPLL3_FBDIV Feedback clock select
ny AT
2 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
21 RG_MEMPLL3_ACCE Fast Slew Enable
N 1'b0: Disable
To DI
1'b1: Enable
20 RG_MEMPLL3_LF Frequency Band Control
always set 1
19 RG_MEMPLL3_BR Resistance adjustment for Bandwidth
R E
1'b0: BW = Fref/10
1'b1: BW = Fref/20
M
18 RG_MEMPLL3_BP Capacitance adjustment for Bandiwdth
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
17 RG_MEMPLL3_FMEN PLL REF/FB monitor clock enable
1'b0: disable
1'b1: enable
16 RG_MEMPLL3_LVRO REGV12 LVR overdrive enable
DEN 1'b0: disable
1'b1: enable
FO
PGMT7621_V.1.0_130607 Page 311 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
15:10 RG_MEMPLL3_DIVEN Time domain cap multiplication ratio
US L
3'd0: x1
EO
3'd1: x2
3'd6: x64
cn IA
9 RG_MEMPLL3_MONC Monitor clock enable
KEN 1'b0: Disable
1'b1: Enable
8 RG_MEMPLL3_MONE Control voltage monitor enable
m. NT
N 1'b0: Disable
1'b1: Enable
7 RG_MEMPLL3_EXFB Mux For Feeback clock
DIV_EN 1'b0: VCO loop
2'b1:outer loop
.co IDE
6 RG_MEMPLL3_RST PLL reset control
1'b0: reset disable
1'b1: reset enable
5:4 RG_MEMPLL3_POSDI Post-divider ratio for single-phase output
V 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
ccn NF
3:2 RG_MEMPLL3_PREDI not use
V
1:0 RG_MEMPLL3_CKCT Fast Slew Time Control
RL 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
ase O
2'b10: 2^7 * Tin
2'b11: 2^6 * Tin
@ KC
1E005624 MEMPLL9 MEMPLL REGISTER SETTING 9 0000001
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_MEMPLL3_REF_DL RG_MEMPLL3_REV[15:8]
xia E
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ny AT
Name RG
RG RG
_M
_M _M
EM
EM EM
PLL
RG_MEMP PLL RG_MEMP PLL
3_L
RG_MEMPLL3_REV[7:0] LL3_TEST 3_F LL3_M4PD 3_M
DO
To DI
_DIV B_ IV 8PD
_LV
MC IVM
RO
K_S ON
DE
EL _EN
N
Type RW RW RW RW RW RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
M
Bit(s) Name Description
31:24 RG_MEMPLL3_REF_ MEMPLL3 skew adjust between reference clock and feedback clock
DL
23:8 RG_MEMPLL3_REV dummy reg
6:5 RG_MEMPLL3_TEST_ Monitor clock divider for testmode
DIV 2'b00: /1
2'b01: /2
2'b10: forbidden
FO
PGMT7621_V.1.0_130607 Page 312 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
2'b11: /4
US L
4 RG_MEMPLL3_FB_M Mux For Feeback clock
EO
CK_SEL 1'b0: internal loop
2'b1:outer loop
cn IA
3 RG_MEMPLL3_LDO_L REGV12 LVR overdrive enable
VRODEN 1'b0: disable
1'b1: enable
2:1 RG_MEMPLL3_M4PDI Multi-phase divider ratio for 4-phase output
m. NT
V 2'b00: VCO/2
2'b01: VCO/4
2'b10: VCO/8
0 RG_MEMPLL3_M8PDI
VMON_EN
.co IDE
1E005628 MEMPLL10 MEMPLL REGISTER SETTING 10 8013000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
ccn NF
_M
RG RG
EM
_M _M
PLL RG_MEMP RG_MEMP RG_MEMP
EM EM
4_E LL4_POSD LL4_PRED LL4_CKCT RG_MEMPLL4_FBDIV
PLL PLL
XF IV IV RL
4_R 4_P
ase O
BDI
ST WD
V_E
N
Type RW RW RW RW RW RW RW
@ KC
Reset 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_MEMPLL3_DL_REV RG_MEMPLL3_FB_DL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
xia E
Bit(s) Name Description
31 RG_MEMPLL4_EXFB Mux For Feeback clock
DIV_EN 1'b0: VCO loop
ny AT
2'b1:outer loop
30 RG_MEMPLL4_RST PLL reset control
1'b0: reset disable
1'b1: reset enable
29:28 RG_MEMPLL4_POSDI Post-divider ratio for single-phase output
To DI
V 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
27:26 RG_MEMPLL4_PREDI not use
R E
V
25:24 RG_MEMPLL4_CKCT Fast Slew Time Control
M
RL 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
2'b10: 2^7 * Tin
2'b11: 2^6 * Tin
23:17 RG_MEMPLL4_FBDIV Feedback divide ratio
7'd0: /1
7'd1: /2
7'd127: /128
16 RG_MEMPLL4_PWD Power Down
FO
PGMT7621_V.1.0_130607 Page 313 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
1'b0: Power On
1'b1: Power Down
US L
EO
(toggle from 1->0 to initialize)
15:8 RG_MEMPLL3_DL_R REV reg
cn IA
EV
7:0 RG_MEMPLL3_FB_DL MEMPLL3 skew adjust between reference clock and feedback clock
m. NT
1E00562C MEMPLL11 MEMPLL REGISTER SETTING 11 1001500
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
.co IDE
RG RG
_M
_M _M RG
EM
EM EM _M
PLL
RG_MEMP PLL RG_MEMP PLL RG_MEMP EM
4_L
LL4_TEST 4_F LL4_M4PD 4_M RG_MEMPLL4_SEL_MON LL4_RST_ PLL
DO
_DIV B_ IV 8PD DLY 4_V
_LV
MC IVM OD
RO
K_S ON EN
DE
ccn NF EL _EN
N
Type RW RW RW RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG
RG RG RG
ase O
RG RG RG _M _M
_M _M _M
_M _M _M EM EM
RG_MEMP EM EM EM
EM EM EM PLL PLL
LL4_FBDI PLL PLL RG_MEMPLL4_DIVEN PLL
PLL PLL PLL 4_L 4_M
@ KC
V2 4_A 4_F 4_M
4_L 4_B 4_B VR ON
CC ME ON
F R P OD CK
EN N EN
EN EN
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
xia E
30:29 RG_MEMPLL4_TEST_ Monitor clock divider for testmode
DIV 2'b00: /1
ny AT
2'b01: /2
2'b10: forbidden
2'b11: /4
28 RG_MEMPLL4_FB_M Mux For Feeback clock
CK_SEL 1'b0: internal loop
2'b1:outer loop
To DI
27 RG_MEMPLL4_LDO_L REGV12 LVR overdrive enable
VRODEN 1'b0: disable
1'b1: enable
26:25 RG_MEMPLL4_M4PDI Multi-phase divider ratio for 4-phase output
R E
V 2'b00: VCO/2
2'b01: VCO/4
M
2'b10: VCO/8
24 RG_MEMPLL4_M8PDI
VMON_EN
23:19 RG_MEMPLL4_SEL_
MON
18:17 RG_MEMPLL4_RST_ ICO reset signal
DLY 2'b00: reset delay min
2'b11: reset delay max
FO
PGMT7621_V.1.0_130607 Page 314 of 349
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MT7621 PROGRAMMING GUIDE
Y
NL
16 RG_MEMPLL4_VODE CHP OverDrive Enable
US L
N 1'b0: Disable
EO
1'b1: Enable
15:14 RG_MEMPLL4_FBDIV Feedback clock select
cn IA
2 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
13 RG_MEMPLL4_ACCE Fast Slew Enable
m. NT
N 1'b0: Disable
1'b1: Enable
12 RG_MEMPLL4_LF Frequency Band Control
always set 1
11 RG_MEMPLL4_BR Resistance adjustment for Bandwidth
.co IDE
1'b0: BW = Fref/10
1'b1: BW = Fref/20
10 RG_MEMPLL4_BP Capacitance adjustment for Bandiwdth
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
9 RG_MEMPLL4_FMEN PLL REF/FB monitor clock enable
ccn NF 1'b0: disable
1'b1: enable
8 RG_MEMPLL4_LVRO REGV12 LVR overdrive enable
DEN 1'b0: disable
1'b1: enable
ase O
7:2 RG_MEMPLL4_DIVEN Time domain cap multiplication ratio
3'd0: x1
3'd1: x2
@ KC
3'd6: x64
1 RG_MEMPLL4_MONC Monitor clock enable
KEN 1'b0: Disable
1'b1: Enable
0 RG_MEMPLL4_MONE Control voltage monitor enable
N 1'b0: Disable
1'b1: Enable
xia E
ny AT
1E005630 MEMPLL12 MEMPLL REGISTER SETTING 12 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_MEMPLL4_FB_DL RG_MEMPLL4_REF_DL
To DI
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_MEMPLL4_REV
Type RW
R E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:24 RG_MEMPLL4_FB_DL MEMPLL4 skew adjust between reference clock and feedback clock
23:16 RG_MEMPLL4_REF_ MEMPLL4 skew adjust between reference clock and feedback clock
DL
15:0 RG_MEMPLL4_REV dummy reg
FO
PGMT7621_V.1.0_130607 Page 315 of 349
[email protected],time=2014-09-19 10:42:07,ip=218.17.61.76,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=ASEC International (H.K.) Limited 亞矽(香港)_RLT
MT7621 PROGRAMMING GUIDE
Y
NL
1E005634 MEMPLL13 MEMPLL REGISTER SETTING 13 02005B0
US L
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cn IA
Name RG
_M
EM
RG_MEMP RG_MEMP
PLL RG_MEMPLL_CK
LL_TEST_ LL_REFM RG_MEMPLL_MONSEL
_C MON_AMPADJ
m. NT
DIV ON
KM
ON
_PD
Type RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.co IDE
Name RG
RG
_M RG RG
_M RG
EM _M _M
EM _M
PLL EM EM
PLL EM
RG_MEMPLL_RE _RE PLL PLL
_LD PLL RG_MEMPLL4_DL_REV
FCK_SEL FC _BI _BI
O_L _SE
K_ AS_ AS_
VR L_C
ccn NF MO RS PW
OD K
NE T D
EN
N
Type RW RW RW RW RW RW RW
Reset 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0
ase O
Bit(s) Name Description
29:28 RG_MEMPLL_TEST_ Monitor clock divider for testmode
@ KC
DIV 2'b00: /1
2'b01: /2
2'b10: forbidden
2'b11: /4
27:26 RG_MEMPLL_REFMO Monitor clock for testmode
N 2'b01 Refernece clock
25 RG_MEMPLL_CKMON
xia E
_PD
24:22 RG_MEMPLL_CKMON
ny AT
_AMPADJ
21:17 RG_MEMPLL_MONSE
L
15 RG_MEMPLL_LDO_L REGV12 LVR overdrive enable
VRODEN 1'b0: disable
1'b1: enable
To DI
14 RG_MEMPLL_SEL_C Monitor clock for debug enable
K 1'b0: Disable
1'b1: Enable
R E
13:11 RG_MEMPLL_REFCK MEMPLL input clock selection
_SEL 000 : XTAL
001 : FNPLL+Divider
M
10 RG_MEMPLL_REFCK MEMPLL2/3/4 refck monitor enable
_MONEN 1'b0: disable
1'b1: enable
9 RG_MEMPLL_BIAS_R Constant-Gm Bias Reset
ST 1'b0: For performance
1'b1: Reset for Fast Power On
8 RG_MEMPLL_BIAS_P Constant-Gm Bias Power Down
WD 1'b0:Power On
FO
PGMT7621_V.1.0_130607 Page 316 of 349
[email protected],time=2014-09-19 10:42:07,ip=218.17.61.76,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=ASEC International (H.K.) Limited 亞矽(香港)_RLT
MT7621 PROGRAMMING GUIDE
Y
NL
1'b1: Power Down
US L
7:0 RG_MEMPLL4_DL_R REV reg
EO
EV
cn IA
1E005638 MEMPLL14 MEMPLL REGISTER SETTING 14 0000000
0
m. NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_MEMP
LL_TOP_R
EV[15:14]
Type RW
.co IDE
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_MEMPLL_TOP_REV[13:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ccn NF
17:2 RG_MEMPLL_TOP_R dummy reg
EV
ase O
1E005640 MEMPLL_DIVI MEMPLL DIVIDER REGISTER CONTROL 0000000
DER 3
@ KC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R_D
R_ R_
M1 R_ R_
DM DM
xia E
PLL DM DM
PLL ALL
_SY BY BY
2CL CL
NC_ P_P P_P
K_E K_E
ny AT
MO LL3 LL4
N N
DE
Type RW RW RW RW RW
Reset 0 0 0 1 1
Bit(s) Name Description
To DI
5 R_DMPLL2CLK_EN Enable 4-phase output clocks of PLL core 2
0: disable
1: enable
4 R_DMALLCLK_EN Enable 4-phase output clocks of all clocks
R E
0: disable
1: enable
M
2 R_DM1PLL_SYNC_M Synchronous mode under 1-PLL clock scheme
ODE 0: asynchronous mode
1: synchronous mode
1 R_DMBYP_PLL3 Bypass PLL core 3
0: not bypass
1: bypass
0 R_DMBYP_PLL4 Bypass PLL core 4
0: not bypass
FO
PGMT7621_V.1.0_130607 Page 317 of 349
[email protected],time=2014-09-19 10:42:07,ip=218.17.61.76,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=ASEC International (H.K.) Limited 亞矽(香港)_RLT
MT7621 PROGRAMMING GUIDE
Y
NL
1: bypass
US L
EO
cn IA
1E005644 VREF VREF setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
m. NT
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EN_ EN_
INTREF1_ INTREF1_ INTREF1_ INT INTREF0_ INTREF0_ INTREF0_ INT
.co IDE
REFN REFP DS RE REFN REFP DS RE
F1 F0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:14 INTREF1_REFN Fine tune Vref to lower level Control for internal VREF 1
ccn NF
00: weakest
11: strongest to lower level
13:12 INTREF1_REFP Fine tune Vref to higher level Control for internal VREF 1
00: weakest
11: strongest to higher level
ase O
11:10 INTREF1_DS Current consumption control for internal VREF 1
00: weakest
11: strongest current consumption
@ KC
8 EN_INTREF1 Internal VREF 1 Enalbe control
1 : enable
0 : disable
7:6 INTREF0_REFN Fine tune Vref to lower level Control for internal VREF 0
00: weakest
11: strongest to lower level
xia E
5:4 INTREF0_REFP Fine tune Vref to higher level Control for internal VREF 0
00: weakest
11: strongest to higher level
ny AT
3:2 INTREF0_DS Current consumption control for internal VREF 0
00: weakest
11: strongest current consumption
0 EN_INTREF0 Internal VREF 0 Enalbe control
1 : enable
To DI
0 : disable
R E
M
FO
PGMT7621_V.1.0_130607 Page 318 of 349
[email protected],time=2014-09-19 10:42:07,ip=218.17.61.76,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=ASEC International (H.K.) Limited 亞矽(香港)_RLT
MT7621 PROGRAMMING GUIDE
Y
NL
US L
2.16 RBUS Matrix and QoS Arbiter
EO
2.16.1 Features
cn IA
8 channel QoS Arbiter
Configurable Bandwidth and Duedate for each agent
QoS classifier can be programmed for RR, BW RR, Fixed Priority and QoS Arb
m. NT
2.16.2 Block Diagram
.co IDE
N requestors (N=8) Req#0 Req#1 Req#2 Req#7
TRTC TRTC TRTC TRTC N Meters
ccn NF
N Run time classifiers
(based on QoS type,
due date and color)
Classifier Classifier Classifier Classifier N Classifiers
ase O
M(=8) run time
@ KC
QoS types
M first
LCgd LSg ... LCg BEy stage arbiters
arbiter arbiter arbiter arbiter (N ports/arbiter)
1 second
xia E
8 to 1 Strict priority arbiter
stage arbiter
(based on service priority)
(M ports)
ny AT
N-port QoS Arbiter
To DI
Figure 2-9 QoS Arbitration Block Diagram
R E
M
FO
PGMT7621_V.1.0_130607 Page 319 of 349
[email protected],time=2014-09-19 10:42:07,ip=218.17.61.76,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=ASEC International (H.K.) Limited 亞矽(香港)_RLT
MT7621 PROGRAMMING GUIDE
Y
NL
2.16.3 Registers of QoS Control
US L
DMA_CFG_ARB Changes LOG
EO
cn IA
Revision Date Author Change Log
0.1 2012/10/5 Lancelot Initialization
0.2 2012/10/22 Lancelot Modify DMA debug message
m. NT
Module name: DMA_CFG_ARB Base address: (+1E000800h)
Address Name Widt Register Function
h
.co IDE
1E000800 DMA_ARB_CFG 32 DMA 8 to 1 arbiter setting
1E000804 DMA_AG_BW 32 DMA Channel BW/QoS_Type/DueDate Setting
1E000808 DMA_AG_MAP 32 DMA channel (AG) mapping
1E00080C DMA_ROUTE 32 DMA Routing
1E000810 DMA_DBG 32 DMA Debug
ccn NF
1E000814 DMA_STATE 32 DMA Debug State
1E000818 DMA_BW 32 DMA Bandwidth
1E00081C DMA_LAT 32 DMA Latency
1E000820 R2P_MONITOR 32 Rbus to Pbus monitor
ase O
1E000824 R2P_ERR_ADDR 32 Rbus to Pbus ERR address
@ KC
1E000800 DMA_ARB_C DMA 8 to 1 arbiter setting 04FAC6
FG 88
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name pre
clas
em trtc
s_e cls_priority[23:16]
xia E
pt_ _en
n
en
Type RW RW RW RW
ny AT
Reset 1 0 0 1 1 1 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cls_priority[15:0]
Type RW
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