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21EC63 Model Question Paper

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4K views3 pages

21EC63 Model Question Paper

Uploaded by

DARSHAN DARSH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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21EC63

Model Question Paper-1/2 with effect from 2022-23 (CBCS Scheme)


USN

Sixth Semester B.E. Degree Examination


VLSI Design and Testing (21EC63)

TIME: 03 Hours Max. Marks: 100

Note: 01. Answer any FIVE full questions, choosing at least ONE question from each MODULE.

*Bloom’s
Module -1 Taxonomy Marks
Level
Q.01 a With necessary circuit diagram explain the operation of tristate inverter. L3 08
Also realize 2:1 mux using tristate inverter.
b Realize the CMOS gate for the following function Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
A(B + C) + DE L3 05

c Implement a D flipflop using transmission gate and explain its operation L3 07


with necessary timing diagram
OR
Q.02 a Draw the circuit diagram of a CMOS inverter and with the help of its L3 10
transfer characteristics, explain various regions of operation and derive the
Vout equation for Region C.
b Derive the equation for drain current of a MOSFET in non-saturated and L3 06
saturated region of operation.
c Compute the output voltage Vout in the pass transistor circuit shown in L3 04
Fig.1

Fig.1
Module-2
Q. 03 a Explain the various steps in CMOS n-well process with necessary L3 10
diagrams.
b With neat diagrams, explain the lambda design rules for wires, contact cuts and L3 06
Transistors.
c Draw the stick diagram for the function 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵𝐶 + 𝐷 L3 04

OR
Q.04 a Construct necessary equivalent circuits using RC delay model to compute the L3 10
propagation delay of 3-input NAND Gate.
b Make use of necessary waveforms to define the following terms (i) Propagation L3 06
delay (ii) Contamination delay (iii)Rise time (iv) Fall time (v) Edge rate.
c Make use of necessary circuit diagrams to compute logical effort of the following L3 04
gates. (i)2-input NOR gate and (ii)3-input NAND Gate.
Module-3

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21EC63
Q. 05 a Make use of necessary circuit diagram explain the operation of three L3 10
transistor DRAM cell.
b Explain the operation of full CMOS SRAM cell with necessary topology. L3 10
OR
Q. 06 a Explain the operation of 4*4 NAND based ROM array with necessary L3 08
circuit diagram.
b With necessary circuit diagram explain the operation of NOR flash L3 08
memory cell with bias conditions.
c Explain the hysteresis characteristics of ferroelectric capacitor with L3 04
necessary diagram.
Module-4
Q. 07 a Differentiate between fault and failure with an example. Explain different L3 05
types of stuck at faults with example.
b For the circuit shown in Fig.2 using Boolean difference (i) detect s@0 and L4 10
s@1 at x2, (ii) determine partial Boolean difference for x2-l-n-p-F.

Fig.2
c . Explain stuck open faults in CMOS circuits with an example. L3 05
OR
Q. 08 a What is fault diagnosis? Explain one dimensional path sensitization L3 08
technique for combinational circuits with an example.
b Find the test pattern for line 6 s@0 for the circuit shown in Fig.3 using D L4 12
Algorithm.

Fig.3
Module-5
Q. 09 a For the state table shown in Table.1 find (i)Response for 101 sequence, L4 10
(ii) Homing tree, (iii) Distinguishing tree.

Table 1
b Explain the various phases involved in checking experiment based on L3 05
sequential circuit structure.

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21EC63
c Explain the process of testing sequential circuit as iterative combinational L3 05
circuits.
OR
Q. 10 a Define the terms controllability and observability with an example. L3 06
b With a neat logic diagram, explain clocked hazard free latches used in LSSD L3 08
Technique.
c Explain any two Adhoc design rules for improving testability. L3 06

Page 03 of 02

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